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Stefan Roesee463bf32015-01-19 11:33:42 +01001/*
Stefan Roese44e7ebd2016-01-07 14:09:09 +01002 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
Stefan Roesee463bf32015-01-19 11:33:42 +01003 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
Stefan Roese83097cf2015-11-25 07:37:00 +01008#include <dm.h>
9#include <debug_uart.h>
10#include <fdtdec.h>
Stefan Roesee463bf32015-01-19 11:33:42 +010011#include <spl.h>
12#include <asm/io.h>
13#include <asm/arch/cpu.h>
14#include <asm/arch/soc.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
Stefan Roese44e7ebd2016-01-07 14:09:09 +010018static u32 get_boot_device(void)
Stefan Roesee463bf32015-01-19 11:33:42 +010019{
Stefan Roese44e7ebd2016-01-07 14:09:09 +010020 u32 val;
21 u32 boot_device;
22
Stefan Roese04ec0d32016-01-07 14:12:04 +010023 /*
24 * First check, if UART boot-mode is active. This can only
25 * be done, via the bootrom error register. Here the
26 * MSB marks if the UART mode is active.
27 */
28 val = readl(CONFIG_BOOTROM_ERR_REG);
29 boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
30 debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
31 if (boot_device == BOOTROM_ERR_MODE_UART)
32 return BOOT_DEVICE_UART;
33
34 /*
35 * Now check the SAR register for the strapped boot-device
36 */
Stefan Roese44e7ebd2016-01-07 14:09:09 +010037 val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
38 boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
Stefan Roese04ec0d32016-01-07 14:12:04 +010039 debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
Stefan Roese44e7ebd2016-01-07 14:09:09 +010040 switch (boot_device) {
41#ifdef CONFIG_SPL_MMC_SUPPORT
42 case BOOT_FROM_MMC:
43 case BOOT_FROM_MMC_ALT:
44 return BOOT_DEVICE_MMC1;
Stefan Roese63962132015-07-20 11:20:36 +020045#endif
Stefan Roese44e7ebd2016-01-07 14:09:09 +010046 case BOOT_FROM_UART:
47 return BOOT_DEVICE_UART;
48 case BOOT_FROM_SPI:
49 default:
50 return BOOT_DEVICE_SPI;
51 };
52}
53
54u32 spl_boot_device(void)
55{
56 return get_boot_device();
Stefan Roese63962132015-07-20 11:20:36 +020057}
58
59#ifdef CONFIG_SPL_MMC_SUPPORT
60u32 spl_boot_mode(void)
61{
62 return MMCSD_MODE_RAW;
Stefan Roesee463bf32015-01-19 11:33:42 +010063}
Stefan Roese63962132015-07-20 11:20:36 +020064#endif
Stefan Roesee463bf32015-01-19 11:33:42 +010065
66void board_init_f(ulong dummy)
67{
Stefan Roese83097cf2015-11-25 07:37:00 +010068 int ret;
69
Stefan Roesed7f2c122015-04-17 18:13:06 +020070 /*
71 * Pin muxing needs to be done before UART output, since
72 * on A38x the UART pins need some re-muxing for output
73 * to work.
74 */
75 board_early_init_f();
76
Stefan Roese83097cf2015-11-25 07:37:00 +010077 /* Example code showing how to enable the debug UART on MVEBU */
78#ifdef EARLY_UART
79 /*
80 * Debug UART can be used from here if required:
81 *
82 * debug_uart_init();
83 * printch('a');
84 * printhex8(0x1234);
85 * printascii("string");
86 */
87#endif
88
89 ret = spl_init();
90 if (ret) {
91 debug("spl_init() failed: %d\n", ret);
92 hang();
93 }
94
95 /* Use special translation offset for SPL */
96 dm_set_translation_offset(0xd0000000 - 0xf1000000);
97
Stefan Roesee463bf32015-01-19 11:33:42 +010098 preloader_console_init();
99
Stefan Roesed04fe8b2015-07-15 15:36:52 +0200100 timer_init();
101
Stefan Roesee463bf32015-01-19 11:33:42 +0100102 /* First init the serdes PHY's */
103 serdes_phy_config();
104
105 /* Setup DDR */
106 ddr3_init();
107
Stefan Roese99b3ea72015-08-25 13:49:41 +0200108 /*
109 * Return to the BootROM to continue the Marvell xmodem
110 * UART boot protocol. As initiated by the kwboot tool.
111 *
112 * This can only be done by the BootROM and not by the
113 * U-Boot SPL infrastructure, since the beginning of the
114 * image is already read and interpreted by the BootROM.
115 * SPL has no chance to receive this information. So we
116 * need to return to the BootROM to enable this xmodem
117 * UART download.
118 */
Stefan Roese04ec0d32016-01-07 14:12:04 +0100119 if (get_boot_device() == BOOT_DEVICE_UART)
120 return_to_bootrom();
Stefan Roesee463bf32015-01-19 11:33:42 +0100121}