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Stefan Roesee373c5f2009-01-21 17:24:49 +01001/*
2 * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
3 *
4 * Copyright (C) 2006 Micronas GmbH
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Stefan Roesee373c5f2009-01-21 17:24:49 +01007 */
8
9#include <common.h>
10#include <command.h>
Ben Warrenfbfdd3a2009-07-20 22:01:11 -070011#include <netdev.h>
Stefan Roesee373c5f2009-01-21 17:24:49 +010012#include <asm/mipsregs.h>
13#include "vct.h"
14
15#if defined(CONFIG_VCT_PREMIUM)
16#define BOARD_NAME "PremiumD"
17#elif defined(CONFIG_VCT_PLATINUM)
18#define BOARD_NAME "PlatinumD"
19#elif defined(CONFIG_VCT_PLATINUMAVC)
20#define BOARD_NAME "PlatinumAVC"
21#else
22#error "vct: No board variant defined!"
23#endif
24
25#if defined(CONFIG_VCT_ONENAND)
26#define BOARD_NAME_ADD " OneNAND"
27#else
28#define BOARD_NAME_ADD " NOR"
29#endif
30
31int board_early_init_f(void)
32{
33 /*
34 * First initialize the PIN mulitplexing
35 */
36 vct_pin_mux_initialize();
37
38 /*
39 * Init the EBI very early so that FLASH can be accessed
40 */
41 ebi_initialize();
42
43 return 0;
44}
45
46void _machine_restart(void)
47{
48 reg_write(DCGU_EN_WDT_RESET(DCGU_BASE), DCGU_MAGIC_WDT);
49 reg_write(WDT_TORR(WDT_BASE), 0x00);
50 reg_write(WDT_CR(WDT_BASE), 0x1D);
51
52 /*
53 * Now wait for the watchdog to trigger the reset
54 */
55 udelay(1000000);
56}
57
58/*
59 * SDRAM is already configured by the bootstrap code, only return the
60 * auto-detected size here
61 */
62phys_size_t initdram(int board_type)
63{
64 return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
65 CONFIG_SYS_MBYTES_SDRAM << 20);
66}
67
68int checkboard(void)
69{
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +000070 char buf[64];
71 int i = getenv_f("serial#", buf, sizeof(buf));
Stefan Roesee373c5f2009-01-21 17:24:49 +010072 u32 config0 = read_c0_prid();
Stefan Roesee373c5f2009-01-21 17:24:49 +010073
74 if ((config0 & 0xff0000) == PRID_COMP_LEGACY
75 && (config0 & 0xff00) == PRID_IMP_LX4280) {
76 puts("Board: MDED \n");
77 printf("CPU: LX4280 id: 0x%02x, rev: 0x%02x\n",
78 (config0 >> 8) & 0xFF, config0 & 0xFF);
79 } else if ((config0 & 0xff0000) == PRID_COMP_MIPS
80 && (config0 & 0xff00) == PRID_IMP_VGC) {
81 u32 jedec_id = *((u32 *) 0xBEBC71A0);
82 if ((((jedec_id) >> 12) & 0xFF) == 0x40) {
83 puts("Board: VGCA \n");
84 } else if ((((jedec_id) >> 12) & 0xFF) == 0x48
85 || (((jedec_id) >> 12) & 0xFF) == 0x49) {
86 puts("Board: VGCB \n");
87 }
88 printf("CPU: MIPS 4K id: 0x%02x, rev: 0x%02x\n",
89 (config0 >> 8) & 0xFF, config0 & 0xFF);
90 } else if (config0 == 0x19378) {
91 printf("CPU: MIPS 24K id: 0x%02x, rev: 0x%02x\n",
92 (config0 >> 8) & 0xFF, config0 & 0xFF);
93 } else {
94 printf("Unsupported cpu %d, proc_id=0x%x\n", config0 >> 24,
95 config0);
96 }
97
98 printf("Board: Micronas VCT " BOARD_NAME BOARD_NAME_ADD);
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +000099 if (i > 0) {
Stefan Roesee373c5f2009-01-21 17:24:49 +0100100 puts(", serial# ");
Wolfgang Denk5c1cfee2011-05-04 10:32:28 +0000101 puts(buf);
Stefan Roesee373c5f2009-01-21 17:24:49 +0100102 }
103 putc('\n');
104
105 return 0;
106}
Ben Warrenfbfdd3a2009-07-20 22:01:11 -0700107
108int board_eth_init(bd_t *bis)
109{
110 int rc = 0;
111#ifdef CONFIG_SMC911X
112 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
113#endif
114 return rc;
115}