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git01.mediatek.com / filogic / uboot / eb87d461db49f8bcdcd07b7b6610afd7279cd3a9 / . / arch / arm / dts / imx8mp-evk-u-boot.dtsi
blob: 0bf489b46248c87ebd317bd52903fd0f9b1ed827 [file] [log] [blame]
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]3 * Copyright 2019, 2021 NXP
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]4 */
5
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]6#include "imx8mp-u-boot.dtsi"
Peng Fand96d94b2021-04-06 11:59:02 +0800[diff] [blame]7
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]8/ {
Marek Vasut797a19a2020-04-29 15:04:26 +0200[diff] [blame]9 wdt-reboot {
10 compatible = "wdt-reboot";
11 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]12 bootph-pre-ram;
Marek Vasut797a19a2020-04-29 15:04:26 +0200[diff] [blame]13 };
14};
15
Fabio Estevam4671ab42023-10-18 16:17:41 -0300[diff] [blame]16&pinctrl_i2c1 {
17 bootph-all;
18};
19
20&pinctrl_pmic {
21 bootph-all;
22};
23
24&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
25 bootph-all;
26};
27
28&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
29 bootph-all;
30};
31
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]32&reg_usdhc2_vmmc {
Andrey Zhizhikincf51a552020-12-05 17:29:17 +0000[diff] [blame]33 u-boot,off-on-delay-us = <20000>;
34};
35
36&reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]38};
39
40&pinctrl_uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]42};
43
44&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]46};
47
48&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]50};
51
52&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]54};
55
Peng Fane22df442022-05-05 19:05:59 +0800[diff] [blame]56&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]57 bootph-pre-ram;
Peng Fane22df442022-05-05 19:05:59 +0800[diff] [blame]58};
59
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]60&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]62};
63
64&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]66};
67
68&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]70};
71
72&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]73 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]74};
75
76&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]78};
79
80&uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]82};
83
84&i2c1 {
Fabio Estevam4671ab42023-10-18 16:17:41 -0300[diff] [blame]85 bootph-all;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]86};
87
88&i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]90};
91
92&i2c3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]93 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]94};
95
96&i2c4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]97 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]98};
99
100&i2c5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]102};
103
104&i2c6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]105 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]106};
107
Fabio Estevambcde1972023-10-15 21:24:37 -0300[diff] [blame]108&usb_dwc3_0 {
109 dr_mode = "peripheral";
110 status = "okay";
111};
112
113&usb3_0 {
114 status = "okay";
115};
116
117&usb3_phy0 {
118 status = "okay";
119};
120
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]121&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]122 bootph-pre-ram;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]123};
124
125&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]126 bootph-pre-ram;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]127 sd-uhs-sdr104;
128 sd-uhs-ddr50;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]129};
130
131&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]132 bootph-pre-ram;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]133 mmc-hs400-1_8v;
134 mmc-hs400-enhanced-strobe;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]135};
Marek Vasut797a19a2020-04-29 15:04:26 +0200[diff] [blame]136
137&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]138 bootph-pre-ram;
Marek Vasut797a19a2020-04-29 15:04:26 +0200[diff] [blame]139};
Peng Fan4f0c97b2020-12-25 16:16:34 +0800[diff] [blame]140
Ye Li25804942021-08-16 18:44:28 +0800[diff] [blame]141&ethphy0 {
142 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
143 reset-delay-us = <15000>;
144 reset-post-delay-us = <100000>;
145};
146
Peng Fan4f0c97b2020-12-25 16:16:34 +0800[diff] [blame]147&fec {
148 phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
Ye Lid1b82062021-02-18 22:33:48 -0800[diff] [blame]149 phy-reset-duration = <15>;
150 phy-reset-post-delay = <100>;
Peng Fan4f0c97b2020-12-25 16:16:34 +0800[diff] [blame]151};
Peng Fand96d94b2021-04-06 11:59:02 +0800[diff] [blame]152
Peng Fand96d94b2021-04-06 11:59:02 +0800[diff] [blame]153