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Stefan Roese76ba23f2014-11-07 14:10:41 +01001/*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 *
Stefan Roesed3b436e2014-11-14 08:10:44 +01004 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese76ba23f2014-11-07 14:10:41 +01005 */
6
7/dts-v1/;
8/* First 4KB has trampoline code for secondary cores. */
9/memreserve/ 0x00000000 0x0001000;
10#include "socfpga.dtsi"
11
12/ {
13 soc {
14 clkmgr@ffd04000 {
15 clocks {
16 osc1 {
17 clock-frequency = <25000000>;
18 };
19 };
20 };
21
22 mmc0: dwmmc0@ff704000 {
23 num-slots = <1>;
24 broken-cd;
25 bus-width = <4>;
26 cap-mmc-highspeed;
27 cap-sd-highspeed;
Chin Liang Seed6391a82015-11-26 09:44:11 +080028 drvsel = <3>;
29 smplsel = <0>;
Stefan Roese76ba23f2014-11-07 14:10:41 +010030 };
31
Stefan Roese76ba23f2014-11-07 14:10:41 +010032 sysmgr@ffd08000 {
33 cpu1-start-addr = <0xffd080c4>;
34 };
35 };
36};