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git01.mediatek.com / filogic / uboot / eb7131158325b4de6a7a4db17c4b65ebef1f325d / . / drivers / pinctrl / renesas / pfc-r8a77951.c
blob: 8ddcbfbbd64f905a2f52618472219491a6a7a737 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2/*
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3 * R8A77951 processor support - PFC hardware block.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4 *
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5 * Copyright (C) 2015-2019 Renesas Electronics Corporation
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6 */
7
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]8#include <dm.h>
9#include <errno.h>
10#include <dm/pinctrl.h>
11#include <linux/kernel.h>
12
13#include "sh_pfc.h"
14
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]15#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]16
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]17#define CPU_ALL_GP(fn, sfx) \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]18 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]19 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]20 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
Marek Vasut14dfdd62023-09-17 16:08:40 +0200[diff] [blame]21 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]22 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
Marek Vasut14dfdd62023-09-17 16:08:40 +0200[diff] [blame]26 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]27 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]30
31#define CPU_ALL_NOGP(fn) \
32 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
33 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
34 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
35 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
36 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
37 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
38 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
39 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
40 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
52 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
70 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
71 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
72 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
73 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
74 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
75
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]76/*
77 * F_() : just information
78 * FM() : macro for FN_xxx / xxx_MARK
79 */
80
81/* GPSR0 */
82#define GPSR0_15 F_(D15, IP7_11_8)
83#define GPSR0_14 F_(D14, IP7_7_4)
84#define GPSR0_13 F_(D13, IP7_3_0)
85#define GPSR0_12 F_(D12, IP6_31_28)
86#define GPSR0_11 F_(D11, IP6_27_24)
87#define GPSR0_10 F_(D10, IP6_23_20)
88#define GPSR0_9 F_(D9, IP6_19_16)
89#define GPSR0_8 F_(D8, IP6_15_12)
90#define GPSR0_7 F_(D7, IP6_11_8)
91#define GPSR0_6 F_(D6, IP6_7_4)
92#define GPSR0_5 F_(D5, IP6_3_0)
93#define GPSR0_4 F_(D4, IP5_31_28)
94#define GPSR0_3 F_(D3, IP5_27_24)
95#define GPSR0_2 F_(D2, IP5_23_20)
96#define GPSR0_1 F_(D1, IP5_19_16)
97#define GPSR0_0 F_(D0, IP5_15_12)
98
99/* GPSR1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]100#define GPSR1_28 FM(CLKOUT)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]101#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
102#define GPSR1_26 F_(WE1_N, IP5_7_4)
103#define GPSR1_25 F_(WE0_N, IP5_3_0)
104#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
105#define GPSR1_23 F_(RD_N, IP4_27_24)
106#define GPSR1_22 F_(BS_N, IP4_23_20)
107#define GPSR1_21 F_(CS1_N, IP4_19_16)
108#define GPSR1_20 F_(CS0_N, IP4_15_12)
109#define GPSR1_19 F_(A19, IP4_11_8)
110#define GPSR1_18 F_(A18, IP4_7_4)
111#define GPSR1_17 F_(A17, IP4_3_0)
112#define GPSR1_16 F_(A16, IP3_31_28)
113#define GPSR1_15 F_(A15, IP3_27_24)
114#define GPSR1_14 F_(A14, IP3_23_20)
115#define GPSR1_13 F_(A13, IP3_19_16)
116#define GPSR1_12 F_(A12, IP3_15_12)
117#define GPSR1_11 F_(A11, IP3_11_8)
118#define GPSR1_10 F_(A10, IP3_7_4)
119#define GPSR1_9 F_(A9, IP3_3_0)
120#define GPSR1_8 F_(A8, IP2_31_28)
121#define GPSR1_7 F_(A7, IP2_27_24)
122#define GPSR1_6 F_(A6, IP2_23_20)
123#define GPSR1_5 F_(A5, IP2_19_16)
124#define GPSR1_4 F_(A4, IP2_15_12)
125#define GPSR1_3 F_(A3, IP2_11_8)
126#define GPSR1_2 F_(A2, IP2_7_4)
127#define GPSR1_1 F_(A1, IP2_3_0)
128#define GPSR1_0 F_(A0, IP1_31_28)
129
130/* GPSR2 */
131#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
132#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
133#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
134#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
135#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
136#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
137#define GPSR2_8 F_(PWM2_A, IP1_27_24)
138#define GPSR2_7 F_(PWM1_A, IP1_23_20)
139#define GPSR2_6 F_(PWM0, IP1_19_16)
140#define GPSR2_5 F_(IRQ5, IP1_15_12)
141#define GPSR2_4 F_(IRQ4, IP1_11_8)
142#define GPSR2_3 F_(IRQ3, IP1_7_4)
143#define GPSR2_2 F_(IRQ2, IP1_3_0)
144#define GPSR2_1 F_(IRQ1, IP0_31_28)
145#define GPSR2_0 F_(IRQ0, IP0_27_24)
146
147/* GPSR3 */
148#define GPSR3_15 F_(SD1_WP, IP11_23_20)
149#define GPSR3_14 F_(SD1_CD, IP11_19_16)
150#define GPSR3_13 F_(SD0_WP, IP11_15_12)
151#define GPSR3_12 F_(SD0_CD, IP11_11_8)
152#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
153#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
154#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
155#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
156#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
157#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
158#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
159#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
160#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
161#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
162#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
163#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
164
165/* GPSR4 */
166#define GPSR4_17 F_(SD3_DS, IP11_7_4)
167#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
168#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
169#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
170#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
171#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
172#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
173#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
174#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
175#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
176#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
177#define GPSR4_6 F_(SD2_DS, IP9_27_24)
178#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
179#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
180#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
181#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
182#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
183#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
184
185/* GPSR5 */
186#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
187#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
188#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
189#define GPSR5_22 FM(MSIOF0_RXD)
190#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
191#define GPSR5_20 FM(MSIOF0_TXD)
192#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
193#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
194#define GPSR5_17 FM(MSIOF0_SCK)
195#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
196#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
197#define GPSR5_14 F_(HTX0, IP13_19_16)
198#define GPSR5_13 F_(HRX0, IP13_15_12)
199#define GPSR5_12 F_(HSCK0, IP13_11_8)
200#define GPSR5_11 F_(RX2_A, IP13_7_4)
201#define GPSR5_10 F_(TX2_A, IP13_3_0)
202#define GPSR5_9 F_(SCK2, IP12_31_28)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]203#define GPSR5_8 F_(RTS1_N, IP12_27_24)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]204#define GPSR5_7 F_(CTS1_N, IP12_23_20)
205#define GPSR5_6 F_(TX1_A, IP12_19_16)
206#define GPSR5_5 F_(RX1_A, IP12_15_12)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]207#define GPSR5_4 F_(RTS0_N, IP12_11_8)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]208#define GPSR5_3 F_(CTS0_N, IP12_7_4)
209#define GPSR5_2 F_(TX0, IP12_3_0)
210#define GPSR5_1 F_(RX0, IP11_31_28)
211#define GPSR5_0 F_(SCK0, IP11_27_24)
212
213/* GPSR6 */
214#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
215#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
216#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
217#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
218#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
219#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
220#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
221#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
222#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
223#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
224#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
225#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
226#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
227#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
228#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
229#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
230#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
231#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
232#define GPSR6_13 FM(SSI_SDATA5)
233#define GPSR6_12 FM(SSI_WS5)
234#define GPSR6_11 FM(SSI_SCK5)
235#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
236#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
237#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
238#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
239#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
240#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
241#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
242#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
243#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
244#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]245#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]246
247/* GPSR7 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]248#define GPSR7_3 FM(GP7_03)
249#define GPSR7_2 FM(GP7_02)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]250#define GPSR7_1 FM(AVS2)
251#define GPSR7_0 FM(AVS1)
252
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]253/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
254#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]259#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]260#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]263#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]269#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273
274/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
275#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]281#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]282#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]297#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]298#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]310#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]311#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316
317/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
318#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348
349/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
350#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]357#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]358#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]361#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]362#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
371#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378
379/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
380#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]397#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]398#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
400#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
401#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
402#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
403#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
404#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
405#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
406#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
407
408#define PINMUX_GPSR \
409\
410 GPSR6_31 \
411 GPSR6_30 \
412 GPSR6_29 \
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]413 GPSR1_28 GPSR6_28 \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]414 GPSR1_27 GPSR6_27 \
415 GPSR1_26 GPSR6_26 \
416 GPSR1_25 GPSR5_25 GPSR6_25 \
417 GPSR1_24 GPSR5_24 GPSR6_24 \
418 GPSR1_23 GPSR5_23 GPSR6_23 \
419 GPSR1_22 GPSR5_22 GPSR6_22 \
420 GPSR1_21 GPSR5_21 GPSR6_21 \
421 GPSR1_20 GPSR5_20 GPSR6_20 \
422 GPSR1_19 GPSR5_19 GPSR6_19 \
423 GPSR1_18 GPSR5_18 GPSR6_18 \
424 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
425 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
426GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
427GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
428GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
429GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
430GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
431GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
432GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
433GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
434GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
435GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
436GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
437GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
438GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
439GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
440GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
441GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
442
443#define PINMUX_IPSR \
444\
445FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
446FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
447FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
448FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
449FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
450FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
451FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
452FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
453\
454FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
455FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
456FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
457FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
458FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
459FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
460FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
461FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
462\
463FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
464FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
465FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
466FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
467FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
468FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
469FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
470FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
471\
472FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
473FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
474FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
475FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
476FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
477FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
478FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
479FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
480\
481FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
482FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
483FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
484FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
485FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
486FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
487FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
488FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
489
490/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
491#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
492#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
493#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
494#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
495#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
496#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
497#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
498#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
499#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
500#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
501#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
502#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
503#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
504#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
505#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
506#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
507#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]508#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]509
510/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
511#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
512#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
513#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
514#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
515#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]516#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]517#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
518#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
519#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
520#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
521#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
522#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
523#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
524#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
525#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
526#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
527#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
528#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
529#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
530#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
531#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
532#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
533
534/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
535#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
536#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
537#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
538#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
539#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
540#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
541#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
542#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
543#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]544#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
545#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]546#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
547
548#define PINMUX_MOD_SELS \
549\
550MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
551 MOD_SEL2_30 \
552 MOD_SEL1_29_28_27 MOD_SEL2_29 \
553MOD_SEL0_28_27 MOD_SEL2_28_27 \
554MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
555 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
556MOD_SEL0_23 MOD_SEL1_23_22_21 \
557MOD_SEL0_22 \
558MOD_SEL0_21 MOD_SEL2_21 \
559MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
560MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
561MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
562 MOD_SEL2_17 \
563MOD_SEL0_16 MOD_SEL1_16 \
564 MOD_SEL1_15_14 \
565MOD_SEL0_14_13 \
566 MOD_SEL1_13 \
567MOD_SEL0_12 MOD_SEL1_12 \
568MOD_SEL0_11 MOD_SEL1_11 \
569MOD_SEL0_10 MOD_SEL1_10 \
570MOD_SEL0_9_8 MOD_SEL1_9 \
571MOD_SEL0_7_6 \
572 MOD_SEL1_6 \
573MOD_SEL0_5 MOD_SEL1_5 \
574MOD_SEL0_4_3 MOD_SEL1_4 \
575 MOD_SEL1_3 \
576 MOD_SEL1_2 \
577 MOD_SEL1_1 \
578 MOD_SEL1_0 MOD_SEL2_0
579
580/*
581 * These pins are not able to be muxed but have other properties
582 * that can be set, such as drive-strength or pull-up/pull-down enable.
583 */
584#define PINMUX_STATIC \
585 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
586 FM(QSPI0_IO2) FM(QSPI0_IO3) \
587 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
588 FM(QSPI1_IO2) FM(QSPI1_IO3) \
589 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
590 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
591 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
592 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]593 FM(PRESETOUT) \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]594 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
595 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
596
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]597#define PINMUX_PHYS \
598 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
599
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]600enum {
601 PINMUX_RESERVED = 0,
602
603 PINMUX_DATA_BEGIN,
604 GP_ALL(DATA),
605 PINMUX_DATA_END,
606
607#define F_(x, y)
608#define FM(x) FN_##x,
609 PINMUX_FUNCTION_BEGIN,
610 GP_ALL(FN),
611 PINMUX_GPSR
612 PINMUX_IPSR
613 PINMUX_MOD_SELS
614 PINMUX_FUNCTION_END,
615#undef F_
616#undef FM
617
618#define F_(x, y)
619#define FM(x) x##_MARK,
620 PINMUX_MARK_BEGIN,
621 PINMUX_GPSR
622 PINMUX_IPSR
623 PINMUX_MOD_SELS
624 PINMUX_STATIC
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]625 PINMUX_PHYS
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]626 PINMUX_MARK_END,
627#undef F_
628#undef FM
629};
630
631static const u16 pinmux_data[] = {
632 PINMUX_DATA_GP_ALL(),
633
634 PINMUX_SINGLE(AVS1),
635 PINMUX_SINGLE(AVS2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]636 PINMUX_SINGLE(CLKOUT),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]637 PINMUX_SINGLE(GP7_02),
638 PINMUX_SINGLE(GP7_03),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]639 PINMUX_SINGLE(MSIOF0_RXD),
640 PINMUX_SINGLE(MSIOF0_SCK),
641 PINMUX_SINGLE(MSIOF0_TXD),
642 PINMUX_SINGLE(SSI_SCK5),
643 PINMUX_SINGLE(SSI_SDATA5),
644 PINMUX_SINGLE(SSI_WS5),
645
646 /* IPSR0 */
647 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
648 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
649
650 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
651 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
652 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
653
654 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
655 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
656 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
657
658 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
659 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
660 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
661
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]662 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
663 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
664 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
665 PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0),
666 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]667
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]668 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
669 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
670 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]671 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]672
673 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
674 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
675 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
676 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
677 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
678 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
679 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
680
681 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
682 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
683 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
684 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
685 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
686 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
687 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
688
689 /* IPSR1 */
690 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
691 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
692 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
693 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
694 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
695 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
696
697 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
698 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]699 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
700 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
701 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
702 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
703
704 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
705 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]706 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
707 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
708 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
709 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
710
711 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
712 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]713 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
714 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
715 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
716 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
717 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
718
719 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
720 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]721 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
722 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
723
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]724 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
725 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
726 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
727 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]728 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]729
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]730 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
731 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
732 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
733 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]734
735 PINMUX_IPSR_GPSR(IP1_31_28, A0),
736 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
737 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
738 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
739 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
740 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
741
742 /* IPSR2 */
743 PINMUX_IPSR_GPSR(IP2_3_0, A1),
744 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
745 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
746 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
747 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
748 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
749
750 PINMUX_IPSR_GPSR(IP2_7_4, A2),
751 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
752 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
753 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
754 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
755 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
756
757 PINMUX_IPSR_GPSR(IP2_11_8, A3),
758 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
759 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
760 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
761 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
762 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
763
764 PINMUX_IPSR_GPSR(IP2_15_12, A4),
765 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
766 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
767 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
768 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
769 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
770
771 PINMUX_IPSR_GPSR(IP2_19_16, A5),
772 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
773 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
774 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
775 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
776 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
777 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
778
779 PINMUX_IPSR_GPSR(IP2_23_20, A6),
780 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
781 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
782 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
783 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
784 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
785 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
786
787 PINMUX_IPSR_GPSR(IP2_27_24, A7),
788 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
789 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
790 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
791 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
792 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
793 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
794
795 PINMUX_IPSR_GPSR(IP2_31_28, A8),
796 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
797 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
798 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
799 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
800 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
801 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
802
803 /* IPSR3 */
804 PINMUX_IPSR_GPSR(IP3_3_0, A9),
805 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
806 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
807 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
808
809 PINMUX_IPSR_GPSR(IP3_7_4, A10),
810 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]811 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]812 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
813
814 PINMUX_IPSR_GPSR(IP3_11_8, A11),
815 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
816 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
817 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
818 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
819 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
820 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
821 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
822 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
823
824 PINMUX_IPSR_GPSR(IP3_15_12, A12),
825 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
826 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
827 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
828 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
829 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
830
831 PINMUX_IPSR_GPSR(IP3_19_16, A13),
832 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
833 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
834 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
835 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
836 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
837
838 PINMUX_IPSR_GPSR(IP3_23_20, A14),
839 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
840 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
841 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
842 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
843 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
844
845 PINMUX_IPSR_GPSR(IP3_27_24, A15),
846 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
847 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
848 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
849 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
850 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
851
852 PINMUX_IPSR_GPSR(IP3_31_28, A16),
853 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
854 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
855 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
856
857 /* IPSR4 */
858 PINMUX_IPSR_GPSR(IP4_3_0, A17),
859 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
860 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
861 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
862
863 PINMUX_IPSR_GPSR(IP4_7_4, A18),
864 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
865 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
866 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
867
868 PINMUX_IPSR_GPSR(IP4_11_8, A19),
869 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
870 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
871 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
872
873 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
874 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
875
876 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
877 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
878 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
879
880 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
881 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
882 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
883 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
884 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
885 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
886 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
887 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
888
889 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
890 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
891 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
892 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
893 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
894 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
895
896 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
897 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
898 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
899 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
900 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
901 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
902
903 /* IPSR5 */
904 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
905 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
906 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
907 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
908 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
909 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
910 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
911
912 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
913 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]914 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]915 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
916 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
917 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
918 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
919 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
920
921 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
922 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
923 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
924 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
925
926 PINMUX_IPSR_GPSR(IP5_15_12, D0),
927 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
928 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
929 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
930 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
931
932 PINMUX_IPSR_GPSR(IP5_19_16, D1),
933 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
934 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
935 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
936 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
937
938 PINMUX_IPSR_GPSR(IP5_23_20, D2),
939 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
940 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
941 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
942
943 PINMUX_IPSR_GPSR(IP5_27_24, D3),
944 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
945 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
946 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
947
948 PINMUX_IPSR_GPSR(IP5_31_28, D4),
949 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
950 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
951 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
952
953 /* IPSR6 */
954 PINMUX_IPSR_GPSR(IP6_3_0, D5),
955 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
956 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
957 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
958
959 PINMUX_IPSR_GPSR(IP6_7_4, D6),
960 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
961 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
962 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
963
964 PINMUX_IPSR_GPSR(IP6_11_8, D7),
965 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
966 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
967 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
968
969 PINMUX_IPSR_GPSR(IP6_15_12, D8),
970 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
971 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
972 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
973 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
974 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
975
976 PINMUX_IPSR_GPSR(IP6_19_16, D9),
977 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
978 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
979 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
980 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
981
982 PINMUX_IPSR_GPSR(IP6_23_20, D10),
983 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
984 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
985 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
986 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
987 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
988 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
989
990 PINMUX_IPSR_GPSR(IP6_27_24, D11),
991 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
992 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
993 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
994 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]995 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]996 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
997
998 PINMUX_IPSR_GPSR(IP6_31_28, D12),
999 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
1000 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
1001 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
1002 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
1003 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
1004
1005 /* IPSR7 */
1006 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1007 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1008 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1009 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1010 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1011 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1012
1013 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1014 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1015 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1016 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1017 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1018 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1019 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1020
1021 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1022 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1023 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1024 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1025 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1026 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1027 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1028
1029 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1030 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1031 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1032
1033 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1034 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1035 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1036
1037 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1038 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1039 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1040 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1041
1042 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1043 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1044 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1045 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1046
1047 /* IPSR8 */
1048 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1049 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1050 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1051 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1052
1053 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1054 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1055 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1056 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1057
1058 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1059 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1060 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1061
1062 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1063 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1064 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
1065 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1066 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1067
1068 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1069 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1070 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1071 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
1072 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1073 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1074
1075 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1076 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1077 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1078 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
1079 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1080 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1081
1082 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1083 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1084 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1085 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
1086 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1087 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1088
1089 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1090 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1091 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1092 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
1093 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1094 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1095
1096 /* IPSR9 */
1097 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1098 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1099
1100 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1101 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1102
1103 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1104 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1105
1106 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1107 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1108
1109 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1110 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1111
1112 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1113 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1114
1115 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1116 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1117 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1118
1119 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1120 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1121
1122 /* IPSR10 */
1123 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1124 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1125
1126 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1127 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1128
1129 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1130 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1131
1132 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1133 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1134
1135 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1136 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1137
1138 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1139 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1140 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1141
1142 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1143 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1144 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1145
1146 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1147 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1148 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1149
1150 /* IPSR11 */
1151 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1152 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1153 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1154
1155 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1156 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1157
1158 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1159 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1160 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1161
1162 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1163 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1164
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1165 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1166 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1167 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1168
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1169 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1170 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1171 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1172
1173 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1174 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1175 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1176 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1177 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1178 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1179 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1180 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1181 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1182 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1183
1184 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1185 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1186 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1187 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1188 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1189
1190 /* IPSR12 */
1191 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1192 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1193 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1194 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1195 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1196
1197 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1198 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1199 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1200 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1201 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1202 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1203 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1204 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1205
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1206 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1207 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1208 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1209 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1210 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1211 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1212 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1213 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1214
1215 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1216 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1217 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1218 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1219 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1220
1221 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1222 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1223 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1224 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1225 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1226
1227 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1228 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1229 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1230 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1231 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1232 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1233 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1234
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1235 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1236 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1237 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1238 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1239 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1240 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1241 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1242
1243 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1244 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1245 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1246 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1247 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1248 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1249 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1250
1251 /* IPSR13 */
1252 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1253 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1254 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1255 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1256 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1257 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1258
1259 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1260 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1261 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1262 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1263 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1264 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1265
1266 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1267 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1268 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1269 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1270 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1271 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1272 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1273 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1274
1275 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1276 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1277 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1278 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1279 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1280 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1281
1282 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1283 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1284 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1285 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1286 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1287 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1288
1289 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1290 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1291 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1292 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1293 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1294 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1295 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1296 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1297
1298 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1299 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1300 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1301 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1302 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1303 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1304 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1305
1306 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1307 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1308 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1309 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1310
1311 /* IPSR14 */
1312 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1313 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1314 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1315 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1316 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1317 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1318 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1319 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
1320
1321 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1322 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1323 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1324 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1325 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1326 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1327 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1328 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1329
1330 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1331 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1332 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1333
1334 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1335 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1336 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1337 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1338
1339 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1340 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1341 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1342
1343 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1344 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1345
1346 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1347 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1348
1349 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1350 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1351
1352 /* IPSR15 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1353 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1354
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1355 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1356 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1357
1358 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1359 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1360 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1361
1362 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1363 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1364 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1365 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1366
1367 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1368 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1369 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1370 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1371 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1372 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1373 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1374
1375 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1376 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1377 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1378 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1379 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1380 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1381 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1382
1383 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1384 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1385 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1386 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1387 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1388 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1389 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1390
1391 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1392 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1393 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1394 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1395 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1396 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1397 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1398
1399 /* IPSR16 */
1400 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1401 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1402 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1403
1404 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1405 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1406 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1407
1408 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1409 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1410 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1411
1412 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1413 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1414 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1415 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1416 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1417 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1418 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1419
1420 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1421 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1422 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1423 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1424 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1425 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1426 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1427
1428 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1429 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1430 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1431 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1432 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1433 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1434 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1435 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1436
1437 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1438 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1439 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1440 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1441 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1442 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1443 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1444
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1445 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1446 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1447 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1448 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1449 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1450 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1451 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1452 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1453
1454 /* IPSR17 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1455 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1456
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1457 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1458 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1459 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1460 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1461 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
1462
1463 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1464 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1465 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1466 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1467 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1468 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1469 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1470
1471 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1472 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1473 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1474 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1475 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1476 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1477
1478 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1479 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1480 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1481 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1482 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1483 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1484 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1485 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1486 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1487
1488 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1489 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1490 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1491 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1492 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1493 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1494 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1495 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1496 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1497
1498 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1499 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1500 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1501 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1502 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1503 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1504 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1505 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1506 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1507 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1508 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1509
1510 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1511 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1512 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1513 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1514 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1515 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1516 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1517 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1518 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1519
1520 /* IPSR18 */
1521 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
1522 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1523 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1524 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1525 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1526 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1527 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1528 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1529 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1530
1531 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
1532 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1533 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1534 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1535 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1536 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1537 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1538 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1539 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1540
1541/*
1542 * Static pins can not be muxed between different functions but
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1543 * still need mark entries in the pinmux list. Add each static
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1544 * pin to the list without an associated function. The sh-pfc
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1545 * core will do the right thing and skip trying to mux the pin
1546 * while still applying configuration to it.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1547 */
1548#define FM(x) PINMUX_DATA(x##_MARK, 0),
1549 PINMUX_STATIC
1550#undef FM
1551};
1552
1553/*
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1554 * Pins not associated with a GPIO port.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1555 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1556enum {
1557 GP_ASSIGN_LAST(),
1558 NOGP_ALL(),
1559};
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1560
1561static const struct sh_pfc_pin pinmux_pins[] = {
1562 PINMUX_GPIO_GP_ALL(),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1563 PINMUX_NOGP_ALL(),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1564};
1565
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]1566#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1567/* - AUDIO CLOCK ------------------------------------------------------------ */
1568static const unsigned int audio_clk_a_a_pins[] = {
1569 /* CLK A */
1570 RCAR_GP_PIN(6, 22),
1571};
1572static const unsigned int audio_clk_a_a_mux[] = {
1573 AUDIO_CLKA_A_MARK,
1574};
1575static const unsigned int audio_clk_a_b_pins[] = {
1576 /* CLK A */
1577 RCAR_GP_PIN(5, 4),
1578};
1579static const unsigned int audio_clk_a_b_mux[] = {
1580 AUDIO_CLKA_B_MARK,
1581};
1582static const unsigned int audio_clk_a_c_pins[] = {
1583 /* CLK A */
1584 RCAR_GP_PIN(5, 19),
1585};
1586static const unsigned int audio_clk_a_c_mux[] = {
1587 AUDIO_CLKA_C_MARK,
1588};
1589static const unsigned int audio_clk_b_a_pins[] = {
1590 /* CLK B */
1591 RCAR_GP_PIN(5, 12),
1592};
1593static const unsigned int audio_clk_b_a_mux[] = {
1594 AUDIO_CLKB_A_MARK,
1595};
1596static const unsigned int audio_clk_b_b_pins[] = {
1597 /* CLK B */
1598 RCAR_GP_PIN(6, 23),
1599};
1600static const unsigned int audio_clk_b_b_mux[] = {
1601 AUDIO_CLKB_B_MARK,
1602};
1603static const unsigned int audio_clk_c_a_pins[] = {
1604 /* CLK C */
1605 RCAR_GP_PIN(5, 21),
1606};
1607static const unsigned int audio_clk_c_a_mux[] = {
1608 AUDIO_CLKC_A_MARK,
1609};
1610static const unsigned int audio_clk_c_b_pins[] = {
1611 /* CLK C */
1612 RCAR_GP_PIN(5, 0),
1613};
1614static const unsigned int audio_clk_c_b_mux[] = {
1615 AUDIO_CLKC_B_MARK,
1616};
1617static const unsigned int audio_clkout_a_pins[] = {
1618 /* CLKOUT */
1619 RCAR_GP_PIN(5, 18),
1620};
1621static const unsigned int audio_clkout_a_mux[] = {
1622 AUDIO_CLKOUT_A_MARK,
1623};
1624static const unsigned int audio_clkout_b_pins[] = {
1625 /* CLKOUT */
1626 RCAR_GP_PIN(6, 28),
1627};
1628static const unsigned int audio_clkout_b_mux[] = {
1629 AUDIO_CLKOUT_B_MARK,
1630};
1631static const unsigned int audio_clkout_c_pins[] = {
1632 /* CLKOUT */
1633 RCAR_GP_PIN(5, 3),
1634};
1635static const unsigned int audio_clkout_c_mux[] = {
1636 AUDIO_CLKOUT_C_MARK,
1637};
1638static const unsigned int audio_clkout_d_pins[] = {
1639 /* CLKOUT */
1640 RCAR_GP_PIN(5, 21),
1641};
1642static const unsigned int audio_clkout_d_mux[] = {
1643 AUDIO_CLKOUT_D_MARK,
1644};
1645static const unsigned int audio_clkout1_a_pins[] = {
1646 /* CLKOUT1 */
1647 RCAR_GP_PIN(5, 15),
1648};
1649static const unsigned int audio_clkout1_a_mux[] = {
1650 AUDIO_CLKOUT1_A_MARK,
1651};
1652static const unsigned int audio_clkout1_b_pins[] = {
1653 /* CLKOUT1 */
1654 RCAR_GP_PIN(6, 29),
1655};
1656static const unsigned int audio_clkout1_b_mux[] = {
1657 AUDIO_CLKOUT1_B_MARK,
1658};
1659static const unsigned int audio_clkout2_a_pins[] = {
1660 /* CLKOUT2 */
1661 RCAR_GP_PIN(5, 16),
1662};
1663static const unsigned int audio_clkout2_a_mux[] = {
1664 AUDIO_CLKOUT2_A_MARK,
1665};
1666static const unsigned int audio_clkout2_b_pins[] = {
1667 /* CLKOUT2 */
1668 RCAR_GP_PIN(6, 30),
1669};
1670static const unsigned int audio_clkout2_b_mux[] = {
1671 AUDIO_CLKOUT2_B_MARK,
1672};
1673static const unsigned int audio_clkout3_a_pins[] = {
1674 /* CLKOUT3 */
1675 RCAR_GP_PIN(5, 19),
1676};
1677static const unsigned int audio_clkout3_a_mux[] = {
1678 AUDIO_CLKOUT3_A_MARK,
1679};
1680static const unsigned int audio_clkout3_b_pins[] = {
1681 /* CLKOUT3 */
1682 RCAR_GP_PIN(6, 31),
1683};
1684static const unsigned int audio_clkout3_b_mux[] = {
1685 AUDIO_CLKOUT3_B_MARK,
1686};
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]1687#endif
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1688
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1689/* - EtherAVB --------------------------------------------------------------- */
1690static const unsigned int avb_link_pins[] = {
1691 /* AVB_LINK */
1692 RCAR_GP_PIN(2, 12),
1693};
1694static const unsigned int avb_link_mux[] = {
1695 AVB_LINK_MARK,
1696};
1697static const unsigned int avb_magic_pins[] = {
1698 /* AVB_MAGIC_ */
1699 RCAR_GP_PIN(2, 10),
1700};
1701static const unsigned int avb_magic_mux[] = {
1702 AVB_MAGIC_MARK,
1703};
1704static const unsigned int avb_phy_int_pins[] = {
1705 /* AVB_PHY_INT */
1706 RCAR_GP_PIN(2, 11),
1707};
1708static const unsigned int avb_phy_int_mux[] = {
1709 AVB_PHY_INT_MARK,
1710};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1711static const unsigned int avb_mdio_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1712 /* AVB_MDC, AVB_MDIO */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1713 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1714};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1715static const unsigned int avb_mdio_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1716 AVB_MDC_MARK, AVB_MDIO_MARK,
1717};
1718static const unsigned int avb_mii_pins[] = {
1719 /*
1720 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1721 * AVB_TD1, AVB_TD2, AVB_TD3,
1722 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1723 * AVB_RD1, AVB_RD2, AVB_RD3,
1724 * AVB_TXCREFCLK
1725 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1726 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1727 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1728 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1729 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1730 PIN_AVB_TXCREFCLK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1731};
1732static const unsigned int avb_mii_mux[] = {
1733 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1734 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1735 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1736 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1737 AVB_TXCREFCLK_MARK,
1738};
1739static const unsigned int avb_avtp_pps_pins[] = {
1740 /* AVB_AVTP_PPS */
1741 RCAR_GP_PIN(2, 6),
1742};
1743static const unsigned int avb_avtp_pps_mux[] = {
1744 AVB_AVTP_PPS_MARK,
1745};
1746static const unsigned int avb_avtp_match_a_pins[] = {
1747 /* AVB_AVTP_MATCH_A */
1748 RCAR_GP_PIN(2, 13),
1749};
1750static const unsigned int avb_avtp_match_a_mux[] = {
1751 AVB_AVTP_MATCH_A_MARK,
1752};
1753static const unsigned int avb_avtp_capture_a_pins[] = {
1754 /* AVB_AVTP_CAPTURE_A */
1755 RCAR_GP_PIN(2, 14),
1756};
1757static const unsigned int avb_avtp_capture_a_mux[] = {
1758 AVB_AVTP_CAPTURE_A_MARK,
1759};
1760static const unsigned int avb_avtp_match_b_pins[] = {
1761 /* AVB_AVTP_MATCH_B */
1762 RCAR_GP_PIN(1, 8),
1763};
1764static const unsigned int avb_avtp_match_b_mux[] = {
1765 AVB_AVTP_MATCH_B_MARK,
1766};
1767static const unsigned int avb_avtp_capture_b_pins[] = {
1768 /* AVB_AVTP_CAPTURE_B */
1769 RCAR_GP_PIN(1, 11),
1770};
1771static const unsigned int avb_avtp_capture_b_mux[] = {
1772 AVB_AVTP_CAPTURE_B_MARK,
1773};
1774
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]1775#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1776/* - CAN ------------------------------------------------------------------ */
1777static const unsigned int can0_data_a_pins[] = {
1778 /* TX, RX */
1779 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1780};
1781static const unsigned int can0_data_a_mux[] = {
1782 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1783};
1784static const unsigned int can0_data_b_pins[] = {
1785 /* TX, RX */
1786 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1787};
1788static const unsigned int can0_data_b_mux[] = {
1789 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1790};
1791static const unsigned int can1_data_pins[] = {
1792 /* TX, RX */
1793 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1794};
1795static const unsigned int can1_data_mux[] = {
1796 CAN1_TX_MARK, CAN1_RX_MARK,
1797};
1798
1799/* - CAN Clock -------------------------------------------------------------- */
1800static const unsigned int can_clk_pins[] = {
1801 /* CLK */
1802 RCAR_GP_PIN(1, 25),
1803};
1804static const unsigned int can_clk_mux[] = {
1805 CAN_CLK_MARK,
1806};
1807
1808/* - CAN FD --------------------------------------------------------------- */
1809static const unsigned int canfd0_data_a_pins[] = {
1810 /* TX, RX */
1811 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1812};
1813static const unsigned int canfd0_data_a_mux[] = {
1814 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1815};
1816static const unsigned int canfd0_data_b_pins[] = {
1817 /* TX, RX */
1818 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1819};
1820static const unsigned int canfd0_data_b_mux[] = {
1821 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1822};
1823static const unsigned int canfd1_data_pins[] = {
1824 /* TX, RX */
1825 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1826};
1827static const unsigned int canfd1_data_mux[] = {
1828 CANFD1_TX_MARK, CANFD1_RX_MARK,
1829};
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]1830#endif
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1831
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]1832#ifdef CONFIG_PINCTRL_PFC_R8A77951
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1833/* - DRIF0 --------------------------------------------------------------- */
1834static const unsigned int drif0_ctrl_a_pins[] = {
1835 /* CLK, SYNC */
1836 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1837};
1838static const unsigned int drif0_ctrl_a_mux[] = {
1839 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1840};
1841static const unsigned int drif0_data0_a_pins[] = {
1842 /* D0 */
1843 RCAR_GP_PIN(6, 10),
1844};
1845static const unsigned int drif0_data0_a_mux[] = {
1846 RIF0_D0_A_MARK,
1847};
1848static const unsigned int drif0_data1_a_pins[] = {
1849 /* D1 */
1850 RCAR_GP_PIN(6, 7),
1851};
1852static const unsigned int drif0_data1_a_mux[] = {
1853 RIF0_D1_A_MARK,
1854};
1855static const unsigned int drif0_ctrl_b_pins[] = {
1856 /* CLK, SYNC */
1857 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1858};
1859static const unsigned int drif0_ctrl_b_mux[] = {
1860 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1861};
1862static const unsigned int drif0_data0_b_pins[] = {
1863 /* D0 */
1864 RCAR_GP_PIN(5, 1),
1865};
1866static const unsigned int drif0_data0_b_mux[] = {
1867 RIF0_D0_B_MARK,
1868};
1869static const unsigned int drif0_data1_b_pins[] = {
1870 /* D1 */
1871 RCAR_GP_PIN(5, 2),
1872};
1873static const unsigned int drif0_data1_b_mux[] = {
1874 RIF0_D1_B_MARK,
1875};
1876static const unsigned int drif0_ctrl_c_pins[] = {
1877 /* CLK, SYNC */
1878 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1879};
1880static const unsigned int drif0_ctrl_c_mux[] = {
1881 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1882};
1883static const unsigned int drif0_data0_c_pins[] = {
1884 /* D0 */
1885 RCAR_GP_PIN(5, 13),
1886};
1887static const unsigned int drif0_data0_c_mux[] = {
1888 RIF0_D0_C_MARK,
1889};
1890static const unsigned int drif0_data1_c_pins[] = {
1891 /* D1 */
1892 RCAR_GP_PIN(5, 14),
1893};
1894static const unsigned int drif0_data1_c_mux[] = {
1895 RIF0_D1_C_MARK,
1896};
1897/* - DRIF1 --------------------------------------------------------------- */
1898static const unsigned int drif1_ctrl_a_pins[] = {
1899 /* CLK, SYNC */
1900 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1901};
1902static const unsigned int drif1_ctrl_a_mux[] = {
1903 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1904};
1905static const unsigned int drif1_data0_a_pins[] = {
1906 /* D0 */
1907 RCAR_GP_PIN(6, 19),
1908};
1909static const unsigned int drif1_data0_a_mux[] = {
1910 RIF1_D0_A_MARK,
1911};
1912static const unsigned int drif1_data1_a_pins[] = {
1913 /* D1 */
1914 RCAR_GP_PIN(6, 20),
1915};
1916static const unsigned int drif1_data1_a_mux[] = {
1917 RIF1_D1_A_MARK,
1918};
1919static const unsigned int drif1_ctrl_b_pins[] = {
1920 /* CLK, SYNC */
1921 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1922};
1923static const unsigned int drif1_ctrl_b_mux[] = {
1924 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1925};
1926static const unsigned int drif1_data0_b_pins[] = {
1927 /* D0 */
1928 RCAR_GP_PIN(5, 7),
1929};
1930static const unsigned int drif1_data0_b_mux[] = {
1931 RIF1_D0_B_MARK,
1932};
1933static const unsigned int drif1_data1_b_pins[] = {
1934 /* D1 */
1935 RCAR_GP_PIN(5, 8),
1936};
1937static const unsigned int drif1_data1_b_mux[] = {
1938 RIF1_D1_B_MARK,
1939};
1940static const unsigned int drif1_ctrl_c_pins[] = {
1941 /* CLK, SYNC */
1942 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1943};
1944static const unsigned int drif1_ctrl_c_mux[] = {
1945 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1946};
1947static const unsigned int drif1_data0_c_pins[] = {
1948 /* D0 */
1949 RCAR_GP_PIN(5, 6),
1950};
1951static const unsigned int drif1_data0_c_mux[] = {
1952 RIF1_D0_C_MARK,
1953};
1954static const unsigned int drif1_data1_c_pins[] = {
1955 /* D1 */
1956 RCAR_GP_PIN(5, 10),
1957};
1958static const unsigned int drif1_data1_c_mux[] = {
1959 RIF1_D1_C_MARK,
1960};
1961/* - DRIF2 --------------------------------------------------------------- */
1962static const unsigned int drif2_ctrl_a_pins[] = {
1963 /* CLK, SYNC */
1964 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1965};
1966static const unsigned int drif2_ctrl_a_mux[] = {
1967 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1968};
1969static const unsigned int drif2_data0_a_pins[] = {
1970 /* D0 */
1971 RCAR_GP_PIN(6, 7),
1972};
1973static const unsigned int drif2_data0_a_mux[] = {
1974 RIF2_D0_A_MARK,
1975};
1976static const unsigned int drif2_data1_a_pins[] = {
1977 /* D1 */
1978 RCAR_GP_PIN(6, 10),
1979};
1980static const unsigned int drif2_data1_a_mux[] = {
1981 RIF2_D1_A_MARK,
1982};
1983static const unsigned int drif2_ctrl_b_pins[] = {
1984 /* CLK, SYNC */
1985 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1986};
1987static const unsigned int drif2_ctrl_b_mux[] = {
1988 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1989};
1990static const unsigned int drif2_data0_b_pins[] = {
1991 /* D0 */
1992 RCAR_GP_PIN(6, 30),
1993};
1994static const unsigned int drif2_data0_b_mux[] = {
1995 RIF2_D0_B_MARK,
1996};
1997static const unsigned int drif2_data1_b_pins[] = {
1998 /* D1 */
1999 RCAR_GP_PIN(6, 31),
2000};
2001static const unsigned int drif2_data1_b_mux[] = {
2002 RIF2_D1_B_MARK,
2003};
2004/* - DRIF3 --------------------------------------------------------------- */
2005static const unsigned int drif3_ctrl_a_pins[] = {
2006 /* CLK, SYNC */
2007 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2008};
2009static const unsigned int drif3_ctrl_a_mux[] = {
2010 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2011};
2012static const unsigned int drif3_data0_a_pins[] = {
2013 /* D0 */
2014 RCAR_GP_PIN(6, 19),
2015};
2016static const unsigned int drif3_data0_a_mux[] = {
2017 RIF3_D0_A_MARK,
2018};
2019static const unsigned int drif3_data1_a_pins[] = {
2020 /* D1 */
2021 RCAR_GP_PIN(6, 20),
2022};
2023static const unsigned int drif3_data1_a_mux[] = {
2024 RIF3_D1_A_MARK,
2025};
2026static const unsigned int drif3_ctrl_b_pins[] = {
2027 /* CLK, SYNC */
2028 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2029};
2030static const unsigned int drif3_ctrl_b_mux[] = {
2031 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2032};
2033static const unsigned int drif3_data0_b_pins[] = {
2034 /* D0 */
2035 RCAR_GP_PIN(6, 28),
2036};
2037static const unsigned int drif3_data0_b_mux[] = {
2038 RIF3_D0_B_MARK,
2039};
2040static const unsigned int drif3_data1_b_pins[] = {
2041 /* D1 */
2042 RCAR_GP_PIN(6, 29),
2043};
2044static const unsigned int drif3_data1_b_mux[] = {
2045 RIF3_D1_B_MARK,
2046};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]2047#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2048
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]2049#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2050/* - DU --------------------------------------------------------------------- */
2051static const unsigned int du_rgb666_pins[] = {
2052 /* R[7:2], G[7:2], B[7:2] */
2053 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2054 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2055 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2056 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2057 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2058 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2059};
2060static const unsigned int du_rgb666_mux[] = {
2061 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2062 DU_DR3_MARK, DU_DR2_MARK,
2063 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2064 DU_DG3_MARK, DU_DG2_MARK,
2065 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2066 DU_DB3_MARK, DU_DB2_MARK,
2067};
2068static const unsigned int du_rgb888_pins[] = {
2069 /* R[7:0], G[7:0], B[7:0] */
2070 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2071 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2072 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2073 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2074 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2075 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2076 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2077 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2078 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2079};
2080static const unsigned int du_rgb888_mux[] = {
2081 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2082 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2083 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2084 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2085 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2086 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2087};
2088static const unsigned int du_clk_out_0_pins[] = {
2089 /* CLKOUT */
2090 RCAR_GP_PIN(1, 27),
2091};
2092static const unsigned int du_clk_out_0_mux[] = {
2093 DU_DOTCLKOUT0_MARK
2094};
2095static const unsigned int du_clk_out_1_pins[] = {
2096 /* CLKOUT */
2097 RCAR_GP_PIN(2, 3),
2098};
2099static const unsigned int du_clk_out_1_mux[] = {
2100 DU_DOTCLKOUT1_MARK
2101};
2102static const unsigned int du_sync_pins[] = {
2103 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2104 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2105};
2106static const unsigned int du_sync_mux[] = {
2107 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2108};
2109static const unsigned int du_oddf_pins[] = {
2110 /* EXDISP/EXODDF/EXCDE */
2111 RCAR_GP_PIN(2, 2),
2112};
2113static const unsigned int du_oddf_mux[] = {
2114 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2115};
2116static const unsigned int du_cde_pins[] = {
2117 /* CDE */
2118 RCAR_GP_PIN(2, 0),
2119};
2120static const unsigned int du_cde_mux[] = {
2121 DU_CDE_MARK,
2122};
2123static const unsigned int du_disp_pins[] = {
2124 /* DISP */
2125 RCAR_GP_PIN(2, 1),
2126};
2127static const unsigned int du_disp_mux[] = {
2128 DU_DISP_MARK,
2129};
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]2130#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2131
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2132/* - HSCIF0 ----------------------------------------------------------------- */
2133static const unsigned int hscif0_data_pins[] = {
2134 /* RX, TX */
2135 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2136};
2137static const unsigned int hscif0_data_mux[] = {
2138 HRX0_MARK, HTX0_MARK,
2139};
2140static const unsigned int hscif0_clk_pins[] = {
2141 /* SCK */
2142 RCAR_GP_PIN(5, 12),
2143};
2144static const unsigned int hscif0_clk_mux[] = {
2145 HSCK0_MARK,
2146};
2147static const unsigned int hscif0_ctrl_pins[] = {
2148 /* RTS, CTS */
2149 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2150};
2151static const unsigned int hscif0_ctrl_mux[] = {
2152 HRTS0_N_MARK, HCTS0_N_MARK,
2153};
2154/* - HSCIF1 ----------------------------------------------------------------- */
2155static const unsigned int hscif1_data_a_pins[] = {
2156 /* RX, TX */
2157 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2158};
2159static const unsigned int hscif1_data_a_mux[] = {
2160 HRX1_A_MARK, HTX1_A_MARK,
2161};
2162static const unsigned int hscif1_clk_a_pins[] = {
2163 /* SCK */
2164 RCAR_GP_PIN(6, 21),
2165};
2166static const unsigned int hscif1_clk_a_mux[] = {
2167 HSCK1_A_MARK,
2168};
2169static const unsigned int hscif1_ctrl_a_pins[] = {
2170 /* RTS, CTS */
2171 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2172};
2173static const unsigned int hscif1_ctrl_a_mux[] = {
2174 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2175};
2176
2177static const unsigned int hscif1_data_b_pins[] = {
2178 /* RX, TX */
2179 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2180};
2181static const unsigned int hscif1_data_b_mux[] = {
2182 HRX1_B_MARK, HTX1_B_MARK,
2183};
2184static const unsigned int hscif1_clk_b_pins[] = {
2185 /* SCK */
2186 RCAR_GP_PIN(5, 0),
2187};
2188static const unsigned int hscif1_clk_b_mux[] = {
2189 HSCK1_B_MARK,
2190};
2191static const unsigned int hscif1_ctrl_b_pins[] = {
2192 /* RTS, CTS */
2193 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2194};
2195static const unsigned int hscif1_ctrl_b_mux[] = {
2196 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2197};
2198/* - HSCIF2 ----------------------------------------------------------------- */
2199static const unsigned int hscif2_data_a_pins[] = {
2200 /* RX, TX */
2201 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2202};
2203static const unsigned int hscif2_data_a_mux[] = {
2204 HRX2_A_MARK, HTX2_A_MARK,
2205};
2206static const unsigned int hscif2_clk_a_pins[] = {
2207 /* SCK */
2208 RCAR_GP_PIN(6, 10),
2209};
2210static const unsigned int hscif2_clk_a_mux[] = {
2211 HSCK2_A_MARK,
2212};
2213static const unsigned int hscif2_ctrl_a_pins[] = {
2214 /* RTS, CTS */
2215 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2216};
2217static const unsigned int hscif2_ctrl_a_mux[] = {
2218 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2219};
2220
2221static const unsigned int hscif2_data_b_pins[] = {
2222 /* RX, TX */
2223 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2224};
2225static const unsigned int hscif2_data_b_mux[] = {
2226 HRX2_B_MARK, HTX2_B_MARK,
2227};
2228static const unsigned int hscif2_clk_b_pins[] = {
2229 /* SCK */
2230 RCAR_GP_PIN(6, 21),
2231};
2232static const unsigned int hscif2_clk_b_mux[] = {
2233 HSCK2_B_MARK,
2234};
2235static const unsigned int hscif2_ctrl_b_pins[] = {
2236 /* RTS, CTS */
2237 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2238};
2239static const unsigned int hscif2_ctrl_b_mux[] = {
2240 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2241};
2242
2243static const unsigned int hscif2_data_c_pins[] = {
2244 /* RX, TX */
2245 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2246};
2247static const unsigned int hscif2_data_c_mux[] = {
2248 HRX2_C_MARK, HTX2_C_MARK,
2249};
2250static const unsigned int hscif2_clk_c_pins[] = {
2251 /* SCK */
2252 RCAR_GP_PIN(6, 24),
2253};
2254static const unsigned int hscif2_clk_c_mux[] = {
2255 HSCK2_C_MARK,
2256};
2257static const unsigned int hscif2_ctrl_c_pins[] = {
2258 /* RTS, CTS */
2259 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2260};
2261static const unsigned int hscif2_ctrl_c_mux[] = {
2262 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2263};
2264/* - HSCIF3 ----------------------------------------------------------------- */
2265static const unsigned int hscif3_data_a_pins[] = {
2266 /* RX, TX */
2267 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2268};
2269static const unsigned int hscif3_data_a_mux[] = {
2270 HRX3_A_MARK, HTX3_A_MARK,
2271};
2272static const unsigned int hscif3_clk_pins[] = {
2273 /* SCK */
2274 RCAR_GP_PIN(1, 22),
2275};
2276static const unsigned int hscif3_clk_mux[] = {
2277 HSCK3_MARK,
2278};
2279static const unsigned int hscif3_ctrl_pins[] = {
2280 /* RTS, CTS */
2281 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2282};
2283static const unsigned int hscif3_ctrl_mux[] = {
2284 HRTS3_N_MARK, HCTS3_N_MARK,
2285};
2286
2287static const unsigned int hscif3_data_b_pins[] = {
2288 /* RX, TX */
2289 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2290};
2291static const unsigned int hscif3_data_b_mux[] = {
2292 HRX3_B_MARK, HTX3_B_MARK,
2293};
2294static const unsigned int hscif3_data_c_pins[] = {
2295 /* RX, TX */
2296 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2297};
2298static const unsigned int hscif3_data_c_mux[] = {
2299 HRX3_C_MARK, HTX3_C_MARK,
2300};
2301static const unsigned int hscif3_data_d_pins[] = {
2302 /* RX, TX */
2303 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2304};
2305static const unsigned int hscif3_data_d_mux[] = {
2306 HRX3_D_MARK, HTX3_D_MARK,
2307};
2308/* - HSCIF4 ----------------------------------------------------------------- */
2309static const unsigned int hscif4_data_a_pins[] = {
2310 /* RX, TX */
2311 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2312};
2313static const unsigned int hscif4_data_a_mux[] = {
2314 HRX4_A_MARK, HTX4_A_MARK,
2315};
2316static const unsigned int hscif4_clk_pins[] = {
2317 /* SCK */
2318 RCAR_GP_PIN(1, 11),
2319};
2320static const unsigned int hscif4_clk_mux[] = {
2321 HSCK4_MARK,
2322};
2323static const unsigned int hscif4_ctrl_pins[] = {
2324 /* RTS, CTS */
2325 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2326};
2327static const unsigned int hscif4_ctrl_mux[] = {
2328 HRTS4_N_MARK, HCTS4_N_MARK,
2329};
2330
2331static const unsigned int hscif4_data_b_pins[] = {
2332 /* RX, TX */
2333 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2334};
2335static const unsigned int hscif4_data_b_mux[] = {
2336 HRX4_B_MARK, HTX4_B_MARK,
2337};
2338
2339/* - I2C -------------------------------------------------------------------- */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2340static const unsigned int i2c0_pins[] = {
2341 /* SCL, SDA */
2342 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2343};
2344
2345static const unsigned int i2c0_mux[] = {
2346 SCL0_MARK, SDA0_MARK,
2347};
2348
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2349static const unsigned int i2c1_a_pins[] = {
2350 /* SDA, SCL */
2351 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2352};
2353static const unsigned int i2c1_a_mux[] = {
2354 SDA1_A_MARK, SCL1_A_MARK,
2355};
2356static const unsigned int i2c1_b_pins[] = {
2357 /* SDA, SCL */
2358 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2359};
2360static const unsigned int i2c1_b_mux[] = {
2361 SDA1_B_MARK, SCL1_B_MARK,
2362};
2363static const unsigned int i2c2_a_pins[] = {
2364 /* SDA, SCL */
2365 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2366};
2367static const unsigned int i2c2_a_mux[] = {
2368 SDA2_A_MARK, SCL2_A_MARK,
2369};
2370static const unsigned int i2c2_b_pins[] = {
2371 /* SDA, SCL */
2372 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2373};
2374static const unsigned int i2c2_b_mux[] = {
2375 SDA2_B_MARK, SCL2_B_MARK,
2376};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2377
2378static const unsigned int i2c3_pins[] = {
2379 /* SCL, SDA */
2380 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2381};
2382
2383static const unsigned int i2c3_mux[] = {
2384 SCL3_MARK, SDA3_MARK,
2385};
2386
2387static const unsigned int i2c5_pins[] = {
2388 /* SCL, SDA */
2389 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2390};
2391
2392static const unsigned int i2c5_mux[] = {
2393 SCL5_MARK, SDA5_MARK,
2394};
2395
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2396static const unsigned int i2c6_a_pins[] = {
2397 /* SDA, SCL */
2398 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2399};
2400static const unsigned int i2c6_a_mux[] = {
2401 SDA6_A_MARK, SCL6_A_MARK,
2402};
2403static const unsigned int i2c6_b_pins[] = {
2404 /* SDA, SCL */
2405 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2406};
2407static const unsigned int i2c6_b_mux[] = {
2408 SDA6_B_MARK, SCL6_B_MARK,
2409};
2410static const unsigned int i2c6_c_pins[] = {
2411 /* SDA, SCL */
2412 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2413};
2414static const unsigned int i2c6_c_mux[] = {
2415 SDA6_C_MARK, SCL6_C_MARK,
2416};
2417
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]2418#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2419/* - INTC-EX ---------------------------------------------------------------- */
2420static const unsigned int intc_ex_irq0_pins[] = {
2421 /* IRQ0 */
2422 RCAR_GP_PIN(2, 0),
2423};
2424static const unsigned int intc_ex_irq0_mux[] = {
2425 IRQ0_MARK,
2426};
2427static const unsigned int intc_ex_irq1_pins[] = {
2428 /* IRQ1 */
2429 RCAR_GP_PIN(2, 1),
2430};
2431static const unsigned int intc_ex_irq1_mux[] = {
2432 IRQ1_MARK,
2433};
2434static const unsigned int intc_ex_irq2_pins[] = {
2435 /* IRQ2 */
2436 RCAR_GP_PIN(2, 2),
2437};
2438static const unsigned int intc_ex_irq2_mux[] = {
2439 IRQ2_MARK,
2440};
2441static const unsigned int intc_ex_irq3_pins[] = {
2442 /* IRQ3 */
2443 RCAR_GP_PIN(2, 3),
2444};
2445static const unsigned int intc_ex_irq3_mux[] = {
2446 IRQ3_MARK,
2447};
2448static const unsigned int intc_ex_irq4_pins[] = {
2449 /* IRQ4 */
2450 RCAR_GP_PIN(2, 4),
2451};
2452static const unsigned int intc_ex_irq4_mux[] = {
2453 IRQ4_MARK,
2454};
2455static const unsigned int intc_ex_irq5_pins[] = {
2456 /* IRQ5 */
2457 RCAR_GP_PIN(2, 5),
2458};
2459static const unsigned int intc_ex_irq5_mux[] = {
2460 IRQ5_MARK,
2461};
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]2462#endif
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2463
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]2464#ifdef CONFIG_PINCTRL_PFC_R8A77951
2465/* - MLB+ ------------------------------------------------------------------- */
2466static const unsigned int mlb_3pin_pins[] = {
2467 RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2468};
2469static const unsigned int mlb_3pin_mux[] = {
2470 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2471};
2472#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
2473
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]2474#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2475/* - MSIOF0 ----------------------------------------------------------------- */
2476static const unsigned int msiof0_clk_pins[] = {
2477 /* SCK */
2478 RCAR_GP_PIN(5, 17),
2479};
2480static const unsigned int msiof0_clk_mux[] = {
2481 MSIOF0_SCK_MARK,
2482};
2483static const unsigned int msiof0_sync_pins[] = {
2484 /* SYNC */
2485 RCAR_GP_PIN(5, 18),
2486};
2487static const unsigned int msiof0_sync_mux[] = {
2488 MSIOF0_SYNC_MARK,
2489};
2490static const unsigned int msiof0_ss1_pins[] = {
2491 /* SS1 */
2492 RCAR_GP_PIN(5, 19),
2493};
2494static const unsigned int msiof0_ss1_mux[] = {
2495 MSIOF0_SS1_MARK,
2496};
2497static const unsigned int msiof0_ss2_pins[] = {
2498 /* SS2 */
2499 RCAR_GP_PIN(5, 21),
2500};
2501static const unsigned int msiof0_ss2_mux[] = {
2502 MSIOF0_SS2_MARK,
2503};
2504static const unsigned int msiof0_txd_pins[] = {
2505 /* TXD */
2506 RCAR_GP_PIN(5, 20),
2507};
2508static const unsigned int msiof0_txd_mux[] = {
2509 MSIOF0_TXD_MARK,
2510};
2511static const unsigned int msiof0_rxd_pins[] = {
2512 /* RXD */
2513 RCAR_GP_PIN(5, 22),
2514};
2515static const unsigned int msiof0_rxd_mux[] = {
2516 MSIOF0_RXD_MARK,
2517};
2518/* - MSIOF1 ----------------------------------------------------------------- */
2519static const unsigned int msiof1_clk_a_pins[] = {
2520 /* SCK */
2521 RCAR_GP_PIN(6, 8),
2522};
2523static const unsigned int msiof1_clk_a_mux[] = {
2524 MSIOF1_SCK_A_MARK,
2525};
2526static const unsigned int msiof1_sync_a_pins[] = {
2527 /* SYNC */
2528 RCAR_GP_PIN(6, 9),
2529};
2530static const unsigned int msiof1_sync_a_mux[] = {
2531 MSIOF1_SYNC_A_MARK,
2532};
2533static const unsigned int msiof1_ss1_a_pins[] = {
2534 /* SS1 */
2535 RCAR_GP_PIN(6, 5),
2536};
2537static const unsigned int msiof1_ss1_a_mux[] = {
2538 MSIOF1_SS1_A_MARK,
2539};
2540static const unsigned int msiof1_ss2_a_pins[] = {
2541 /* SS2 */
2542 RCAR_GP_PIN(6, 6),
2543};
2544static const unsigned int msiof1_ss2_a_mux[] = {
2545 MSIOF1_SS2_A_MARK,
2546};
2547static const unsigned int msiof1_txd_a_pins[] = {
2548 /* TXD */
2549 RCAR_GP_PIN(6, 7),
2550};
2551static const unsigned int msiof1_txd_a_mux[] = {
2552 MSIOF1_TXD_A_MARK,
2553};
2554static const unsigned int msiof1_rxd_a_pins[] = {
2555 /* RXD */
2556 RCAR_GP_PIN(6, 10),
2557};
2558static const unsigned int msiof1_rxd_a_mux[] = {
2559 MSIOF1_RXD_A_MARK,
2560};
2561static const unsigned int msiof1_clk_b_pins[] = {
2562 /* SCK */
2563 RCAR_GP_PIN(5, 9),
2564};
2565static const unsigned int msiof1_clk_b_mux[] = {
2566 MSIOF1_SCK_B_MARK,
2567};
2568static const unsigned int msiof1_sync_b_pins[] = {
2569 /* SYNC */
2570 RCAR_GP_PIN(5, 3),
2571};
2572static const unsigned int msiof1_sync_b_mux[] = {
2573 MSIOF1_SYNC_B_MARK,
2574};
2575static const unsigned int msiof1_ss1_b_pins[] = {
2576 /* SS1 */
2577 RCAR_GP_PIN(5, 4),
2578};
2579static const unsigned int msiof1_ss1_b_mux[] = {
2580 MSIOF1_SS1_B_MARK,
2581};
2582static const unsigned int msiof1_ss2_b_pins[] = {
2583 /* SS2 */
2584 RCAR_GP_PIN(5, 0),
2585};
2586static const unsigned int msiof1_ss2_b_mux[] = {
2587 MSIOF1_SS2_B_MARK,
2588};
2589static const unsigned int msiof1_txd_b_pins[] = {
2590 /* TXD */
2591 RCAR_GP_PIN(5, 8),
2592};
2593static const unsigned int msiof1_txd_b_mux[] = {
2594 MSIOF1_TXD_B_MARK,
2595};
2596static const unsigned int msiof1_rxd_b_pins[] = {
2597 /* RXD */
2598 RCAR_GP_PIN(5, 7),
2599};
2600static const unsigned int msiof1_rxd_b_mux[] = {
2601 MSIOF1_RXD_B_MARK,
2602};
2603static const unsigned int msiof1_clk_c_pins[] = {
2604 /* SCK */
2605 RCAR_GP_PIN(6, 17),
2606};
2607static const unsigned int msiof1_clk_c_mux[] = {
2608 MSIOF1_SCK_C_MARK,
2609};
2610static const unsigned int msiof1_sync_c_pins[] = {
2611 /* SYNC */
2612 RCAR_GP_PIN(6, 18),
2613};
2614static const unsigned int msiof1_sync_c_mux[] = {
2615 MSIOF1_SYNC_C_MARK,
2616};
2617static const unsigned int msiof1_ss1_c_pins[] = {
2618 /* SS1 */
2619 RCAR_GP_PIN(6, 21),
2620};
2621static const unsigned int msiof1_ss1_c_mux[] = {
2622 MSIOF1_SS1_C_MARK,
2623};
2624static const unsigned int msiof1_ss2_c_pins[] = {
2625 /* SS2 */
2626 RCAR_GP_PIN(6, 27),
2627};
2628static const unsigned int msiof1_ss2_c_mux[] = {
2629 MSIOF1_SS2_C_MARK,
2630};
2631static const unsigned int msiof1_txd_c_pins[] = {
2632 /* TXD */
2633 RCAR_GP_PIN(6, 20),
2634};
2635static const unsigned int msiof1_txd_c_mux[] = {
2636 MSIOF1_TXD_C_MARK,
2637};
2638static const unsigned int msiof1_rxd_c_pins[] = {
2639 /* RXD */
2640 RCAR_GP_PIN(6, 19),
2641};
2642static const unsigned int msiof1_rxd_c_mux[] = {
2643 MSIOF1_RXD_C_MARK,
2644};
2645static const unsigned int msiof1_clk_d_pins[] = {
2646 /* SCK */
2647 RCAR_GP_PIN(5, 12),
2648};
2649static const unsigned int msiof1_clk_d_mux[] = {
2650 MSIOF1_SCK_D_MARK,
2651};
2652static const unsigned int msiof1_sync_d_pins[] = {
2653 /* SYNC */
2654 RCAR_GP_PIN(5, 15),
2655};
2656static const unsigned int msiof1_sync_d_mux[] = {
2657 MSIOF1_SYNC_D_MARK,
2658};
2659static const unsigned int msiof1_ss1_d_pins[] = {
2660 /* SS1 */
2661 RCAR_GP_PIN(5, 16),
2662};
2663static const unsigned int msiof1_ss1_d_mux[] = {
2664 MSIOF1_SS1_D_MARK,
2665};
2666static const unsigned int msiof1_ss2_d_pins[] = {
2667 /* SS2 */
2668 RCAR_GP_PIN(5, 21),
2669};
2670static const unsigned int msiof1_ss2_d_mux[] = {
2671 MSIOF1_SS2_D_MARK,
2672};
2673static const unsigned int msiof1_txd_d_pins[] = {
2674 /* TXD */
2675 RCAR_GP_PIN(5, 14),
2676};
2677static const unsigned int msiof1_txd_d_mux[] = {
2678 MSIOF1_TXD_D_MARK,
2679};
2680static const unsigned int msiof1_rxd_d_pins[] = {
2681 /* RXD */
2682 RCAR_GP_PIN(5, 13),
2683};
2684static const unsigned int msiof1_rxd_d_mux[] = {
2685 MSIOF1_RXD_D_MARK,
2686};
2687static const unsigned int msiof1_clk_e_pins[] = {
2688 /* SCK */
2689 RCAR_GP_PIN(3, 0),
2690};
2691static const unsigned int msiof1_clk_e_mux[] = {
2692 MSIOF1_SCK_E_MARK,
2693};
2694static const unsigned int msiof1_sync_e_pins[] = {
2695 /* SYNC */
2696 RCAR_GP_PIN(3, 1),
2697};
2698static const unsigned int msiof1_sync_e_mux[] = {
2699 MSIOF1_SYNC_E_MARK,
2700};
2701static const unsigned int msiof1_ss1_e_pins[] = {
2702 /* SS1 */
2703 RCAR_GP_PIN(3, 4),
2704};
2705static const unsigned int msiof1_ss1_e_mux[] = {
2706 MSIOF1_SS1_E_MARK,
2707};
2708static const unsigned int msiof1_ss2_e_pins[] = {
2709 /* SS2 */
2710 RCAR_GP_PIN(3, 5),
2711};
2712static const unsigned int msiof1_ss2_e_mux[] = {
2713 MSIOF1_SS2_E_MARK,
2714};
2715static const unsigned int msiof1_txd_e_pins[] = {
2716 /* TXD */
2717 RCAR_GP_PIN(3, 3),
2718};
2719static const unsigned int msiof1_txd_e_mux[] = {
2720 MSIOF1_TXD_E_MARK,
2721};
2722static const unsigned int msiof1_rxd_e_pins[] = {
2723 /* RXD */
2724 RCAR_GP_PIN(3, 2),
2725};
2726static const unsigned int msiof1_rxd_e_mux[] = {
2727 MSIOF1_RXD_E_MARK,
2728};
2729static const unsigned int msiof1_clk_f_pins[] = {
2730 /* SCK */
2731 RCAR_GP_PIN(5, 23),
2732};
2733static const unsigned int msiof1_clk_f_mux[] = {
2734 MSIOF1_SCK_F_MARK,
2735};
2736static const unsigned int msiof1_sync_f_pins[] = {
2737 /* SYNC */
2738 RCAR_GP_PIN(5, 24),
2739};
2740static const unsigned int msiof1_sync_f_mux[] = {
2741 MSIOF1_SYNC_F_MARK,
2742};
2743static const unsigned int msiof1_ss1_f_pins[] = {
2744 /* SS1 */
2745 RCAR_GP_PIN(6, 1),
2746};
2747static const unsigned int msiof1_ss1_f_mux[] = {
2748 MSIOF1_SS1_F_MARK,
2749};
2750static const unsigned int msiof1_ss2_f_pins[] = {
2751 /* SS2 */
2752 RCAR_GP_PIN(6, 2),
2753};
2754static const unsigned int msiof1_ss2_f_mux[] = {
2755 MSIOF1_SS2_F_MARK,
2756};
2757static const unsigned int msiof1_txd_f_pins[] = {
2758 /* TXD */
2759 RCAR_GP_PIN(6, 0),
2760};
2761static const unsigned int msiof1_txd_f_mux[] = {
2762 MSIOF1_TXD_F_MARK,
2763};
2764static const unsigned int msiof1_rxd_f_pins[] = {
2765 /* RXD */
2766 RCAR_GP_PIN(5, 25),
2767};
2768static const unsigned int msiof1_rxd_f_mux[] = {
2769 MSIOF1_RXD_F_MARK,
2770};
2771static const unsigned int msiof1_clk_g_pins[] = {
2772 /* SCK */
2773 RCAR_GP_PIN(3, 6),
2774};
2775static const unsigned int msiof1_clk_g_mux[] = {
2776 MSIOF1_SCK_G_MARK,
2777};
2778static const unsigned int msiof1_sync_g_pins[] = {
2779 /* SYNC */
2780 RCAR_GP_PIN(3, 7),
2781};
2782static const unsigned int msiof1_sync_g_mux[] = {
2783 MSIOF1_SYNC_G_MARK,
2784};
2785static const unsigned int msiof1_ss1_g_pins[] = {
2786 /* SS1 */
2787 RCAR_GP_PIN(3, 10),
2788};
2789static const unsigned int msiof1_ss1_g_mux[] = {
2790 MSIOF1_SS1_G_MARK,
2791};
2792static const unsigned int msiof1_ss2_g_pins[] = {
2793 /* SS2 */
2794 RCAR_GP_PIN(3, 11),
2795};
2796static const unsigned int msiof1_ss2_g_mux[] = {
2797 MSIOF1_SS2_G_MARK,
2798};
2799static const unsigned int msiof1_txd_g_pins[] = {
2800 /* TXD */
2801 RCAR_GP_PIN(3, 9),
2802};
2803static const unsigned int msiof1_txd_g_mux[] = {
2804 MSIOF1_TXD_G_MARK,
2805};
2806static const unsigned int msiof1_rxd_g_pins[] = {
2807 /* RXD */
2808 RCAR_GP_PIN(3, 8),
2809};
2810static const unsigned int msiof1_rxd_g_mux[] = {
2811 MSIOF1_RXD_G_MARK,
2812};
2813/* - MSIOF2 ----------------------------------------------------------------- */
2814static const unsigned int msiof2_clk_a_pins[] = {
2815 /* SCK */
2816 RCAR_GP_PIN(1, 9),
2817};
2818static const unsigned int msiof2_clk_a_mux[] = {
2819 MSIOF2_SCK_A_MARK,
2820};
2821static const unsigned int msiof2_sync_a_pins[] = {
2822 /* SYNC */
2823 RCAR_GP_PIN(1, 8),
2824};
2825static const unsigned int msiof2_sync_a_mux[] = {
2826 MSIOF2_SYNC_A_MARK,
2827};
2828static const unsigned int msiof2_ss1_a_pins[] = {
2829 /* SS1 */
2830 RCAR_GP_PIN(1, 6),
2831};
2832static const unsigned int msiof2_ss1_a_mux[] = {
2833 MSIOF2_SS1_A_MARK,
2834};
2835static const unsigned int msiof2_ss2_a_pins[] = {
2836 /* SS2 */
2837 RCAR_GP_PIN(1, 7),
2838};
2839static const unsigned int msiof2_ss2_a_mux[] = {
2840 MSIOF2_SS2_A_MARK,
2841};
2842static const unsigned int msiof2_txd_a_pins[] = {
2843 /* TXD */
2844 RCAR_GP_PIN(1, 11),
2845};
2846static const unsigned int msiof2_txd_a_mux[] = {
2847 MSIOF2_TXD_A_MARK,
2848};
2849static const unsigned int msiof2_rxd_a_pins[] = {
2850 /* RXD */
2851 RCAR_GP_PIN(1, 10),
2852};
2853static const unsigned int msiof2_rxd_a_mux[] = {
2854 MSIOF2_RXD_A_MARK,
2855};
2856static const unsigned int msiof2_clk_b_pins[] = {
2857 /* SCK */
2858 RCAR_GP_PIN(0, 4),
2859};
2860static const unsigned int msiof2_clk_b_mux[] = {
2861 MSIOF2_SCK_B_MARK,
2862};
2863static const unsigned int msiof2_sync_b_pins[] = {
2864 /* SYNC */
2865 RCAR_GP_PIN(0, 5),
2866};
2867static const unsigned int msiof2_sync_b_mux[] = {
2868 MSIOF2_SYNC_B_MARK,
2869};
2870static const unsigned int msiof2_ss1_b_pins[] = {
2871 /* SS1 */
2872 RCAR_GP_PIN(0, 0),
2873};
2874static const unsigned int msiof2_ss1_b_mux[] = {
2875 MSIOF2_SS1_B_MARK,
2876};
2877static const unsigned int msiof2_ss2_b_pins[] = {
2878 /* SS2 */
2879 RCAR_GP_PIN(0, 1),
2880};
2881static const unsigned int msiof2_ss2_b_mux[] = {
2882 MSIOF2_SS2_B_MARK,
2883};
2884static const unsigned int msiof2_txd_b_pins[] = {
2885 /* TXD */
2886 RCAR_GP_PIN(0, 7),
2887};
2888static const unsigned int msiof2_txd_b_mux[] = {
2889 MSIOF2_TXD_B_MARK,
2890};
2891static const unsigned int msiof2_rxd_b_pins[] = {
2892 /* RXD */
2893 RCAR_GP_PIN(0, 6),
2894};
2895static const unsigned int msiof2_rxd_b_mux[] = {
2896 MSIOF2_RXD_B_MARK,
2897};
2898static const unsigned int msiof2_clk_c_pins[] = {
2899 /* SCK */
2900 RCAR_GP_PIN(2, 12),
2901};
2902static const unsigned int msiof2_clk_c_mux[] = {
2903 MSIOF2_SCK_C_MARK,
2904};
2905static const unsigned int msiof2_sync_c_pins[] = {
2906 /* SYNC */
2907 RCAR_GP_PIN(2, 11),
2908};
2909static const unsigned int msiof2_sync_c_mux[] = {
2910 MSIOF2_SYNC_C_MARK,
2911};
2912static const unsigned int msiof2_ss1_c_pins[] = {
2913 /* SS1 */
2914 RCAR_GP_PIN(2, 10),
2915};
2916static const unsigned int msiof2_ss1_c_mux[] = {
2917 MSIOF2_SS1_C_MARK,
2918};
2919static const unsigned int msiof2_ss2_c_pins[] = {
2920 /* SS2 */
2921 RCAR_GP_PIN(2, 9),
2922};
2923static const unsigned int msiof2_ss2_c_mux[] = {
2924 MSIOF2_SS2_C_MARK,
2925};
2926static const unsigned int msiof2_txd_c_pins[] = {
2927 /* TXD */
2928 RCAR_GP_PIN(2, 14),
2929};
2930static const unsigned int msiof2_txd_c_mux[] = {
2931 MSIOF2_TXD_C_MARK,
2932};
2933static const unsigned int msiof2_rxd_c_pins[] = {
2934 /* RXD */
2935 RCAR_GP_PIN(2, 13),
2936};
2937static const unsigned int msiof2_rxd_c_mux[] = {
2938 MSIOF2_RXD_C_MARK,
2939};
2940static const unsigned int msiof2_clk_d_pins[] = {
2941 /* SCK */
2942 RCAR_GP_PIN(0, 8),
2943};
2944static const unsigned int msiof2_clk_d_mux[] = {
2945 MSIOF2_SCK_D_MARK,
2946};
2947static const unsigned int msiof2_sync_d_pins[] = {
2948 /* SYNC */
2949 RCAR_GP_PIN(0, 9),
2950};
2951static const unsigned int msiof2_sync_d_mux[] = {
2952 MSIOF2_SYNC_D_MARK,
2953};
2954static const unsigned int msiof2_ss1_d_pins[] = {
2955 /* SS1 */
2956 RCAR_GP_PIN(0, 12),
2957};
2958static const unsigned int msiof2_ss1_d_mux[] = {
2959 MSIOF2_SS1_D_MARK,
2960};
2961static const unsigned int msiof2_ss2_d_pins[] = {
2962 /* SS2 */
2963 RCAR_GP_PIN(0, 13),
2964};
2965static const unsigned int msiof2_ss2_d_mux[] = {
2966 MSIOF2_SS2_D_MARK,
2967};
2968static const unsigned int msiof2_txd_d_pins[] = {
2969 /* TXD */
2970 RCAR_GP_PIN(0, 11),
2971};
2972static const unsigned int msiof2_txd_d_mux[] = {
2973 MSIOF2_TXD_D_MARK,
2974};
2975static const unsigned int msiof2_rxd_d_pins[] = {
2976 /* RXD */
2977 RCAR_GP_PIN(0, 10),
2978};
2979static const unsigned int msiof2_rxd_d_mux[] = {
2980 MSIOF2_RXD_D_MARK,
2981};
2982/* - MSIOF3 ----------------------------------------------------------------- */
2983static const unsigned int msiof3_clk_a_pins[] = {
2984 /* SCK */
2985 RCAR_GP_PIN(0, 0),
2986};
2987static const unsigned int msiof3_clk_a_mux[] = {
2988 MSIOF3_SCK_A_MARK,
2989};
2990static const unsigned int msiof3_sync_a_pins[] = {
2991 /* SYNC */
2992 RCAR_GP_PIN(0, 1),
2993};
2994static const unsigned int msiof3_sync_a_mux[] = {
2995 MSIOF3_SYNC_A_MARK,
2996};
2997static const unsigned int msiof3_ss1_a_pins[] = {
2998 /* SS1 */
2999 RCAR_GP_PIN(0, 14),
3000};
3001static const unsigned int msiof3_ss1_a_mux[] = {
3002 MSIOF3_SS1_A_MARK,
3003};
3004static const unsigned int msiof3_ss2_a_pins[] = {
3005 /* SS2 */
3006 RCAR_GP_PIN(0, 15),
3007};
3008static const unsigned int msiof3_ss2_a_mux[] = {
3009 MSIOF3_SS2_A_MARK,
3010};
3011static const unsigned int msiof3_txd_a_pins[] = {
3012 /* TXD */
3013 RCAR_GP_PIN(0, 3),
3014};
3015static const unsigned int msiof3_txd_a_mux[] = {
3016 MSIOF3_TXD_A_MARK,
3017};
3018static const unsigned int msiof3_rxd_a_pins[] = {
3019 /* RXD */
3020 RCAR_GP_PIN(0, 2),
3021};
3022static const unsigned int msiof3_rxd_a_mux[] = {
3023 MSIOF3_RXD_A_MARK,
3024};
3025static const unsigned int msiof3_clk_b_pins[] = {
3026 /* SCK */
3027 RCAR_GP_PIN(1, 2),
3028};
3029static const unsigned int msiof3_clk_b_mux[] = {
3030 MSIOF3_SCK_B_MARK,
3031};
3032static const unsigned int msiof3_sync_b_pins[] = {
3033 /* SYNC */
3034 RCAR_GP_PIN(1, 0),
3035};
3036static const unsigned int msiof3_sync_b_mux[] = {
3037 MSIOF3_SYNC_B_MARK,
3038};
3039static const unsigned int msiof3_ss1_b_pins[] = {
3040 /* SS1 */
3041 RCAR_GP_PIN(1, 4),
3042};
3043static const unsigned int msiof3_ss1_b_mux[] = {
3044 MSIOF3_SS1_B_MARK,
3045};
3046static const unsigned int msiof3_ss2_b_pins[] = {
3047 /* SS2 */
3048 RCAR_GP_PIN(1, 5),
3049};
3050static const unsigned int msiof3_ss2_b_mux[] = {
3051 MSIOF3_SS2_B_MARK,
3052};
3053static const unsigned int msiof3_txd_b_pins[] = {
3054 /* TXD */
3055 RCAR_GP_PIN(1, 1),
3056};
3057static const unsigned int msiof3_txd_b_mux[] = {
3058 MSIOF3_TXD_B_MARK,
3059};
3060static const unsigned int msiof3_rxd_b_pins[] = {
3061 /* RXD */
3062 RCAR_GP_PIN(1, 3),
3063};
3064static const unsigned int msiof3_rxd_b_mux[] = {
3065 MSIOF3_RXD_B_MARK,
3066};
3067static const unsigned int msiof3_clk_c_pins[] = {
3068 /* SCK */
3069 RCAR_GP_PIN(1, 12),
3070};
3071static const unsigned int msiof3_clk_c_mux[] = {
3072 MSIOF3_SCK_C_MARK,
3073};
3074static const unsigned int msiof3_sync_c_pins[] = {
3075 /* SYNC */
3076 RCAR_GP_PIN(1, 13),
3077};
3078static const unsigned int msiof3_sync_c_mux[] = {
3079 MSIOF3_SYNC_C_MARK,
3080};
3081static const unsigned int msiof3_txd_c_pins[] = {
3082 /* TXD */
3083 RCAR_GP_PIN(1, 15),
3084};
3085static const unsigned int msiof3_txd_c_mux[] = {
3086 MSIOF3_TXD_C_MARK,
3087};
3088static const unsigned int msiof3_rxd_c_pins[] = {
3089 /* RXD */
3090 RCAR_GP_PIN(1, 14),
3091};
3092static const unsigned int msiof3_rxd_c_mux[] = {
3093 MSIOF3_RXD_C_MARK,
3094};
3095static const unsigned int msiof3_clk_d_pins[] = {
3096 /* SCK */
3097 RCAR_GP_PIN(1, 22),
3098};
3099static const unsigned int msiof3_clk_d_mux[] = {
3100 MSIOF3_SCK_D_MARK,
3101};
3102static const unsigned int msiof3_sync_d_pins[] = {
3103 /* SYNC */
3104 RCAR_GP_PIN(1, 23),
3105};
3106static const unsigned int msiof3_sync_d_mux[] = {
3107 MSIOF3_SYNC_D_MARK,
3108};
3109static const unsigned int msiof3_ss1_d_pins[] = {
3110 /* SS1 */
3111 RCAR_GP_PIN(1, 26),
3112};
3113static const unsigned int msiof3_ss1_d_mux[] = {
3114 MSIOF3_SS1_D_MARK,
3115};
3116static const unsigned int msiof3_txd_d_pins[] = {
3117 /* TXD */
3118 RCAR_GP_PIN(1, 25),
3119};
3120static const unsigned int msiof3_txd_d_mux[] = {
3121 MSIOF3_TXD_D_MARK,
3122};
3123static const unsigned int msiof3_rxd_d_pins[] = {
3124 /* RXD */
3125 RCAR_GP_PIN(1, 24),
3126};
3127static const unsigned int msiof3_rxd_d_mux[] = {
3128 MSIOF3_RXD_D_MARK,
3129};
3130static const unsigned int msiof3_clk_e_pins[] = {
3131 /* SCK */
3132 RCAR_GP_PIN(2, 3),
3133};
3134static const unsigned int msiof3_clk_e_mux[] = {
3135 MSIOF3_SCK_E_MARK,
3136};
3137static const unsigned int msiof3_sync_e_pins[] = {
3138 /* SYNC */
3139 RCAR_GP_PIN(2, 2),
3140};
3141static const unsigned int msiof3_sync_e_mux[] = {
3142 MSIOF3_SYNC_E_MARK,
3143};
3144static const unsigned int msiof3_ss1_e_pins[] = {
3145 /* SS1 */
3146 RCAR_GP_PIN(2, 1),
3147};
3148static const unsigned int msiof3_ss1_e_mux[] = {
3149 MSIOF3_SS1_E_MARK,
3150};
3151static const unsigned int msiof3_ss2_e_pins[] = {
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]3152 /* SS2 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3153 RCAR_GP_PIN(2, 0),
3154};
3155static const unsigned int msiof3_ss2_e_mux[] = {
3156 MSIOF3_SS2_E_MARK,
3157};
3158static const unsigned int msiof3_txd_e_pins[] = {
3159 /* TXD */
3160 RCAR_GP_PIN(2, 5),
3161};
3162static const unsigned int msiof3_txd_e_mux[] = {
3163 MSIOF3_TXD_E_MARK,
3164};
3165static const unsigned int msiof3_rxd_e_pins[] = {
3166 /* RXD */
3167 RCAR_GP_PIN(2, 4),
3168};
3169static const unsigned int msiof3_rxd_e_mux[] = {
3170 MSIOF3_RXD_E_MARK,
3171};
3172
3173/* - PWM0 --------------------------------------------------------------------*/
3174static const unsigned int pwm0_pins[] = {
3175 /* PWM */
3176 RCAR_GP_PIN(2, 6),
3177};
3178static const unsigned int pwm0_mux[] = {
3179 PWM0_MARK,
3180};
3181/* - PWM1 --------------------------------------------------------------------*/
3182static const unsigned int pwm1_a_pins[] = {
3183 /* PWM */
3184 RCAR_GP_PIN(2, 7),
3185};
3186static const unsigned int pwm1_a_mux[] = {
3187 PWM1_A_MARK,
3188};
3189static const unsigned int pwm1_b_pins[] = {
3190 /* PWM */
3191 RCAR_GP_PIN(1, 8),
3192};
3193static const unsigned int pwm1_b_mux[] = {
3194 PWM1_B_MARK,
3195};
3196/* - PWM2 --------------------------------------------------------------------*/
3197static const unsigned int pwm2_a_pins[] = {
3198 /* PWM */
3199 RCAR_GP_PIN(2, 8),
3200};
3201static const unsigned int pwm2_a_mux[] = {
3202 PWM2_A_MARK,
3203};
3204static const unsigned int pwm2_b_pins[] = {
3205 /* PWM */
3206 RCAR_GP_PIN(1, 11),
3207};
3208static const unsigned int pwm2_b_mux[] = {
3209 PWM2_B_MARK,
3210};
3211/* - PWM3 --------------------------------------------------------------------*/
3212static const unsigned int pwm3_a_pins[] = {
3213 /* PWM */
3214 RCAR_GP_PIN(1, 0),
3215};
3216static const unsigned int pwm3_a_mux[] = {
3217 PWM3_A_MARK,
3218};
3219static const unsigned int pwm3_b_pins[] = {
3220 /* PWM */
3221 RCAR_GP_PIN(2, 2),
3222};
3223static const unsigned int pwm3_b_mux[] = {
3224 PWM3_B_MARK,
3225};
3226/* - PWM4 --------------------------------------------------------------------*/
3227static const unsigned int pwm4_a_pins[] = {
3228 /* PWM */
3229 RCAR_GP_PIN(1, 1),
3230};
3231static const unsigned int pwm4_a_mux[] = {
3232 PWM4_A_MARK,
3233};
3234static const unsigned int pwm4_b_pins[] = {
3235 /* PWM */
3236 RCAR_GP_PIN(2, 3),
3237};
3238static const unsigned int pwm4_b_mux[] = {
3239 PWM4_B_MARK,
3240};
3241/* - PWM5 --------------------------------------------------------------------*/
3242static const unsigned int pwm5_a_pins[] = {
3243 /* PWM */
3244 RCAR_GP_PIN(1, 2),
3245};
3246static const unsigned int pwm5_a_mux[] = {
3247 PWM5_A_MARK,
3248};
3249static const unsigned int pwm5_b_pins[] = {
3250 /* PWM */
3251 RCAR_GP_PIN(2, 4),
3252};
3253static const unsigned int pwm5_b_mux[] = {
3254 PWM5_B_MARK,
3255};
3256/* - PWM6 --------------------------------------------------------------------*/
3257static const unsigned int pwm6_a_pins[] = {
3258 /* PWM */
3259 RCAR_GP_PIN(1, 3),
3260};
3261static const unsigned int pwm6_a_mux[] = {
3262 PWM6_A_MARK,
3263};
3264static const unsigned int pwm6_b_pins[] = {
3265 /* PWM */
3266 RCAR_GP_PIN(2, 5),
3267};
3268static const unsigned int pwm6_b_mux[] = {
3269 PWM6_B_MARK,
3270};
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]3271#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3272
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3273/* - QSPI0 ------------------------------------------------------------------ */
3274static const unsigned int qspi0_ctrl_pins[] = {
3275 /* QSPI0_SPCLK, QSPI0_SSL */
3276 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3277};
3278static const unsigned int qspi0_ctrl_mux[] = {
3279 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3280};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3281static const unsigned int qspi0_data_pins[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3282 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3283 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3284 /* QSPI0_IO2, QSPI0_IO3 */
3285 PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3286};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3287static const unsigned int qspi0_data_mux[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3288 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3289 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3290};
3291/* - QSPI1 ------------------------------------------------------------------ */
3292static const unsigned int qspi1_ctrl_pins[] = {
3293 /* QSPI1_SPCLK, QSPI1_SSL */
3294 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3295};
3296static const unsigned int qspi1_ctrl_mux[] = {
3297 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3298};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3299static const unsigned int qspi1_data_pins[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3300 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3301 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3302 /* QSPI1_IO2, QSPI1_IO3 */
3303 PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3304};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3305static const unsigned int qspi1_data_mux[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3306 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3307 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3308};
3309
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3310/* - SATA --------------------------------------------------------------------*/
3311static const unsigned int sata0_devslp_a_pins[] = {
3312 /* DEVSLP */
3313 RCAR_GP_PIN(6, 16),
3314};
3315static const unsigned int sata0_devslp_a_mux[] = {
3316 SATA_DEVSLP_A_MARK,
3317};
3318static const unsigned int sata0_devslp_b_pins[] = {
3319 /* DEVSLP */
3320 RCAR_GP_PIN(4, 6),
3321};
3322static const unsigned int sata0_devslp_b_mux[] = {
3323 SATA_DEVSLP_B_MARK,
3324};
3325
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3326/* - SCIF0 ------------------------------------------------------------------ */
3327static const unsigned int scif0_data_pins[] = {
3328 /* RX, TX */
3329 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3330};
3331static const unsigned int scif0_data_mux[] = {
3332 RX0_MARK, TX0_MARK,
3333};
3334static const unsigned int scif0_clk_pins[] = {
3335 /* SCK */
3336 RCAR_GP_PIN(5, 0),
3337};
3338static const unsigned int scif0_clk_mux[] = {
3339 SCK0_MARK,
3340};
3341static const unsigned int scif0_ctrl_pins[] = {
3342 /* RTS, CTS */
3343 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3344};
3345static const unsigned int scif0_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3346 RTS0_N_MARK, CTS0_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3347};
3348/* - SCIF1 ------------------------------------------------------------------ */
3349static const unsigned int scif1_data_a_pins[] = {
3350 /* RX, TX */
3351 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3352};
3353static const unsigned int scif1_data_a_mux[] = {
3354 RX1_A_MARK, TX1_A_MARK,
3355};
3356static const unsigned int scif1_clk_pins[] = {
3357 /* SCK */
3358 RCAR_GP_PIN(6, 21),
3359};
3360static const unsigned int scif1_clk_mux[] = {
3361 SCK1_MARK,
3362};
3363static const unsigned int scif1_ctrl_pins[] = {
3364 /* RTS, CTS */
3365 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3366};
3367static const unsigned int scif1_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3368 RTS1_N_MARK, CTS1_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3369};
3370
3371static const unsigned int scif1_data_b_pins[] = {
3372 /* RX, TX */
3373 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3374};
3375static const unsigned int scif1_data_b_mux[] = {
3376 RX1_B_MARK, TX1_B_MARK,
3377};
3378/* - SCIF2 ------------------------------------------------------------------ */
3379static const unsigned int scif2_data_a_pins[] = {
3380 /* RX, TX */
3381 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3382};
3383static const unsigned int scif2_data_a_mux[] = {
3384 RX2_A_MARK, TX2_A_MARK,
3385};
3386static const unsigned int scif2_clk_pins[] = {
3387 /* SCK */
3388 RCAR_GP_PIN(5, 9),
3389};
3390static const unsigned int scif2_clk_mux[] = {
3391 SCK2_MARK,
3392};
3393static const unsigned int scif2_data_b_pins[] = {
3394 /* RX, TX */
3395 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3396};
3397static const unsigned int scif2_data_b_mux[] = {
3398 RX2_B_MARK, TX2_B_MARK,
3399};
3400/* - SCIF3 ------------------------------------------------------------------ */
3401static const unsigned int scif3_data_a_pins[] = {
3402 /* RX, TX */
3403 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3404};
3405static const unsigned int scif3_data_a_mux[] = {
3406 RX3_A_MARK, TX3_A_MARK,
3407};
3408static const unsigned int scif3_clk_pins[] = {
3409 /* SCK */
3410 RCAR_GP_PIN(1, 22),
3411};
3412static const unsigned int scif3_clk_mux[] = {
3413 SCK3_MARK,
3414};
3415static const unsigned int scif3_ctrl_pins[] = {
3416 /* RTS, CTS */
3417 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3418};
3419static const unsigned int scif3_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3420 RTS3_N_MARK, CTS3_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3421};
3422static const unsigned int scif3_data_b_pins[] = {
3423 /* RX, TX */
3424 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3425};
3426static const unsigned int scif3_data_b_mux[] = {
3427 RX3_B_MARK, TX3_B_MARK,
3428};
3429/* - SCIF4 ------------------------------------------------------------------ */
3430static const unsigned int scif4_data_a_pins[] = {
3431 /* RX, TX */
3432 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3433};
3434static const unsigned int scif4_data_a_mux[] = {
3435 RX4_A_MARK, TX4_A_MARK,
3436};
3437static const unsigned int scif4_clk_a_pins[] = {
3438 /* SCK */
3439 RCAR_GP_PIN(2, 10),
3440};
3441static const unsigned int scif4_clk_a_mux[] = {
3442 SCK4_A_MARK,
3443};
3444static const unsigned int scif4_ctrl_a_pins[] = {
3445 /* RTS, CTS */
3446 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3447};
3448static const unsigned int scif4_ctrl_a_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3449 RTS4_N_A_MARK, CTS4_N_A_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3450};
3451static const unsigned int scif4_data_b_pins[] = {
3452 /* RX, TX */
3453 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3454};
3455static const unsigned int scif4_data_b_mux[] = {
3456 RX4_B_MARK, TX4_B_MARK,
3457};
3458static const unsigned int scif4_clk_b_pins[] = {
3459 /* SCK */
3460 RCAR_GP_PIN(1, 5),
3461};
3462static const unsigned int scif4_clk_b_mux[] = {
3463 SCK4_B_MARK,
3464};
3465static const unsigned int scif4_ctrl_b_pins[] = {
3466 /* RTS, CTS */
3467 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3468};
3469static const unsigned int scif4_ctrl_b_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3470 RTS4_N_B_MARK, CTS4_N_B_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3471};
3472static const unsigned int scif4_data_c_pins[] = {
3473 /* RX, TX */
3474 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3475};
3476static const unsigned int scif4_data_c_mux[] = {
3477 RX4_C_MARK, TX4_C_MARK,
3478};
3479static const unsigned int scif4_clk_c_pins[] = {
3480 /* SCK */
3481 RCAR_GP_PIN(0, 8),
3482};
3483static const unsigned int scif4_clk_c_mux[] = {
3484 SCK4_C_MARK,
3485};
3486static const unsigned int scif4_ctrl_c_pins[] = {
3487 /* RTS, CTS */
3488 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3489};
3490static const unsigned int scif4_ctrl_c_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3491 RTS4_N_C_MARK, CTS4_N_C_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3492};
3493/* - SCIF5 ------------------------------------------------------------------ */
3494static const unsigned int scif5_data_a_pins[] = {
3495 /* RX, TX */
3496 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3497};
3498static const unsigned int scif5_data_a_mux[] = {
3499 RX5_A_MARK, TX5_A_MARK,
3500};
3501static const unsigned int scif5_clk_a_pins[] = {
3502 /* SCK */
3503 RCAR_GP_PIN(6, 21),
3504};
3505static const unsigned int scif5_clk_a_mux[] = {
3506 SCK5_A_MARK,
3507};
3508static const unsigned int scif5_data_b_pins[] = {
3509 /* RX, TX */
3510 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3511};
3512static const unsigned int scif5_data_b_mux[] = {
3513 RX5_B_MARK, TX5_B_MARK,
3514};
3515static const unsigned int scif5_clk_b_pins[] = {
3516 /* SCK */
3517 RCAR_GP_PIN(5, 0),
3518};
3519static const unsigned int scif5_clk_b_mux[] = {
3520 SCK5_B_MARK,
3521};
3522
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3523/* - SCIF Clock ------------------------------------------------------------- */
3524static const unsigned int scif_clk_a_pins[] = {
3525 /* SCIF_CLK */
3526 RCAR_GP_PIN(6, 23),
3527};
3528static const unsigned int scif_clk_a_mux[] = {
3529 SCIF_CLK_A_MARK,
3530};
3531static const unsigned int scif_clk_b_pins[] = {
3532 /* SCIF_CLK */
3533 RCAR_GP_PIN(5, 9),
3534};
3535static const unsigned int scif_clk_b_mux[] = {
3536 SCIF_CLK_B_MARK,
3537};
3538
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3539/* - SDHI0 ------------------------------------------------------------------ */
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3540static const unsigned int sdhi0_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3541 /* D[0:3] */
3542 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3543 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3544};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3545static const unsigned int sdhi0_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3546 SD0_DAT0_MARK, SD0_DAT1_MARK,
3547 SD0_DAT2_MARK, SD0_DAT3_MARK,
3548};
3549static const unsigned int sdhi0_ctrl_pins[] = {
3550 /* CLK, CMD */
3551 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3552};
3553static const unsigned int sdhi0_ctrl_mux[] = {
3554 SD0_CLK_MARK, SD0_CMD_MARK,
3555};
3556static const unsigned int sdhi0_cd_pins[] = {
3557 /* CD */
3558 RCAR_GP_PIN(3, 12),
3559};
3560static const unsigned int sdhi0_cd_mux[] = {
3561 SD0_CD_MARK,
3562};
3563static const unsigned int sdhi0_wp_pins[] = {
3564 /* WP */
3565 RCAR_GP_PIN(3, 13),
3566};
3567static const unsigned int sdhi0_wp_mux[] = {
3568 SD0_WP_MARK,
3569};
3570/* - SDHI1 ------------------------------------------------------------------ */
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3571static const unsigned int sdhi1_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3572 /* D[0:3] */
3573 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3574 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3575};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3576static const unsigned int sdhi1_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3577 SD1_DAT0_MARK, SD1_DAT1_MARK,
3578 SD1_DAT2_MARK, SD1_DAT3_MARK,
3579};
3580static const unsigned int sdhi1_ctrl_pins[] = {
3581 /* CLK, CMD */
3582 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3583};
3584static const unsigned int sdhi1_ctrl_mux[] = {
3585 SD1_CLK_MARK, SD1_CMD_MARK,
3586};
3587static const unsigned int sdhi1_cd_pins[] = {
3588 /* CD */
3589 RCAR_GP_PIN(3, 14),
3590};
3591static const unsigned int sdhi1_cd_mux[] = {
3592 SD1_CD_MARK,
3593};
3594static const unsigned int sdhi1_wp_pins[] = {
3595 /* WP */
3596 RCAR_GP_PIN(3, 15),
3597};
3598static const unsigned int sdhi1_wp_mux[] = {
3599 SD1_WP_MARK,
3600};
3601/* - SDHI2 ------------------------------------------------------------------ */
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3602static const unsigned int sdhi2_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3603 /* D[0:7] */
3604 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3605 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3606 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3607 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3608};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3609static const unsigned int sdhi2_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3610 SD2_DAT0_MARK, SD2_DAT1_MARK,
3611 SD2_DAT2_MARK, SD2_DAT3_MARK,
3612 SD2_DAT4_MARK, SD2_DAT5_MARK,
3613 SD2_DAT6_MARK, SD2_DAT7_MARK,
3614};
3615static const unsigned int sdhi2_ctrl_pins[] = {
3616 /* CLK, CMD */
3617 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3618};
3619static const unsigned int sdhi2_ctrl_mux[] = {
3620 SD2_CLK_MARK, SD2_CMD_MARK,
3621};
3622static const unsigned int sdhi2_cd_a_pins[] = {
3623 /* CD */
3624 RCAR_GP_PIN(4, 13),
3625};
3626static const unsigned int sdhi2_cd_a_mux[] = {
3627 SD2_CD_A_MARK,
3628};
3629static const unsigned int sdhi2_cd_b_pins[] = {
3630 /* CD */
3631 RCAR_GP_PIN(5, 10),
3632};
3633static const unsigned int sdhi2_cd_b_mux[] = {
3634 SD2_CD_B_MARK,
3635};
3636static const unsigned int sdhi2_wp_a_pins[] = {
3637 /* WP */
3638 RCAR_GP_PIN(4, 14),
3639};
3640static const unsigned int sdhi2_wp_a_mux[] = {
3641 SD2_WP_A_MARK,
3642};
3643static const unsigned int sdhi2_wp_b_pins[] = {
3644 /* WP */
3645 RCAR_GP_PIN(5, 11),
3646};
3647static const unsigned int sdhi2_wp_b_mux[] = {
3648 SD2_WP_B_MARK,
3649};
3650static const unsigned int sdhi2_ds_pins[] = {
3651 /* DS */
3652 RCAR_GP_PIN(4, 6),
3653};
3654static const unsigned int sdhi2_ds_mux[] = {
3655 SD2_DS_MARK,
3656};
3657/* - SDHI3 ------------------------------------------------------------------ */
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3658static const unsigned int sdhi3_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3659 /* D[0:7] */
3660 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3661 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3662 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3663 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3664};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3665static const unsigned int sdhi3_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3666 SD3_DAT0_MARK, SD3_DAT1_MARK,
3667 SD3_DAT2_MARK, SD3_DAT3_MARK,
3668 SD3_DAT4_MARK, SD3_DAT5_MARK,
3669 SD3_DAT6_MARK, SD3_DAT7_MARK,
3670};
3671static const unsigned int sdhi3_ctrl_pins[] = {
3672 /* CLK, CMD */
3673 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3674};
3675static const unsigned int sdhi3_ctrl_mux[] = {
3676 SD3_CLK_MARK, SD3_CMD_MARK,
3677};
3678static const unsigned int sdhi3_cd_pins[] = {
3679 /* CD */
3680 RCAR_GP_PIN(4, 15),
3681};
3682static const unsigned int sdhi3_cd_mux[] = {
3683 SD3_CD_MARK,
3684};
3685static const unsigned int sdhi3_wp_pins[] = {
3686 /* WP */
3687 RCAR_GP_PIN(4, 16),
3688};
3689static const unsigned int sdhi3_wp_mux[] = {
3690 SD3_WP_MARK,
3691};
3692static const unsigned int sdhi3_ds_pins[] = {
3693 /* DS */
3694 RCAR_GP_PIN(4, 17),
3695};
3696static const unsigned int sdhi3_ds_mux[] = {
3697 SD3_DS_MARK,
3698};
3699
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]3700#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3701/* - SSI -------------------------------------------------------------------- */
3702static const unsigned int ssi0_data_pins[] = {
3703 /* SDATA */
3704 RCAR_GP_PIN(6, 2),
3705};
3706static const unsigned int ssi0_data_mux[] = {
3707 SSI_SDATA0_MARK,
3708};
3709static const unsigned int ssi01239_ctrl_pins[] = {
3710 /* SCK, WS */
3711 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3712};
3713static const unsigned int ssi01239_ctrl_mux[] = {
3714 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3715};
3716static const unsigned int ssi1_data_a_pins[] = {
3717 /* SDATA */
3718 RCAR_GP_PIN(6, 3),
3719};
3720static const unsigned int ssi1_data_a_mux[] = {
3721 SSI_SDATA1_A_MARK,
3722};
3723static const unsigned int ssi1_data_b_pins[] = {
3724 /* SDATA */
3725 RCAR_GP_PIN(5, 12),
3726};
3727static const unsigned int ssi1_data_b_mux[] = {
3728 SSI_SDATA1_B_MARK,
3729};
3730static const unsigned int ssi1_ctrl_a_pins[] = {
3731 /* SCK, WS */
3732 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3733};
3734static const unsigned int ssi1_ctrl_a_mux[] = {
3735 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3736};
3737static const unsigned int ssi1_ctrl_b_pins[] = {
3738 /* SCK, WS */
3739 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3740};
3741static const unsigned int ssi1_ctrl_b_mux[] = {
3742 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3743};
3744static const unsigned int ssi2_data_a_pins[] = {
3745 /* SDATA */
3746 RCAR_GP_PIN(6, 4),
3747};
3748static const unsigned int ssi2_data_a_mux[] = {
3749 SSI_SDATA2_A_MARK,
3750};
3751static const unsigned int ssi2_data_b_pins[] = {
3752 /* SDATA */
3753 RCAR_GP_PIN(5, 13),
3754};
3755static const unsigned int ssi2_data_b_mux[] = {
3756 SSI_SDATA2_B_MARK,
3757};
3758static const unsigned int ssi2_ctrl_a_pins[] = {
3759 /* SCK, WS */
3760 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3761};
3762static const unsigned int ssi2_ctrl_a_mux[] = {
3763 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3764};
3765static const unsigned int ssi2_ctrl_b_pins[] = {
3766 /* SCK, WS */
3767 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3768};
3769static const unsigned int ssi2_ctrl_b_mux[] = {
3770 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3771};
3772static const unsigned int ssi3_data_pins[] = {
3773 /* SDATA */
3774 RCAR_GP_PIN(6, 7),
3775};
3776static const unsigned int ssi3_data_mux[] = {
3777 SSI_SDATA3_MARK,
3778};
3779static const unsigned int ssi349_ctrl_pins[] = {
3780 /* SCK, WS */
3781 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3782};
3783static const unsigned int ssi349_ctrl_mux[] = {
3784 SSI_SCK349_MARK, SSI_WS349_MARK,
3785};
3786static const unsigned int ssi4_data_pins[] = {
3787 /* SDATA */
3788 RCAR_GP_PIN(6, 10),
3789};
3790static const unsigned int ssi4_data_mux[] = {
3791 SSI_SDATA4_MARK,
3792};
3793static const unsigned int ssi4_ctrl_pins[] = {
3794 /* SCK, WS */
3795 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3796};
3797static const unsigned int ssi4_ctrl_mux[] = {
3798 SSI_SCK4_MARK, SSI_WS4_MARK,
3799};
3800static const unsigned int ssi5_data_pins[] = {
3801 /* SDATA */
3802 RCAR_GP_PIN(6, 13),
3803};
3804static const unsigned int ssi5_data_mux[] = {
3805 SSI_SDATA5_MARK,
3806};
3807static const unsigned int ssi5_ctrl_pins[] = {
3808 /* SCK, WS */
3809 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3810};
3811static const unsigned int ssi5_ctrl_mux[] = {
3812 SSI_SCK5_MARK, SSI_WS5_MARK,
3813};
3814static const unsigned int ssi6_data_pins[] = {
3815 /* SDATA */
3816 RCAR_GP_PIN(6, 16),
3817};
3818static const unsigned int ssi6_data_mux[] = {
3819 SSI_SDATA6_MARK,
3820};
3821static const unsigned int ssi6_ctrl_pins[] = {
3822 /* SCK, WS */
3823 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3824};
3825static const unsigned int ssi6_ctrl_mux[] = {
3826 SSI_SCK6_MARK, SSI_WS6_MARK,
3827};
3828static const unsigned int ssi7_data_pins[] = {
3829 /* SDATA */
3830 RCAR_GP_PIN(6, 19),
3831};
3832static const unsigned int ssi7_data_mux[] = {
3833 SSI_SDATA7_MARK,
3834};
3835static const unsigned int ssi78_ctrl_pins[] = {
3836 /* SCK, WS */
3837 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3838};
3839static const unsigned int ssi78_ctrl_mux[] = {
3840 SSI_SCK78_MARK, SSI_WS78_MARK,
3841};
3842static const unsigned int ssi8_data_pins[] = {
3843 /* SDATA */
3844 RCAR_GP_PIN(6, 20),
3845};
3846static const unsigned int ssi8_data_mux[] = {
3847 SSI_SDATA8_MARK,
3848};
3849static const unsigned int ssi9_data_a_pins[] = {
3850 /* SDATA */
3851 RCAR_GP_PIN(6, 21),
3852};
3853static const unsigned int ssi9_data_a_mux[] = {
3854 SSI_SDATA9_A_MARK,
3855};
3856static const unsigned int ssi9_data_b_pins[] = {
3857 /* SDATA */
3858 RCAR_GP_PIN(5, 14),
3859};
3860static const unsigned int ssi9_data_b_mux[] = {
3861 SSI_SDATA9_B_MARK,
3862};
3863static const unsigned int ssi9_ctrl_a_pins[] = {
3864 /* SCK, WS */
3865 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3866};
3867static const unsigned int ssi9_ctrl_a_mux[] = {
3868 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3869};
3870static const unsigned int ssi9_ctrl_b_pins[] = {
3871 /* SCK, WS */
3872 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3873};
3874static const unsigned int ssi9_ctrl_b_mux[] = {
3875 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3876};
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]3877#endif
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3878
3879/* - TMU -------------------------------------------------------------------- */
3880static const unsigned int tmu_tclk1_a_pins[] = {
3881 /* TCLK */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3882 RCAR_GP_PIN(6, 23),
3883};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3884static const unsigned int tmu_tclk1_a_mux[] = {
3885 TCLK1_A_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3886};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3887static const unsigned int tmu_tclk1_b_pins[] = {
3888 /* TCLK */
3889 RCAR_GP_PIN(5, 19),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3890};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3891static const unsigned int tmu_tclk1_b_mux[] = {
3892 TCLK1_B_MARK,
3893};
3894static const unsigned int tmu_tclk2_a_pins[] = {
3895 /* TCLK */
3896 RCAR_GP_PIN(6, 19),
3897};
3898static const unsigned int tmu_tclk2_a_mux[] = {
3899 TCLK2_A_MARK,
3900};
3901static const unsigned int tmu_tclk2_b_pins[] = {
3902 /* TCLK */
3903 RCAR_GP_PIN(6, 28),
3904};
3905static const unsigned int tmu_tclk2_b_mux[] = {
3906 TCLK2_B_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3907};
3908
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]3909/* - TPU ------------------------------------------------------------------- */
3910static const unsigned int tpu_to0_pins[] = {
3911 /* TPU0TO0 */
3912 RCAR_GP_PIN(6, 28),
3913};
3914static const unsigned int tpu_to0_mux[] = {
3915 TPU0TO0_MARK,
3916};
3917static const unsigned int tpu_to1_pins[] = {
3918 /* TPU0TO1 */
3919 RCAR_GP_PIN(6, 29),
3920};
3921static const unsigned int tpu_to1_mux[] = {
3922 TPU0TO1_MARK,
3923};
3924static const unsigned int tpu_to2_pins[] = {
3925 /* TPU0TO2 */
3926 RCAR_GP_PIN(6, 30),
3927};
3928static const unsigned int tpu_to2_mux[] = {
3929 TPU0TO2_MARK,
3930};
3931static const unsigned int tpu_to3_pins[] = {
3932 /* TPU0TO3 */
3933 RCAR_GP_PIN(6, 31),
3934};
3935static const unsigned int tpu_to3_mux[] = {
3936 TPU0TO3_MARK,
3937};
3938
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3939/* - USB0 ------------------------------------------------------------------- */
3940static const unsigned int usb0_pins[] = {
3941 /* PWEN, OVC */
3942 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3943};
3944static const unsigned int usb0_mux[] = {
3945 USB0_PWEN_MARK, USB0_OVC_MARK,
3946};
3947/* - USB1 ------------------------------------------------------------------- */
3948static const unsigned int usb1_pins[] = {
3949 /* PWEN, OVC */
3950 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3951};
3952static const unsigned int usb1_mux[] = {
3953 USB1_PWEN_MARK, USB1_OVC_MARK,
3954};
3955/* - USB2 ------------------------------------------------------------------- */
3956static const unsigned int usb2_pins[] = {
3957 /* PWEN, OVC */
3958 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3959};
3960static const unsigned int usb2_mux[] = {
3961 USB2_PWEN_MARK, USB2_OVC_MARK,
3962};
3963/* - USB2_CH3 --------------------------------------------------------------- */
3964static const unsigned int usb2_ch3_pins[] = {
3965 /* PWEN, OVC */
3966 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3967};
3968static const unsigned int usb2_ch3_mux[] = {
3969 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3970};
3971
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3972/* - USB30 ------------------------------------------------------------------ */
3973static const unsigned int usb30_pins[] = {
3974 /* PWEN, OVC */
3975 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3976};
3977static const unsigned int usb30_mux[] = {
3978 USB30_PWEN_MARK, USB30_OVC_MARK,
3979};
3980
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]3981#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3982/* - VIN4 ------------------------------------------------------------------- */
3983static const unsigned int vin4_data18_a_pins[] = {
3984 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3985 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3986 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3987 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3988 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3989 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3990 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3991 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3992 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3993};
3994static const unsigned int vin4_data18_a_mux[] = {
3995 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3996 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3997 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3998 VI4_DATA10_MARK, VI4_DATA11_MARK,
3999 VI4_DATA12_MARK, VI4_DATA13_MARK,
4000 VI4_DATA14_MARK, VI4_DATA15_MARK,
4001 VI4_DATA18_MARK, VI4_DATA19_MARK,
4002 VI4_DATA20_MARK, VI4_DATA21_MARK,
4003 VI4_DATA22_MARK, VI4_DATA23_MARK,
4004};
4005static const unsigned int vin4_data18_b_pins[] = {
4006 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4007 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4008 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4009 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4010 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4011 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4012 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4013 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4014 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4015};
4016static const unsigned int vin4_data18_b_mux[] = {
4017 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4018 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4019 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4020 VI4_DATA10_MARK, VI4_DATA11_MARK,
4021 VI4_DATA12_MARK, VI4_DATA13_MARK,
4022 VI4_DATA14_MARK, VI4_DATA15_MARK,
4023 VI4_DATA18_MARK, VI4_DATA19_MARK,
4024 VI4_DATA20_MARK, VI4_DATA21_MARK,
4025 VI4_DATA22_MARK, VI4_DATA23_MARK,
4026};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4027static const unsigned int vin4_data_a_pins[] = {
4028 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4029 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4030 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4031 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4032 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4033 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4034 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4035 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4036 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4037 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4038 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4039 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4040};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4041static const unsigned int vin4_data_a_mux[] = {
4042 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4043 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4044 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4045 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4046 VI4_DATA8_MARK, VI4_DATA9_MARK,
4047 VI4_DATA10_MARK, VI4_DATA11_MARK,
4048 VI4_DATA12_MARK, VI4_DATA13_MARK,
4049 VI4_DATA14_MARK, VI4_DATA15_MARK,
4050 VI4_DATA16_MARK, VI4_DATA17_MARK,
4051 VI4_DATA18_MARK, VI4_DATA19_MARK,
4052 VI4_DATA20_MARK, VI4_DATA21_MARK,
4053 VI4_DATA22_MARK, VI4_DATA23_MARK,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4054};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4055static const unsigned int vin4_data_b_pins[] = {
4056 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4057 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4058 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4059 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4060 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4061 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4062 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4063 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4064 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4065 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4066 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4067 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4068};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4069static const unsigned int vin4_data_b_mux[] = {
4070 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4071 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4072 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4073 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4074 VI4_DATA8_MARK, VI4_DATA9_MARK,
4075 VI4_DATA10_MARK, VI4_DATA11_MARK,
4076 VI4_DATA12_MARK, VI4_DATA13_MARK,
4077 VI4_DATA14_MARK, VI4_DATA15_MARK,
4078 VI4_DATA16_MARK, VI4_DATA17_MARK,
4079 VI4_DATA18_MARK, VI4_DATA19_MARK,
4080 VI4_DATA20_MARK, VI4_DATA21_MARK,
4081 VI4_DATA22_MARK, VI4_DATA23_MARK,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4082};
4083static const unsigned int vin4_sync_pins[] = {
4084 /* HSYNC#, VSYNC# */
4085 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4086};
4087static const unsigned int vin4_sync_mux[] = {
4088 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4089};
4090static const unsigned int vin4_field_pins[] = {
4091 /* FIELD */
4092 RCAR_GP_PIN(1, 16),
4093};
4094static const unsigned int vin4_field_mux[] = {
4095 VI4_FIELD_MARK,
4096};
4097static const unsigned int vin4_clkenb_pins[] = {
4098 /* CLKENB */
4099 RCAR_GP_PIN(1, 19),
4100};
4101static const unsigned int vin4_clkenb_mux[] = {
4102 VI4_CLKENB_MARK,
4103};
4104static const unsigned int vin4_clk_pins[] = {
4105 /* CLK */
4106 RCAR_GP_PIN(1, 27),
4107};
4108static const unsigned int vin4_clk_mux[] = {
4109 VI4_CLK_MARK,
4110};
4111
4112/* - VIN5 ------------------------------------------------------------------- */
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4113static const unsigned int vin5_data_pins[] = {
4114 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4115 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4116 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4117 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4118 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4119 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4120 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4121 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4122};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4123static const unsigned int vin5_data_mux[] = {
4124 VI5_DATA0_MARK, VI5_DATA1_MARK,
4125 VI5_DATA2_MARK, VI5_DATA3_MARK,
4126 VI5_DATA4_MARK, VI5_DATA5_MARK,
4127 VI5_DATA6_MARK, VI5_DATA7_MARK,
4128 VI5_DATA8_MARK, VI5_DATA9_MARK,
4129 VI5_DATA10_MARK, VI5_DATA11_MARK,
4130 VI5_DATA12_MARK, VI5_DATA13_MARK,
4131 VI5_DATA14_MARK, VI5_DATA15_MARK,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4132};
4133static const unsigned int vin5_sync_pins[] = {
4134 /* HSYNC#, VSYNC# */
4135 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4136};
4137static const unsigned int vin5_sync_mux[] = {
4138 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4139};
4140static const unsigned int vin5_field_pins[] = {
4141 RCAR_GP_PIN(1, 11),
4142};
4143static const unsigned int vin5_field_mux[] = {
4144 /* FIELD */
4145 VI5_FIELD_MARK,
4146};
4147static const unsigned int vin5_clkenb_pins[] = {
4148 RCAR_GP_PIN(1, 20),
4149};
4150static const unsigned int vin5_clkenb_mux[] = {
4151 /* CLKENB */
4152 VI5_CLKENB_MARK,
4153};
4154static const unsigned int vin5_clk_pins[] = {
4155 RCAR_GP_PIN(1, 21),
4156};
4157static const unsigned int vin5_clk_mux[] = {
4158 /* CLK */
4159 VI5_CLK_MARK,
4160};
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4161#endif
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4162
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4163static const struct {
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4164 struct sh_pfc_pin_group common[328];
4165#ifdef CONFIG_PINCTRL_PFC_R8A77951
4166 struct sh_pfc_pin_group automotive[31];
Biju Dasd2288272020-10-28 10:34:25 +0000[diff] [blame]4167#endif
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4168} pinmux_groups = {
4169 .common = {
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4170#ifdef CONFIG_PINCTRL_PFC_FULL
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4171 SH_PFC_PIN_GROUP(audio_clk_a_a),
4172 SH_PFC_PIN_GROUP(audio_clk_a_b),
4173 SH_PFC_PIN_GROUP(audio_clk_a_c),
4174 SH_PFC_PIN_GROUP(audio_clk_b_a),
4175 SH_PFC_PIN_GROUP(audio_clk_b_b),
4176 SH_PFC_PIN_GROUP(audio_clk_c_a),
4177 SH_PFC_PIN_GROUP(audio_clk_c_b),
4178 SH_PFC_PIN_GROUP(audio_clkout_a),
4179 SH_PFC_PIN_GROUP(audio_clkout_b),
4180 SH_PFC_PIN_GROUP(audio_clkout_c),
4181 SH_PFC_PIN_GROUP(audio_clkout_d),
4182 SH_PFC_PIN_GROUP(audio_clkout1_a),
4183 SH_PFC_PIN_GROUP(audio_clkout1_b),
4184 SH_PFC_PIN_GROUP(audio_clkout2_a),
4185 SH_PFC_PIN_GROUP(audio_clkout2_b),
4186 SH_PFC_PIN_GROUP(audio_clkout3_a),
4187 SH_PFC_PIN_GROUP(audio_clkout3_b),
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4188#endif
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4189 SH_PFC_PIN_GROUP(avb_link),
4190 SH_PFC_PIN_GROUP(avb_magic),
4191 SH_PFC_PIN_GROUP(avb_phy_int),
4192 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4193 SH_PFC_PIN_GROUP(avb_mdio),
4194 SH_PFC_PIN_GROUP(avb_mii),
4195 SH_PFC_PIN_GROUP(avb_avtp_pps),
4196 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4197 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4198 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4199 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4200#ifdef CONFIG_PINCTRL_PFC_FULL
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4201 SH_PFC_PIN_GROUP(can0_data_a),
4202 SH_PFC_PIN_GROUP(can0_data_b),
4203 SH_PFC_PIN_GROUP(can1_data),
4204 SH_PFC_PIN_GROUP(can_clk),
4205 SH_PFC_PIN_GROUP(canfd0_data_a),
4206 SH_PFC_PIN_GROUP(canfd0_data_b),
4207 SH_PFC_PIN_GROUP(canfd1_data),
4208 SH_PFC_PIN_GROUP(du_rgb666),
4209 SH_PFC_PIN_GROUP(du_rgb888),
4210 SH_PFC_PIN_GROUP(du_clk_out_0),
4211 SH_PFC_PIN_GROUP(du_clk_out_1),
4212 SH_PFC_PIN_GROUP(du_sync),
4213 SH_PFC_PIN_GROUP(du_oddf),
4214 SH_PFC_PIN_GROUP(du_cde),
4215 SH_PFC_PIN_GROUP(du_disp),
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4216#endif
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4217 SH_PFC_PIN_GROUP(hscif0_data),
4218 SH_PFC_PIN_GROUP(hscif0_clk),
4219 SH_PFC_PIN_GROUP(hscif0_ctrl),
4220 SH_PFC_PIN_GROUP(hscif1_data_a),
4221 SH_PFC_PIN_GROUP(hscif1_clk_a),
4222 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4223 SH_PFC_PIN_GROUP(hscif1_data_b),
4224 SH_PFC_PIN_GROUP(hscif1_clk_b),
4225 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4226 SH_PFC_PIN_GROUP(hscif2_data_a),
4227 SH_PFC_PIN_GROUP(hscif2_clk_a),
4228 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4229 SH_PFC_PIN_GROUP(hscif2_data_b),
4230 SH_PFC_PIN_GROUP(hscif2_clk_b),
4231 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4232 SH_PFC_PIN_GROUP(hscif2_data_c),
4233 SH_PFC_PIN_GROUP(hscif2_clk_c),
4234 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4235 SH_PFC_PIN_GROUP(hscif3_data_a),
4236 SH_PFC_PIN_GROUP(hscif3_clk),
4237 SH_PFC_PIN_GROUP(hscif3_ctrl),
4238 SH_PFC_PIN_GROUP(hscif3_data_b),
4239 SH_PFC_PIN_GROUP(hscif3_data_c),
4240 SH_PFC_PIN_GROUP(hscif3_data_d),
4241 SH_PFC_PIN_GROUP(hscif4_data_a),
4242 SH_PFC_PIN_GROUP(hscif4_clk),
4243 SH_PFC_PIN_GROUP(hscif4_ctrl),
4244 SH_PFC_PIN_GROUP(hscif4_data_b),
4245 SH_PFC_PIN_GROUP(i2c0),
4246 SH_PFC_PIN_GROUP(i2c1_a),
4247 SH_PFC_PIN_GROUP(i2c1_b),
4248 SH_PFC_PIN_GROUP(i2c2_a),
4249 SH_PFC_PIN_GROUP(i2c2_b),
4250 SH_PFC_PIN_GROUP(i2c3),
4251 SH_PFC_PIN_GROUP(i2c5),
4252 SH_PFC_PIN_GROUP(i2c6_a),
4253 SH_PFC_PIN_GROUP(i2c6_b),
4254 SH_PFC_PIN_GROUP(i2c6_c),
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4255#ifdef CONFIG_PINCTRL_PFC_FULL
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4256 SH_PFC_PIN_GROUP(intc_ex_irq0),
4257 SH_PFC_PIN_GROUP(intc_ex_irq1),
4258 SH_PFC_PIN_GROUP(intc_ex_irq2),
4259 SH_PFC_PIN_GROUP(intc_ex_irq3),
4260 SH_PFC_PIN_GROUP(intc_ex_irq4),
4261 SH_PFC_PIN_GROUP(intc_ex_irq5),
4262 SH_PFC_PIN_GROUP(msiof0_clk),
4263 SH_PFC_PIN_GROUP(msiof0_sync),
4264 SH_PFC_PIN_GROUP(msiof0_ss1),
4265 SH_PFC_PIN_GROUP(msiof0_ss2),
4266 SH_PFC_PIN_GROUP(msiof0_txd),
4267 SH_PFC_PIN_GROUP(msiof0_rxd),
4268 SH_PFC_PIN_GROUP(msiof1_clk_a),
4269 SH_PFC_PIN_GROUP(msiof1_sync_a),
4270 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4271 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4272 SH_PFC_PIN_GROUP(msiof1_txd_a),
4273 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4274 SH_PFC_PIN_GROUP(msiof1_clk_b),
4275 SH_PFC_PIN_GROUP(msiof1_sync_b),
4276 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4277 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4278 SH_PFC_PIN_GROUP(msiof1_txd_b),
4279 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4280 SH_PFC_PIN_GROUP(msiof1_clk_c),
4281 SH_PFC_PIN_GROUP(msiof1_sync_c),
4282 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4283 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4284 SH_PFC_PIN_GROUP(msiof1_txd_c),
4285 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4286 SH_PFC_PIN_GROUP(msiof1_clk_d),
4287 SH_PFC_PIN_GROUP(msiof1_sync_d),
4288 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4289 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4290 SH_PFC_PIN_GROUP(msiof1_txd_d),
4291 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4292 SH_PFC_PIN_GROUP(msiof1_clk_e),
4293 SH_PFC_PIN_GROUP(msiof1_sync_e),
4294 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4295 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4296 SH_PFC_PIN_GROUP(msiof1_txd_e),
4297 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4298 SH_PFC_PIN_GROUP(msiof1_clk_f),
4299 SH_PFC_PIN_GROUP(msiof1_sync_f),
4300 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4301 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4302 SH_PFC_PIN_GROUP(msiof1_txd_f),
4303 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4304 SH_PFC_PIN_GROUP(msiof1_clk_g),
4305 SH_PFC_PIN_GROUP(msiof1_sync_g),
4306 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4307 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4308 SH_PFC_PIN_GROUP(msiof1_txd_g),
4309 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4310 SH_PFC_PIN_GROUP(msiof2_clk_a),
4311 SH_PFC_PIN_GROUP(msiof2_sync_a),
4312 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4313 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4314 SH_PFC_PIN_GROUP(msiof2_txd_a),
4315 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4316 SH_PFC_PIN_GROUP(msiof2_clk_b),
4317 SH_PFC_PIN_GROUP(msiof2_sync_b),
4318 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4319 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4320 SH_PFC_PIN_GROUP(msiof2_txd_b),
4321 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4322 SH_PFC_PIN_GROUP(msiof2_clk_c),
4323 SH_PFC_PIN_GROUP(msiof2_sync_c),
4324 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4325 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4326 SH_PFC_PIN_GROUP(msiof2_txd_c),
4327 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4328 SH_PFC_PIN_GROUP(msiof2_clk_d),
4329 SH_PFC_PIN_GROUP(msiof2_sync_d),
4330 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4331 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4332 SH_PFC_PIN_GROUP(msiof2_txd_d),
4333 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4334 SH_PFC_PIN_GROUP(msiof3_clk_a),
4335 SH_PFC_PIN_GROUP(msiof3_sync_a),
4336 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4337 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4338 SH_PFC_PIN_GROUP(msiof3_txd_a),
4339 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4340 SH_PFC_PIN_GROUP(msiof3_clk_b),
4341 SH_PFC_PIN_GROUP(msiof3_sync_b),
4342 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4343 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4344 SH_PFC_PIN_GROUP(msiof3_txd_b),
4345 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4346 SH_PFC_PIN_GROUP(msiof3_clk_c),
4347 SH_PFC_PIN_GROUP(msiof3_sync_c),
4348 SH_PFC_PIN_GROUP(msiof3_txd_c),
4349 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4350 SH_PFC_PIN_GROUP(msiof3_clk_d),
4351 SH_PFC_PIN_GROUP(msiof3_sync_d),
4352 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4353 SH_PFC_PIN_GROUP(msiof3_txd_d),
4354 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4355 SH_PFC_PIN_GROUP(msiof3_clk_e),
4356 SH_PFC_PIN_GROUP(msiof3_sync_e),
4357 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4358 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4359 SH_PFC_PIN_GROUP(msiof3_txd_e),
4360 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4361 SH_PFC_PIN_GROUP(pwm0),
4362 SH_PFC_PIN_GROUP(pwm1_a),
4363 SH_PFC_PIN_GROUP(pwm1_b),
4364 SH_PFC_PIN_GROUP(pwm2_a),
4365 SH_PFC_PIN_GROUP(pwm2_b),
4366 SH_PFC_PIN_GROUP(pwm3_a),
4367 SH_PFC_PIN_GROUP(pwm3_b),
4368 SH_PFC_PIN_GROUP(pwm4_a),
4369 SH_PFC_PIN_GROUP(pwm4_b),
4370 SH_PFC_PIN_GROUP(pwm5_a),
4371 SH_PFC_PIN_GROUP(pwm5_b),
4372 SH_PFC_PIN_GROUP(pwm6_a),
4373 SH_PFC_PIN_GROUP(pwm6_b),
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4374#endif
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4375 SH_PFC_PIN_GROUP(qspi0_ctrl),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4376 BUS_DATA_PIN_GROUP(qspi0_data, 2),
4377 BUS_DATA_PIN_GROUP(qspi0_data, 4),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4378 SH_PFC_PIN_GROUP(qspi1_ctrl),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4379 BUS_DATA_PIN_GROUP(qspi1_data, 2),
4380 BUS_DATA_PIN_GROUP(qspi1_data, 4),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4381 SH_PFC_PIN_GROUP(sata0_devslp_a),
4382 SH_PFC_PIN_GROUP(sata0_devslp_b),
4383 SH_PFC_PIN_GROUP(scif0_data),
4384 SH_PFC_PIN_GROUP(scif0_clk),
4385 SH_PFC_PIN_GROUP(scif0_ctrl),
4386 SH_PFC_PIN_GROUP(scif1_data_a),
4387 SH_PFC_PIN_GROUP(scif1_clk),
4388 SH_PFC_PIN_GROUP(scif1_ctrl),
4389 SH_PFC_PIN_GROUP(scif1_data_b),
4390 SH_PFC_PIN_GROUP(scif2_data_a),
4391 SH_PFC_PIN_GROUP(scif2_clk),
4392 SH_PFC_PIN_GROUP(scif2_data_b),
4393 SH_PFC_PIN_GROUP(scif3_data_a),
4394 SH_PFC_PIN_GROUP(scif3_clk),
4395 SH_PFC_PIN_GROUP(scif3_ctrl),
4396 SH_PFC_PIN_GROUP(scif3_data_b),
4397 SH_PFC_PIN_GROUP(scif4_data_a),
4398 SH_PFC_PIN_GROUP(scif4_clk_a),
4399 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4400 SH_PFC_PIN_GROUP(scif4_data_b),
4401 SH_PFC_PIN_GROUP(scif4_clk_b),
4402 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4403 SH_PFC_PIN_GROUP(scif4_data_c),
4404 SH_PFC_PIN_GROUP(scif4_clk_c),
4405 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4406 SH_PFC_PIN_GROUP(scif5_data_a),
4407 SH_PFC_PIN_GROUP(scif5_clk_a),
4408 SH_PFC_PIN_GROUP(scif5_data_b),
4409 SH_PFC_PIN_GROUP(scif5_clk_b),
4410 SH_PFC_PIN_GROUP(scif_clk_a),
4411 SH_PFC_PIN_GROUP(scif_clk_b),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4412 BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4413 BUS_DATA_PIN_GROUP(sdhi0_data, 4),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4414 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4415 SH_PFC_PIN_GROUP(sdhi0_cd),
4416 SH_PFC_PIN_GROUP(sdhi0_wp),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4417 BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4418 BUS_DATA_PIN_GROUP(sdhi1_data, 4),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4419 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4420 SH_PFC_PIN_GROUP(sdhi1_cd),
4421 SH_PFC_PIN_GROUP(sdhi1_wp),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4422 BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4423 BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4424 BUS_DATA_PIN_GROUP(sdhi2_data, 8),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4425 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4426 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4427 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4428 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4429 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4430 SH_PFC_PIN_GROUP(sdhi2_ds),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4431 BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4432 BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4433 BUS_DATA_PIN_GROUP(sdhi3_data, 8),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4434 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4435 SH_PFC_PIN_GROUP(sdhi3_cd),
4436 SH_PFC_PIN_GROUP(sdhi3_wp),
4437 SH_PFC_PIN_GROUP(sdhi3_ds),
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4438#ifdef CONFIG_PINCTRL_PFC_FULL
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4439 SH_PFC_PIN_GROUP(ssi0_data),
4440 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4441 SH_PFC_PIN_GROUP(ssi1_data_a),
4442 SH_PFC_PIN_GROUP(ssi1_data_b),
4443 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4444 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4445 SH_PFC_PIN_GROUP(ssi2_data_a),
4446 SH_PFC_PIN_GROUP(ssi2_data_b),
4447 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4448 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4449 SH_PFC_PIN_GROUP(ssi3_data),
4450 SH_PFC_PIN_GROUP(ssi349_ctrl),
4451 SH_PFC_PIN_GROUP(ssi4_data),
4452 SH_PFC_PIN_GROUP(ssi4_ctrl),
4453 SH_PFC_PIN_GROUP(ssi5_data),
4454 SH_PFC_PIN_GROUP(ssi5_ctrl),
4455 SH_PFC_PIN_GROUP(ssi6_data),
4456 SH_PFC_PIN_GROUP(ssi6_ctrl),
4457 SH_PFC_PIN_GROUP(ssi7_data),
4458 SH_PFC_PIN_GROUP(ssi78_ctrl),
4459 SH_PFC_PIN_GROUP(ssi8_data),
4460 SH_PFC_PIN_GROUP(ssi9_data_a),
4461 SH_PFC_PIN_GROUP(ssi9_data_b),
4462 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4463 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4464#endif
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4465 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4466 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4467 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4468 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4469 SH_PFC_PIN_GROUP(tpu_to0),
4470 SH_PFC_PIN_GROUP(tpu_to1),
4471 SH_PFC_PIN_GROUP(tpu_to2),
4472 SH_PFC_PIN_GROUP(tpu_to3),
4473 SH_PFC_PIN_GROUP(usb0),
4474 SH_PFC_PIN_GROUP(usb1),
4475 SH_PFC_PIN_GROUP(usb2),
4476 SH_PFC_PIN_GROUP(usb2_ch3),
4477 SH_PFC_PIN_GROUP(usb30),
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4478#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4479 BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4480 BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4481 BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4482 BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4483 SH_PFC_PIN_GROUP(vin4_data18_a),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4484 BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4485 BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4486 BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4487 BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4488 BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4489 BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4490 SH_PFC_PIN_GROUP(vin4_data18_b),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4491 BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4492 BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4493 SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4494 SH_PFC_PIN_GROUP(vin4_sync),
4495 SH_PFC_PIN_GROUP(vin4_field),
4496 SH_PFC_PIN_GROUP(vin4_clkenb),
4497 SH_PFC_PIN_GROUP(vin4_clk),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4498 BUS_DATA_PIN_GROUP(vin5_data, 8),
4499 BUS_DATA_PIN_GROUP(vin5_data, 10),
4500 BUS_DATA_PIN_GROUP(vin5_data, 12),
4501 BUS_DATA_PIN_GROUP(vin5_data, 16),
4502 SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4503 SH_PFC_PIN_GROUP(vin5_sync),
4504 SH_PFC_PIN_GROUP(vin5_field),
4505 SH_PFC_PIN_GROUP(vin5_clkenb),
4506 SH_PFC_PIN_GROUP(vin5_clk),
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4507#endif
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4508 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4509#ifdef CONFIG_PINCTRL_PFC_R8A77951
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4510 .automotive = {
4511 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4512 SH_PFC_PIN_GROUP(drif0_data0_a),
4513 SH_PFC_PIN_GROUP(drif0_data1_a),
4514 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4515 SH_PFC_PIN_GROUP(drif0_data0_b),
4516 SH_PFC_PIN_GROUP(drif0_data1_b),
4517 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4518 SH_PFC_PIN_GROUP(drif0_data0_c),
4519 SH_PFC_PIN_GROUP(drif0_data1_c),
4520 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4521 SH_PFC_PIN_GROUP(drif1_data0_a),
4522 SH_PFC_PIN_GROUP(drif1_data1_a),
4523 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4524 SH_PFC_PIN_GROUP(drif1_data0_b),
4525 SH_PFC_PIN_GROUP(drif1_data1_b),
4526 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4527 SH_PFC_PIN_GROUP(drif1_data0_c),
4528 SH_PFC_PIN_GROUP(drif1_data1_c),
4529 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4530 SH_PFC_PIN_GROUP(drif2_data0_a),
4531 SH_PFC_PIN_GROUP(drif2_data1_a),
4532 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4533 SH_PFC_PIN_GROUP(drif2_data0_b),
4534 SH_PFC_PIN_GROUP(drif2_data1_b),
4535 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4536 SH_PFC_PIN_GROUP(drif3_data0_a),
4537 SH_PFC_PIN_GROUP(drif3_data1_a),
4538 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4539 SH_PFC_PIN_GROUP(drif3_data0_b),
4540 SH_PFC_PIN_GROUP(drif3_data1_b),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4541 SH_PFC_PIN_GROUP(mlb_3pin),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4542 }
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4543#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4544};
4545
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4546#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4547static const char * const audio_clk_groups[] = {
4548 "audio_clk_a_a",
4549 "audio_clk_a_b",
4550 "audio_clk_a_c",
4551 "audio_clk_b_a",
4552 "audio_clk_b_b",
4553 "audio_clk_c_a",
4554 "audio_clk_c_b",
4555 "audio_clkout_a",
4556 "audio_clkout_b",
4557 "audio_clkout_c",
4558 "audio_clkout_d",
4559 "audio_clkout1_a",
4560 "audio_clkout1_b",
4561 "audio_clkout2_a",
4562 "audio_clkout2_b",
4563 "audio_clkout3_a",
4564 "audio_clkout3_b",
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4565};
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4566#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4567
4568static const char * const avb_groups[] = {
4569 "avb_link",
4570 "avb_magic",
4571 "avb_phy_int",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4572 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4573 "avb_mdio",
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4574 "avb_mii",
4575 "avb_avtp_pps",
4576 "avb_avtp_match_a",
4577 "avb_avtp_capture_a",
4578 "avb_avtp_match_b",
4579 "avb_avtp_capture_b",
4580};
4581
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4582#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4583static const char * const can0_groups[] = {
4584 "can0_data_a",
4585 "can0_data_b",
4586};
4587
4588static const char * const can1_groups[] = {
4589 "can1_data",
4590};
4591
4592static const char * const can_clk_groups[] = {
4593 "can_clk",
4594};
4595
4596static const char * const canfd0_groups[] = {
4597 "canfd0_data_a",
4598 "canfd0_data_b",
4599};
4600
4601static const char * const canfd1_groups[] = {
4602 "canfd1_data",
4603};
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4604#endif
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4605
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4606#ifdef CONFIG_PINCTRL_PFC_R8A77951
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4607static const char * const drif0_groups[] = {
4608 "drif0_ctrl_a",
4609 "drif0_data0_a",
4610 "drif0_data1_a",
4611 "drif0_ctrl_b",
4612 "drif0_data0_b",
4613 "drif0_data1_b",
4614 "drif0_ctrl_c",
4615 "drif0_data0_c",
4616 "drif0_data1_c",
4617};
4618
4619static const char * const drif1_groups[] = {
4620 "drif1_ctrl_a",
4621 "drif1_data0_a",
4622 "drif1_data1_a",
4623 "drif1_ctrl_b",
4624 "drif1_data0_b",
4625 "drif1_data1_b",
4626 "drif1_ctrl_c",
4627 "drif1_data0_c",
4628 "drif1_data1_c",
4629};
4630
4631static const char * const drif2_groups[] = {
4632 "drif2_ctrl_a",
4633 "drif2_data0_a",
4634 "drif2_data1_a",
4635 "drif2_ctrl_b",
4636 "drif2_data0_b",
4637 "drif2_data1_b",
4638};
4639
4640static const char * const drif3_groups[] = {
4641 "drif3_ctrl_a",
4642 "drif3_data0_a",
4643 "drif3_data1_a",
4644 "drif3_ctrl_b",
4645 "drif3_data0_b",
4646 "drif3_data1_b",
4647};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4648#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4649
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4650#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4651static const char * const du_groups[] = {
4652 "du_rgb666",
4653 "du_rgb888",
4654 "du_clk_out_0",
4655 "du_clk_out_1",
4656 "du_sync",
4657 "du_oddf",
4658 "du_cde",
4659 "du_disp",
4660};
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4661#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4662
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4663static const char * const hscif0_groups[] = {
4664 "hscif0_data",
4665 "hscif0_clk",
4666 "hscif0_ctrl",
4667};
4668
4669static const char * const hscif1_groups[] = {
4670 "hscif1_data_a",
4671 "hscif1_clk_a",
4672 "hscif1_ctrl_a",
4673 "hscif1_data_b",
4674 "hscif1_clk_b",
4675 "hscif1_ctrl_b",
4676};
4677
4678static const char * const hscif2_groups[] = {
4679 "hscif2_data_a",
4680 "hscif2_clk_a",
4681 "hscif2_ctrl_a",
4682 "hscif2_data_b",
4683 "hscif2_clk_b",
4684 "hscif2_ctrl_b",
4685 "hscif2_data_c",
4686 "hscif2_clk_c",
4687 "hscif2_ctrl_c",
4688};
4689
4690static const char * const hscif3_groups[] = {
4691 "hscif3_data_a",
4692 "hscif3_clk",
4693 "hscif3_ctrl",
4694 "hscif3_data_b",
4695 "hscif3_data_c",
4696 "hscif3_data_d",
4697};
4698
4699static const char * const hscif4_groups[] = {
4700 "hscif4_data_a",
4701 "hscif4_clk",
4702 "hscif4_ctrl",
4703 "hscif4_data_b",
4704};
4705
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4706static const char * const i2c0_groups[] = {
4707 "i2c0",
4708};
4709
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4710static const char * const i2c1_groups[] = {
4711 "i2c1_a",
4712 "i2c1_b",
4713};
4714
4715static const char * const i2c2_groups[] = {
4716 "i2c2_a",
4717 "i2c2_b",
4718};
4719
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4720static const char * const i2c3_groups[] = {
4721 "i2c3",
4722};
4723
4724static const char * const i2c5_groups[] = {
4725 "i2c5",
4726};
4727
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4728static const char * const i2c6_groups[] = {
4729 "i2c6_a",
4730 "i2c6_b",
4731 "i2c6_c",
4732};
4733
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4734#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4735static const char * const intc_ex_groups[] = {
4736 "intc_ex_irq0",
4737 "intc_ex_irq1",
4738 "intc_ex_irq2",
4739 "intc_ex_irq3",
4740 "intc_ex_irq4",
4741 "intc_ex_irq5",
4742};
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4743#endif
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4744
4745#ifdef CONFIG_PINCTRL_PFC_R8A77951
4746static const char * const mlb_3pin_groups[] = {
4747 "mlb_3pin",
4748};
4749#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4750
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4751#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4752static const char * const msiof0_groups[] = {
4753 "msiof0_clk",
4754 "msiof0_sync",
4755 "msiof0_ss1",
4756 "msiof0_ss2",
4757 "msiof0_txd",
4758 "msiof0_rxd",
4759};
4760
4761static const char * const msiof1_groups[] = {
4762 "msiof1_clk_a",
4763 "msiof1_sync_a",
4764 "msiof1_ss1_a",
4765 "msiof1_ss2_a",
4766 "msiof1_txd_a",
4767 "msiof1_rxd_a",
4768 "msiof1_clk_b",
4769 "msiof1_sync_b",
4770 "msiof1_ss1_b",
4771 "msiof1_ss2_b",
4772 "msiof1_txd_b",
4773 "msiof1_rxd_b",
4774 "msiof1_clk_c",
4775 "msiof1_sync_c",
4776 "msiof1_ss1_c",
4777 "msiof1_ss2_c",
4778 "msiof1_txd_c",
4779 "msiof1_rxd_c",
4780 "msiof1_clk_d",
4781 "msiof1_sync_d",
4782 "msiof1_ss1_d",
4783 "msiof1_ss2_d",
4784 "msiof1_txd_d",
4785 "msiof1_rxd_d",
4786 "msiof1_clk_e",
4787 "msiof1_sync_e",
4788 "msiof1_ss1_e",
4789 "msiof1_ss2_e",
4790 "msiof1_txd_e",
4791 "msiof1_rxd_e",
4792 "msiof1_clk_f",
4793 "msiof1_sync_f",
4794 "msiof1_ss1_f",
4795 "msiof1_ss2_f",
4796 "msiof1_txd_f",
4797 "msiof1_rxd_f",
4798 "msiof1_clk_g",
4799 "msiof1_sync_g",
4800 "msiof1_ss1_g",
4801 "msiof1_ss2_g",
4802 "msiof1_txd_g",
4803 "msiof1_rxd_g",
4804};
4805
4806static const char * const msiof2_groups[] = {
4807 "msiof2_clk_a",
4808 "msiof2_sync_a",
4809 "msiof2_ss1_a",
4810 "msiof2_ss2_a",
4811 "msiof2_txd_a",
4812 "msiof2_rxd_a",
4813 "msiof2_clk_b",
4814 "msiof2_sync_b",
4815 "msiof2_ss1_b",
4816 "msiof2_ss2_b",
4817 "msiof2_txd_b",
4818 "msiof2_rxd_b",
4819 "msiof2_clk_c",
4820 "msiof2_sync_c",
4821 "msiof2_ss1_c",
4822 "msiof2_ss2_c",
4823 "msiof2_txd_c",
4824 "msiof2_rxd_c",
4825 "msiof2_clk_d",
4826 "msiof2_sync_d",
4827 "msiof2_ss1_d",
4828 "msiof2_ss2_d",
4829 "msiof2_txd_d",
4830 "msiof2_rxd_d",
4831};
4832
4833static const char * const msiof3_groups[] = {
4834 "msiof3_clk_a",
4835 "msiof3_sync_a",
4836 "msiof3_ss1_a",
4837 "msiof3_ss2_a",
4838 "msiof3_txd_a",
4839 "msiof3_rxd_a",
4840 "msiof3_clk_b",
4841 "msiof3_sync_b",
4842 "msiof3_ss1_b",
4843 "msiof3_ss2_b",
4844 "msiof3_txd_b",
4845 "msiof3_rxd_b",
4846 "msiof3_clk_c",
4847 "msiof3_sync_c",
4848 "msiof3_txd_c",
4849 "msiof3_rxd_c",
4850 "msiof3_clk_d",
4851 "msiof3_sync_d",
4852 "msiof3_ss1_d",
4853 "msiof3_txd_d",
4854 "msiof3_rxd_d",
4855 "msiof3_clk_e",
4856 "msiof3_sync_e",
4857 "msiof3_ss1_e",
4858 "msiof3_ss2_e",
4859 "msiof3_txd_e",
4860 "msiof3_rxd_e",
4861};
4862
4863static const char * const pwm0_groups[] = {
4864 "pwm0",
4865};
4866
4867static const char * const pwm1_groups[] = {
4868 "pwm1_a",
4869 "pwm1_b",
4870};
4871
4872static const char * const pwm2_groups[] = {
4873 "pwm2_a",
4874 "pwm2_b",
4875};
4876
4877static const char * const pwm3_groups[] = {
4878 "pwm3_a",
4879 "pwm3_b",
4880};
4881
4882static const char * const pwm4_groups[] = {
4883 "pwm4_a",
4884 "pwm4_b",
4885};
4886
4887static const char * const pwm5_groups[] = {
4888 "pwm5_a",
4889 "pwm5_b",
4890};
4891
4892static const char * const pwm6_groups[] = {
4893 "pwm6_a",
4894 "pwm6_b",
4895};
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]4896#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4897
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4898static const char * const qspi0_groups[] = {
4899 "qspi0_ctrl",
4900 "qspi0_data2",
4901 "qspi0_data4",
4902};
4903
4904static const char * const qspi1_groups[] = {
4905 "qspi1_ctrl",
4906 "qspi1_data2",
4907 "qspi1_data4",
4908};
4909
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4910static const char * const sata0_groups[] = {
4911 "sata0_devslp_a",
4912 "sata0_devslp_b",
4913};
4914
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4915static const char * const scif0_groups[] = {
4916 "scif0_data",
4917 "scif0_clk",
4918 "scif0_ctrl",
4919};
4920
4921static const char * const scif1_groups[] = {
4922 "scif1_data_a",
4923 "scif1_clk",
4924 "scif1_ctrl",
4925 "scif1_data_b",
4926};
4927
4928static const char * const scif2_groups[] = {
4929 "scif2_data_a",
4930 "scif2_clk",
4931 "scif2_data_b",
4932};
4933
4934static const char * const scif3_groups[] = {
4935 "scif3_data_a",
4936 "scif3_clk",
4937 "scif3_ctrl",
4938 "scif3_data_b",
4939};
4940
4941static const char * const scif4_groups[] = {
4942 "scif4_data_a",
4943 "scif4_clk_a",
4944 "scif4_ctrl_a",
4945 "scif4_data_b",
4946 "scif4_clk_b",
4947 "scif4_ctrl_b",
4948 "scif4_data_c",
4949 "scif4_clk_c",
4950 "scif4_ctrl_c",
4951};
4952
4953static const char * const scif5_groups[] = {
4954 "scif5_data_a",
4955 "scif5_clk_a",
4956 "scif5_data_b",
4957 "scif5_clk_b",
4958};
4959
4960static const char * const scif_clk_groups[] = {
4961 "scif_clk_a",
4962 "scif_clk_b",
4963};
4964
4965static const char * const sdhi0_groups[] = {
4966 "sdhi0_data1",
4967 "sdhi0_data4",
4968 "sdhi0_ctrl",
4969 "sdhi0_cd",
4970 "sdhi0_wp",
4971};
4972
4973static const char * const sdhi1_groups[] = {
4974 "sdhi1_data1",
4975 "sdhi1_data4",
4976 "sdhi1_ctrl",
4977 "sdhi1_cd",
4978 "sdhi1_wp",
4979};
4980
4981static const char * const sdhi2_groups[] = {
4982 "sdhi2_data1",
4983 "sdhi2_data4",
4984 "sdhi2_data8",
4985 "sdhi2_ctrl",
4986 "sdhi2_cd_a",
4987 "sdhi2_wp_a",
4988 "sdhi2_cd_b",
4989 "sdhi2_wp_b",
4990 "sdhi2_ds",
4991};
4992
4993static const char * const sdhi3_groups[] = {
4994 "sdhi3_data1",
4995 "sdhi3_data4",
4996 "sdhi3_data8",
4997 "sdhi3_ctrl",
4998 "sdhi3_cd",
4999 "sdhi3_wp",
5000 "sdhi3_ds",
5001};
5002
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]5003#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5004static const char * const ssi_groups[] = {
5005 "ssi0_data",
5006 "ssi01239_ctrl",
5007 "ssi1_data_a",
5008 "ssi1_data_b",
5009 "ssi1_ctrl_a",
5010 "ssi1_ctrl_b",
5011 "ssi2_data_a",
5012 "ssi2_data_b",
5013 "ssi2_ctrl_a",
5014 "ssi2_ctrl_b",
5015 "ssi3_data",
5016 "ssi349_ctrl",
5017 "ssi4_data",
5018 "ssi4_ctrl",
5019 "ssi5_data",
5020 "ssi5_ctrl",
5021 "ssi6_data",
5022 "ssi6_ctrl",
5023 "ssi7_data",
5024 "ssi78_ctrl",
5025 "ssi8_data",
5026 "ssi9_data_a",
5027 "ssi9_data_b",
5028 "ssi9_ctrl_a",
5029 "ssi9_ctrl_b",
5030};
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]5031#endif
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5032
5033static const char * const tmu_groups[] = {
5034 "tmu_tclk1_a",
5035 "tmu_tclk1_b",
5036 "tmu_tclk2_a",
5037 "tmu_tclk2_b",
5038};
5039
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5040static const char * const tpu_groups[] = {
5041 "tpu_to0",
5042 "tpu_to1",
5043 "tpu_to2",
5044 "tpu_to3",
5045};
5046
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5047static const char * const usb0_groups[] = {
5048 "usb0",
5049};
5050
5051static const char * const usb1_groups[] = {
5052 "usb1",
5053};
5054
5055static const char * const usb2_groups[] = {
5056 "usb2",
5057};
5058
5059static const char * const usb2_ch3_groups[] = {
5060 "usb2_ch3",
5061};
5062
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5063static const char * const usb30_groups[] = {
5064 "usb30",
5065};
5066
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]5067#ifdef CONFIG_PINCTRL_PFC_FULL
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5068static const char * const vin4_groups[] = {
5069 "vin4_data8_a",
5070 "vin4_data10_a",
5071 "vin4_data12_a",
5072 "vin4_data16_a",
5073 "vin4_data18_a",
5074 "vin4_data20_a",
5075 "vin4_data24_a",
5076 "vin4_data8_b",
5077 "vin4_data10_b",
5078 "vin4_data12_b",
5079 "vin4_data16_b",
5080 "vin4_data18_b",
5081 "vin4_data20_b",
5082 "vin4_data24_b",
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5083 "vin4_g8",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5084 "vin4_sync",
5085 "vin4_field",
5086 "vin4_clkenb",
5087 "vin4_clk",
5088};
5089
5090static const char * const vin5_groups[] = {
5091 "vin5_data8",
5092 "vin5_data10",
5093 "vin5_data12",
5094 "vin5_data16",
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5095 "vin5_high8",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5096 "vin5_sync",
5097 "vin5_field",
5098 "vin5_clkenb",
5099 "vin5_clk",
5100};
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]5101#endif
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5102
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5103static const struct {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5104 struct sh_pfc_function common[55];
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5105#ifdef CONFIG_PINCTRL_PFC_R8A77951
5106 struct sh_pfc_function automotive[5];
Biju Dasd2288272020-10-28 10:34:25 +0000[diff] [blame]5107#endif
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5108} pinmux_functions = {
5109 .common = {
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]5110#ifdef CONFIG_PINCTRL_PFC_FULL
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5111 SH_PFC_FUNCTION(audio_clk),
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]5112#endif
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5113 SH_PFC_FUNCTION(avb),
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]5114#ifdef CONFIG_PINCTRL_PFC_FULL
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5115 SH_PFC_FUNCTION(can0),
5116 SH_PFC_FUNCTION(can1),
5117 SH_PFC_FUNCTION(can_clk),
5118 SH_PFC_FUNCTION(canfd0),
5119 SH_PFC_FUNCTION(canfd1),
5120 SH_PFC_FUNCTION(du),
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]5121#endif
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5122 SH_PFC_FUNCTION(hscif0),
5123 SH_PFC_FUNCTION(hscif1),
5124 SH_PFC_FUNCTION(hscif2),
5125 SH_PFC_FUNCTION(hscif3),
5126 SH_PFC_FUNCTION(hscif4),
5127 SH_PFC_FUNCTION(i2c0),
5128 SH_PFC_FUNCTION(i2c1),
5129 SH_PFC_FUNCTION(i2c2),
5130 SH_PFC_FUNCTION(i2c3),
5131 SH_PFC_FUNCTION(i2c5),
5132 SH_PFC_FUNCTION(i2c6),
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]5133#ifdef CONFIG_PINCTRL_PFC_FULL
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5134 SH_PFC_FUNCTION(intc_ex),
5135 SH_PFC_FUNCTION(msiof0),
5136 SH_PFC_FUNCTION(msiof1),
5137 SH_PFC_FUNCTION(msiof2),
5138 SH_PFC_FUNCTION(msiof3),
5139 SH_PFC_FUNCTION(pwm0),
5140 SH_PFC_FUNCTION(pwm1),
5141 SH_PFC_FUNCTION(pwm2),
5142 SH_PFC_FUNCTION(pwm3),
5143 SH_PFC_FUNCTION(pwm4),
5144 SH_PFC_FUNCTION(pwm5),
5145 SH_PFC_FUNCTION(pwm6),
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]5146#endif
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5147 SH_PFC_FUNCTION(qspi0),
5148 SH_PFC_FUNCTION(qspi1),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5149 SH_PFC_FUNCTION(sata0),
5150 SH_PFC_FUNCTION(scif0),
5151 SH_PFC_FUNCTION(scif1),
5152 SH_PFC_FUNCTION(scif2),
5153 SH_PFC_FUNCTION(scif3),
5154 SH_PFC_FUNCTION(scif4),
5155 SH_PFC_FUNCTION(scif5),
5156 SH_PFC_FUNCTION(scif_clk),
5157 SH_PFC_FUNCTION(sdhi0),
5158 SH_PFC_FUNCTION(sdhi1),
5159 SH_PFC_FUNCTION(sdhi2),
5160 SH_PFC_FUNCTION(sdhi3),
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]5161#ifdef CONFIG_PINCTRL_PFC_FULL
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5162 SH_PFC_FUNCTION(ssi),
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]5163#endif
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5164 SH_PFC_FUNCTION(tmu),
5165 SH_PFC_FUNCTION(tpu),
5166 SH_PFC_FUNCTION(usb0),
5167 SH_PFC_FUNCTION(usb1),
5168 SH_PFC_FUNCTION(usb2),
5169 SH_PFC_FUNCTION(usb2_ch3),
5170 SH_PFC_FUNCTION(usb30),
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]5171#ifdef CONFIG_PINCTRL_PFC_FULL
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5172 SH_PFC_FUNCTION(vin4),
5173 SH_PFC_FUNCTION(vin5),
Marek Vasuteb713112024-12-23 14:34:10 +0100[diff] [blame^]5174#endif
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5175 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5176#ifdef CONFIG_PINCTRL_PFC_R8A77951
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5177 .automotive = {
5178 SH_PFC_FUNCTION(drif0),
5179 SH_PFC_FUNCTION(drif1),
5180 SH_PFC_FUNCTION(drif2),
5181 SH_PFC_FUNCTION(drif3),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5182 SH_PFC_FUNCTION(mlb_3pin),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5183 }
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5184#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5185};
5186
5187static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5188#define F_(x, y) FN_##y
5189#define FM(x) FN_##x
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5190 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
5191 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5192 1, 1, 1, 1, 1),
5193 GROUP(
5194 /* GP0_31_16 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5195 GP_0_15_FN, GPSR0_15,
5196 GP_0_14_FN, GPSR0_14,
5197 GP_0_13_FN, GPSR0_13,
5198 GP_0_12_FN, GPSR0_12,
5199 GP_0_11_FN, GPSR0_11,
5200 GP_0_10_FN, GPSR0_10,
5201 GP_0_9_FN, GPSR0_9,
5202 GP_0_8_FN, GPSR0_8,
5203 GP_0_7_FN, GPSR0_7,
5204 GP_0_6_FN, GPSR0_6,
5205 GP_0_5_FN, GPSR0_5,
5206 GP_0_4_FN, GPSR0_4,
5207 GP_0_3_FN, GPSR0_3,
5208 GP_0_2_FN, GPSR0_2,
5209 GP_0_1_FN, GPSR0_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5210 GP_0_0_FN, GPSR0_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5211 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5212 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5213 0, 0,
5214 0, 0,
5215 0, 0,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5216 GP_1_28_FN, GPSR1_28,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5217 GP_1_27_FN, GPSR1_27,
5218 GP_1_26_FN, GPSR1_26,
5219 GP_1_25_FN, GPSR1_25,
5220 GP_1_24_FN, GPSR1_24,
5221 GP_1_23_FN, GPSR1_23,
5222 GP_1_22_FN, GPSR1_22,
5223 GP_1_21_FN, GPSR1_21,
5224 GP_1_20_FN, GPSR1_20,
5225 GP_1_19_FN, GPSR1_19,
5226 GP_1_18_FN, GPSR1_18,
5227 GP_1_17_FN, GPSR1_17,
5228 GP_1_16_FN, GPSR1_16,
5229 GP_1_15_FN, GPSR1_15,
5230 GP_1_14_FN, GPSR1_14,
5231 GP_1_13_FN, GPSR1_13,
5232 GP_1_12_FN, GPSR1_12,
5233 GP_1_11_FN, GPSR1_11,
5234 GP_1_10_FN, GPSR1_10,
5235 GP_1_9_FN, GPSR1_9,
5236 GP_1_8_FN, GPSR1_8,
5237 GP_1_7_FN, GPSR1_7,
5238 GP_1_6_FN, GPSR1_6,
5239 GP_1_5_FN, GPSR1_5,
5240 GP_1_4_FN, GPSR1_4,
5241 GP_1_3_FN, GPSR1_3,
5242 GP_1_2_FN, GPSR1_2,
5243 GP_1_1_FN, GPSR1_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5244 GP_1_0_FN, GPSR1_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5245 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5246 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
5247 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5248 1, 1, 1, 1),
5249 GROUP(
5250 /* GP2_31_15 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5251 GP_2_14_FN, GPSR2_14,
5252 GP_2_13_FN, GPSR2_13,
5253 GP_2_12_FN, GPSR2_12,
5254 GP_2_11_FN, GPSR2_11,
5255 GP_2_10_FN, GPSR2_10,
5256 GP_2_9_FN, GPSR2_9,
5257 GP_2_8_FN, GPSR2_8,
5258 GP_2_7_FN, GPSR2_7,
5259 GP_2_6_FN, GPSR2_6,
5260 GP_2_5_FN, GPSR2_5,
5261 GP_2_4_FN, GPSR2_4,
5262 GP_2_3_FN, GPSR2_3,
5263 GP_2_2_FN, GPSR2_2,
5264 GP_2_1_FN, GPSR2_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5265 GP_2_0_FN, GPSR2_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5266 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5267 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
5268 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5269 1, 1, 1, 1, 1),
5270 GROUP(
5271 /* GP3_31_16 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5272 GP_3_15_FN, GPSR3_15,
5273 GP_3_14_FN, GPSR3_14,
5274 GP_3_13_FN, GPSR3_13,
5275 GP_3_12_FN, GPSR3_12,
5276 GP_3_11_FN, GPSR3_11,
5277 GP_3_10_FN, GPSR3_10,
5278 GP_3_9_FN, GPSR3_9,
5279 GP_3_8_FN, GPSR3_8,
5280 GP_3_7_FN, GPSR3_7,
5281 GP_3_6_FN, GPSR3_6,
5282 GP_3_5_FN, GPSR3_5,
5283 GP_3_4_FN, GPSR3_4,
5284 GP_3_3_FN, GPSR3_3,
5285 GP_3_2_FN, GPSR3_2,
5286 GP_3_1_FN, GPSR3_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5287 GP_3_0_FN, GPSR3_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5288 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5289 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
5290 GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5291 1, 1, 1, 1, 1, 1, 1),
5292 GROUP(
5293 /* GP4_31_18 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5294 GP_4_17_FN, GPSR4_17,
5295 GP_4_16_FN, GPSR4_16,
5296 GP_4_15_FN, GPSR4_15,
5297 GP_4_14_FN, GPSR4_14,
5298 GP_4_13_FN, GPSR4_13,
5299 GP_4_12_FN, GPSR4_12,
5300 GP_4_11_FN, GPSR4_11,
5301 GP_4_10_FN, GPSR4_10,
5302 GP_4_9_FN, GPSR4_9,
5303 GP_4_8_FN, GPSR4_8,
5304 GP_4_7_FN, GPSR4_7,
5305 GP_4_6_FN, GPSR4_6,
5306 GP_4_5_FN, GPSR4_5,
5307 GP_4_4_FN, GPSR4_4,
5308 GP_4_3_FN, GPSR4_3,
5309 GP_4_2_FN, GPSR4_2,
5310 GP_4_1_FN, GPSR4_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5311 GP_4_0_FN, GPSR4_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5312 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5313 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5314 0, 0,
5315 0, 0,
5316 0, 0,
5317 0, 0,
5318 0, 0,
5319 0, 0,
5320 GP_5_25_FN, GPSR5_25,
5321 GP_5_24_FN, GPSR5_24,
5322 GP_5_23_FN, GPSR5_23,
5323 GP_5_22_FN, GPSR5_22,
5324 GP_5_21_FN, GPSR5_21,
5325 GP_5_20_FN, GPSR5_20,
5326 GP_5_19_FN, GPSR5_19,
5327 GP_5_18_FN, GPSR5_18,
5328 GP_5_17_FN, GPSR5_17,
5329 GP_5_16_FN, GPSR5_16,
5330 GP_5_15_FN, GPSR5_15,
5331 GP_5_14_FN, GPSR5_14,
5332 GP_5_13_FN, GPSR5_13,
5333 GP_5_12_FN, GPSR5_12,
5334 GP_5_11_FN, GPSR5_11,
5335 GP_5_10_FN, GPSR5_10,
5336 GP_5_9_FN, GPSR5_9,
5337 GP_5_8_FN, GPSR5_8,
5338 GP_5_7_FN, GPSR5_7,
5339 GP_5_6_FN, GPSR5_6,
5340 GP_5_5_FN, GPSR5_5,
5341 GP_5_4_FN, GPSR5_4,
5342 GP_5_3_FN, GPSR5_3,
5343 GP_5_2_FN, GPSR5_2,
5344 GP_5_1_FN, GPSR5_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5345 GP_5_0_FN, GPSR5_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5346 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5347 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5348 GP_6_31_FN, GPSR6_31,
5349 GP_6_30_FN, GPSR6_30,
5350 GP_6_29_FN, GPSR6_29,
5351 GP_6_28_FN, GPSR6_28,
5352 GP_6_27_FN, GPSR6_27,
5353 GP_6_26_FN, GPSR6_26,
5354 GP_6_25_FN, GPSR6_25,
5355 GP_6_24_FN, GPSR6_24,
5356 GP_6_23_FN, GPSR6_23,
5357 GP_6_22_FN, GPSR6_22,
5358 GP_6_21_FN, GPSR6_21,
5359 GP_6_20_FN, GPSR6_20,
5360 GP_6_19_FN, GPSR6_19,
5361 GP_6_18_FN, GPSR6_18,
5362 GP_6_17_FN, GPSR6_17,
5363 GP_6_16_FN, GPSR6_16,
5364 GP_6_15_FN, GPSR6_15,
5365 GP_6_14_FN, GPSR6_14,
5366 GP_6_13_FN, GPSR6_13,
5367 GP_6_12_FN, GPSR6_12,
5368 GP_6_11_FN, GPSR6_11,
5369 GP_6_10_FN, GPSR6_10,
5370 GP_6_9_FN, GPSR6_9,
5371 GP_6_8_FN, GPSR6_8,
5372 GP_6_7_FN, GPSR6_7,
5373 GP_6_6_FN, GPSR6_6,
5374 GP_6_5_FN, GPSR6_5,
5375 GP_6_4_FN, GPSR6_4,
5376 GP_6_3_FN, GPSR6_3,
5377 GP_6_2_FN, GPSR6_2,
5378 GP_6_1_FN, GPSR6_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5379 GP_6_0_FN, GPSR6_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5380 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5381 { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
5382 GROUP(-28, 1, 1, 1, 1),
5383 GROUP(
5384 /* GP7_31_4 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5385 GP_7_3_FN, GPSR7_3,
5386 GP_7_2_FN, GPSR7_2,
5387 GP_7_1_FN, GPSR7_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5388 GP_7_0_FN, GPSR7_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5389 },
5390#undef F_
5391#undef FM
5392
5393#define F_(x, y) x,
5394#define FM(x) FN_##x,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5395 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5396 IP0_31_28
5397 IP0_27_24
5398 IP0_23_20
5399 IP0_19_16
5400 IP0_15_12
5401 IP0_11_8
5402 IP0_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5403 IP0_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5404 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5405 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5406 IP1_31_28
5407 IP1_27_24
5408 IP1_23_20
5409 IP1_19_16
5410 IP1_15_12
5411 IP1_11_8
5412 IP1_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5413 IP1_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5414 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5415 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5416 IP2_31_28
5417 IP2_27_24
5418 IP2_23_20
5419 IP2_19_16
5420 IP2_15_12
5421 IP2_11_8
5422 IP2_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5423 IP2_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5424 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5425 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5426 IP3_31_28
5427 IP3_27_24
5428 IP3_23_20
5429 IP3_19_16
5430 IP3_15_12
5431 IP3_11_8
5432 IP3_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5433 IP3_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5434 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5435 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5436 IP4_31_28
5437 IP4_27_24
5438 IP4_23_20
5439 IP4_19_16
5440 IP4_15_12
5441 IP4_11_8
5442 IP4_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5443 IP4_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5444 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5445 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5446 IP5_31_28
5447 IP5_27_24
5448 IP5_23_20
5449 IP5_19_16
5450 IP5_15_12
5451 IP5_11_8
5452 IP5_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5453 IP5_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5454 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5455 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5456 IP6_31_28
5457 IP6_27_24
5458 IP6_23_20
5459 IP6_19_16
5460 IP6_15_12
5461 IP6_11_8
5462 IP6_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5463 IP6_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5464 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5465 { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
5466 GROUP(4, 4, 4, 4, -4, 4, 4, 4),
5467 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5468 IP7_31_28
5469 IP7_27_24
5470 IP7_23_20
5471 IP7_19_16
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5472 /* IP7_15_12 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5473 IP7_11_8
5474 IP7_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5475 IP7_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5476 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5477 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5478 IP8_31_28
5479 IP8_27_24
5480 IP8_23_20
5481 IP8_19_16
5482 IP8_15_12
5483 IP8_11_8
5484 IP8_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5485 IP8_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5486 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5487 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5488 IP9_31_28
5489 IP9_27_24
5490 IP9_23_20
5491 IP9_19_16
5492 IP9_15_12
5493 IP9_11_8
5494 IP9_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5495 IP9_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5496 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5497 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5498 IP10_31_28
5499 IP10_27_24
5500 IP10_23_20
5501 IP10_19_16
5502 IP10_15_12
5503 IP10_11_8
5504 IP10_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5505 IP10_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5506 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5507 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5508 IP11_31_28
5509 IP11_27_24
5510 IP11_23_20
5511 IP11_19_16
5512 IP11_15_12
5513 IP11_11_8
5514 IP11_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5515 IP11_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5516 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5517 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5518 IP12_31_28
5519 IP12_27_24
5520 IP12_23_20
5521 IP12_19_16
5522 IP12_15_12
5523 IP12_11_8
5524 IP12_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5525 IP12_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5526 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5527 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5528 IP13_31_28
5529 IP13_27_24
5530 IP13_23_20
5531 IP13_19_16
5532 IP13_15_12
5533 IP13_11_8
5534 IP13_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5535 IP13_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5536 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5537 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5538 IP14_31_28
5539 IP14_27_24
5540 IP14_23_20
5541 IP14_19_16
5542 IP14_15_12
5543 IP14_11_8
5544 IP14_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5545 IP14_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5546 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5547 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5548 IP15_31_28
5549 IP15_27_24
5550 IP15_23_20
5551 IP15_19_16
5552 IP15_15_12
5553 IP15_11_8
5554 IP15_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5555 IP15_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5556 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5557 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5558 IP16_31_28
5559 IP16_27_24
5560 IP16_23_20
5561 IP16_19_16
5562 IP16_15_12
5563 IP16_11_8
5564 IP16_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5565 IP16_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5566 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5567 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5568 IP17_31_28
5569 IP17_27_24
5570 IP17_23_20
5571 IP17_19_16
5572 IP17_15_12
5573 IP17_11_8
5574 IP17_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5575 IP17_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5576 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5577 { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
5578 GROUP(-24, 4, 4),
5579 GROUP(
5580 /* IP18_31_8 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5581 IP18_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5582 IP18_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5583 },
5584#undef F_
5585#undef FM
5586
5587#define F_(x, y) x,
5588#define FM(x) FN_##x,
5589 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5590 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
5591 1, 1, 1, 2, 2, 1, 2, -3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5592 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5593 MOD_SEL0_31_30_29
5594 MOD_SEL0_28_27
5595 MOD_SEL0_26_25_24
5596 MOD_SEL0_23
5597 MOD_SEL0_22
5598 MOD_SEL0_21
5599 MOD_SEL0_20
5600 MOD_SEL0_19
5601 MOD_SEL0_18_17
5602 MOD_SEL0_16
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5603 /* RESERVED 15 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5604 MOD_SEL0_14_13
5605 MOD_SEL0_12
5606 MOD_SEL0_11
5607 MOD_SEL0_10
5608 MOD_SEL0_9_8
5609 MOD_SEL0_7_6
5610 MOD_SEL0_5
5611 MOD_SEL0_4_3
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5612 /* RESERVED 2, 1, 0 */ ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5613 },
5614 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5615 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5616 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5617 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5618 MOD_SEL1_31_30
5619 MOD_SEL1_29_28_27
5620 MOD_SEL1_26
5621 MOD_SEL1_25_24
5622 MOD_SEL1_23_22_21
5623 MOD_SEL1_20
5624 MOD_SEL1_19
5625 MOD_SEL1_18_17
5626 MOD_SEL1_16
5627 MOD_SEL1_15_14
5628 MOD_SEL1_13
5629 MOD_SEL1_12
5630 MOD_SEL1_11
5631 MOD_SEL1_10
5632 MOD_SEL1_9
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5633 /* RESERVED 8, 7 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5634 MOD_SEL1_6
5635 MOD_SEL1_5
5636 MOD_SEL1_4
5637 MOD_SEL1_3
5638 MOD_SEL1_2
5639 MOD_SEL1_1
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5640 MOD_SEL1_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5641 },
5642 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5643 GROUP(1, 1, 1, 2, 1, 3, -1, 1, 1, 1, 1, 1,
5644 -16, 1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5645 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5646 MOD_SEL2_31
5647 MOD_SEL2_30
5648 MOD_SEL2_29
5649 MOD_SEL2_28_27
5650 MOD_SEL2_26
5651 MOD_SEL2_25_24_23
5652 /* RESERVED 22 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5653 MOD_SEL2_21
5654 MOD_SEL2_20
5655 MOD_SEL2_19
5656 MOD_SEL2_18
5657 MOD_SEL2_17
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5658 /* RESERVED 16-1 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5659 MOD_SEL2_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5660 },
Marek Vasut14dfdd62023-09-17 16:08:40 +0200[diff] [blame]5661 { /* sentinel */ }
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5662};
5663
5664static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5665 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5666 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5667 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5668 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5669 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5670 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5671 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5672 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5673 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5674 } },
5675 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5676 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5677 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5678 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5679 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5680 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5681 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5682 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5683 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5684 } },
5685 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5686 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5687 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5688 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5689 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5690 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5691 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5692 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5693 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5694 } },
5695 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5696 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5697 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5698 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5699 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5700 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5701 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5702 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5703 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5704 } },
5705 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5706 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5707 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5708 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5709 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5710 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5711 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5712 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5713 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5714 } },
5715 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5716 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5717 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5718 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5719 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5720 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5721 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5722 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5723 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5724 } },
5725 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5726 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5727 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5728 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5729 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5730 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5731 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5732 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5733 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5734 } },
5735 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5736 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5737 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5738 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5739 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5740 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5741 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5742 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5743 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5744 } },
5745 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5746 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5747 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5748 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5749 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5750 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5751 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5752 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5753 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5754 } },
5755 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5756 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5757 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5758 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5759 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5760 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5761 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5762 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5763 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5764 } },
5765 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5766 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5767 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5768 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5769 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5770 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5771 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5772 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5773 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5774 } },
5775 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5776 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5777 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5778 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5779 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5780 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5781 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5782 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5783 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5784 } },
5785 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5786#ifdef CONFIG_PINCTRL_PFC_R8A77951
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5787 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
5788#endif
5789 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
5790 { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
5791 { PIN_TMS, 4, 2 }, /* TMS */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5792 } },
5793 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5794 { PIN_TDO, 28, 2 }, /* TDO */
5795 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5796 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5797 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5798 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5799 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5800 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5801 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5802 } },
5803 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5804 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5805 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5806 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5807 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5808 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5809 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5810 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5811 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5812 } },
5813 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5814 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5815 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5816 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5817 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5818 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5819 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5820 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5821 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5822 } },
5823 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5824 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5825 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5826 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5827 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5828 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5829 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5830 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5831 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5832 } },
5833 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5834 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5835 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5836 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5837 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5838 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5839 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5840 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5841 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5842 } },
5843 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5844 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5845 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5846 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5847 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5848 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5849 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5850 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5851 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5852 } },
5853 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5854 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5855 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5856 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5857 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5858 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5859 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5860 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5861 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5862 } },
5863 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5864 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5865 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5866 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5867 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5868 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5869 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5870 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5871 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5872 } },
5873 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5874 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5875 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5876 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5877 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5878 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5879 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5880 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5881 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5882 } },
5883 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5884 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5885 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5886 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5887 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5888 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5889 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5890 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5891 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5892 } },
5893 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5894 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5895 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5896 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5897 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5898 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5899 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5900 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5901 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5902 } },
5903 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5904 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5905 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5906 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5907 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5908 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5909 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */
5910 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5911 } },
Marek Vasut14dfdd62023-09-17 16:08:40 +0200[diff] [blame]5912 { /* sentinel */ }
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5913};
5914
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5915enum ioctrl_regs {
5916 POCCTRL,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5917 TDSELCTRL,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5918};
5919
5920static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5921 [POCCTRL] = { 0xe6060380, },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5922 [TDSELCTRL] = { 0xe60603c0, },
Marek Vasut14dfdd62023-09-17 16:08:40 +0200[diff] [blame]5923 { /* sentinel */ }
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5924};
5925
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5926static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5927{
5928 int bit = -EINVAL;
5929
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5930 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5931
5932 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5933 bit = pin & 0x1f;
5934
5935 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5936 bit = (pin & 0x1f) + 12;
5937
5938 return bit;
5939}
5940
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5941static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5942 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5943 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
5944 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
5945 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
5946 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
5947 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
5948 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
5949 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
5950 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
5951 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
5952 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
5953 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
5954 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
5955 [12] = PIN_RPC_INT_N, /* RPC_INT# */
5956 [13] = PIN_RPC_WP_N, /* RPC_WP# */
5957 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
5958 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
5959 [16] = PIN_AVB_RXC, /* AVB_RXC */
5960 [17] = PIN_AVB_RD0, /* AVB_RD0 */
5961 [18] = PIN_AVB_RD1, /* AVB_RD1 */
5962 [19] = PIN_AVB_RD2, /* AVB_RD2 */
5963 [20] = PIN_AVB_RD3, /* AVB_RD3 */
5964 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
5965 [22] = PIN_AVB_TXC, /* AVB_TXC */
5966 [23] = PIN_AVB_TD0, /* AVB_TD0 */
5967 [24] = PIN_AVB_TD1, /* AVB_TD1 */
5968 [25] = PIN_AVB_TD2, /* AVB_TD2 */
5969 [26] = PIN_AVB_TD3, /* AVB_TD3 */
5970 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
5971 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5972 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5973 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5974 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5975 } },
5976 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5977 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5978 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5979 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5980 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5981 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5982 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5983 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5984 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5985 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5986 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5987 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5988 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5989 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5990 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5991 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5992 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5993 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5994 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5995 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5996 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5997 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5998 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5999 [22] = RCAR_GP_PIN(1, 10), /* A10 */
6000 [23] = RCAR_GP_PIN(1, 11), /* A11 */
6001 [24] = RCAR_GP_PIN(1, 12), /* A12 */
6002 [25] = RCAR_GP_PIN(1, 13), /* A13 */
6003 [26] = RCAR_GP_PIN(1, 14), /* A14 */
6004 [27] = RCAR_GP_PIN(1, 15), /* A15 */
6005 [28] = RCAR_GP_PIN(1, 16), /* A16 */
6006 [29] = RCAR_GP_PIN(1, 17), /* A17 */
6007 [30] = RCAR_GP_PIN(1, 18), /* A18 */
6008 [31] = RCAR_GP_PIN(1, 19), /* A19 */
6009 } },
6010 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
6011 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
6012 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
6013 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
6014 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
6015 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
6016 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
6017 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
6018 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
6019 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6020 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6021 [10] = RCAR_GP_PIN(0, 0), /* D0 */
6022 [11] = RCAR_GP_PIN(0, 1), /* D1 */
6023 [12] = RCAR_GP_PIN(0, 2), /* D2 */
6024 [13] = RCAR_GP_PIN(0, 3), /* D3 */
6025 [14] = RCAR_GP_PIN(0, 4), /* D4 */
6026 [15] = RCAR_GP_PIN(0, 5), /* D5 */
6027 [16] = RCAR_GP_PIN(0, 6), /* D6 */
6028 [17] = RCAR_GP_PIN(0, 7), /* D7 */
6029 [18] = RCAR_GP_PIN(0, 8), /* D8 */
6030 [19] = RCAR_GP_PIN(0, 9), /* D9 */
6031 [20] = RCAR_GP_PIN(0, 10), /* D10 */
6032 [21] = RCAR_GP_PIN(0, 11), /* D11 */
6033 [22] = RCAR_GP_PIN(0, 12), /* D12 */
6034 [23] = RCAR_GP_PIN(0, 13), /* D13 */
6035 [24] = RCAR_GP_PIN(0, 14), /* D14 */
6036 [25] = RCAR_GP_PIN(0, 15), /* D15 */
6037 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
6038 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6039 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
6040 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6041 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
6042 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6043 } },
6044 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6045 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
6046 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
6047 [ 2] = PIN_FSCLKST_N, /* FSCLKST# */
6048 [ 3] = PIN_EXTALR, /* EXTALR*/
6049 [ 4] = PIN_TRST_N, /* TRST# */
6050 [ 5] = PIN_TCK, /* TCK */
6051 [ 6] = PIN_TMS, /* TMS */
6052 [ 7] = PIN_TDI, /* TDI */
6053 [ 8] = SH_PFC_PIN_NONE,
6054 [ 9] = PIN_ASEBRK, /* ASEBRK */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6055 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6056 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6057 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6058 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6059 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6060 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6061 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6062 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6063 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6064 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6065 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6066 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6067 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6068 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6069 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6070 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6071 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6072 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6073 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6074 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6075 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6076 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6077 } },
6078 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6079 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6080 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6081 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6082 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6083 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6084 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6085 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6086 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6087 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6088 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6089 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6090 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6091 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6092 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6093 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6094 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6095 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6096 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6097 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6098 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6099 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6100 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6101 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6102 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6103 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6104 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6105 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6106 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6107 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6108 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6109 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6110 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6111 } },
6112 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6113 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6114 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6115 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6116 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6117 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6118 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6119 [ 6] = PIN_MLB_REF, /* MLB_REF */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6120 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6121 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6122 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6123 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6124 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6125 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6126 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6127 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6128 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6129 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6130 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6131 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6132 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6133 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6134 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6135 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6136 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6137 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6138 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6139 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6140 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6141 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6142 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6143 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6144 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6145 } },
6146 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6147 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6148 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6149 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6150 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6151 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6152 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
6153 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6154 [ 7] = SH_PFC_PIN_NONE,
6155 [ 8] = SH_PFC_PIN_NONE,
6156 [ 9] = SH_PFC_PIN_NONE,
6157 [10] = SH_PFC_PIN_NONE,
6158 [11] = SH_PFC_PIN_NONE,
6159 [12] = SH_PFC_PIN_NONE,
6160 [13] = SH_PFC_PIN_NONE,
6161 [14] = SH_PFC_PIN_NONE,
6162 [15] = SH_PFC_PIN_NONE,
6163 [16] = SH_PFC_PIN_NONE,
6164 [17] = SH_PFC_PIN_NONE,
6165 [18] = SH_PFC_PIN_NONE,
6166 [19] = SH_PFC_PIN_NONE,
6167 [20] = SH_PFC_PIN_NONE,
6168 [21] = SH_PFC_PIN_NONE,
6169 [22] = SH_PFC_PIN_NONE,
6170 [23] = SH_PFC_PIN_NONE,
6171 [24] = SH_PFC_PIN_NONE,
6172 [25] = SH_PFC_PIN_NONE,
6173 [26] = SH_PFC_PIN_NONE,
6174 [27] = SH_PFC_PIN_NONE,
6175 [28] = SH_PFC_PIN_NONE,
6176 [29] = SH_PFC_PIN_NONE,
6177 [30] = SH_PFC_PIN_NONE,
6178 [31] = SH_PFC_PIN_NONE,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6179 } },
Marek Vasut14dfdd62023-09-17 16:08:40 +0200[diff] [blame]6180 { /* sentinel */ }
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6181};
6182
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]6183static const struct sh_pfc_soc_operations r8a77951_pfc_ops = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6184 .pin_to_pocctrl = r8a77951_pin_to_pocctrl,
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]6185 .get_bias = rcar_pinmux_get_bias,
6186 .set_bias = rcar_pinmux_set_bias,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6187};
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]6188
6189#ifdef CONFIG_PINCTRL_PFC_R8A774E1
6190const struct sh_pfc_soc_info r8a774e1_pinmux_info = {
6191 .name = "r8a774e1_pfc",
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]6192 .ops = &r8a77951_pfc_ops,
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]6193 .unlock_reg = 0xe6060000, /* PMMR */
6194
6195 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6196
6197 .pins = pinmux_pins,
6198 .nr_pins = ARRAY_SIZE(pinmux_pins),
6199 .groups = pinmux_groups.common,
6200 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6201 .functions = pinmux_functions.common,
6202 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6203
6204 .cfg_regs = pinmux_config_regs,
6205 .drive_regs = pinmux_drive_regs,
6206 .bias_regs = pinmux_bias_regs,
6207 .ioctrl_regs = pinmux_ioctrl_regs,
6208
6209 .pinmux_data = pinmux_data,
6210 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6211};
6212#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6213
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]6214#ifdef CONFIG_PINCTRL_PFC_R8A77951
6215const struct sh_pfc_soc_info r8a77951_pinmux_info = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6216 .name = "r8a77951_pfc",
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]6217 .ops = &r8a77951_pfc_ops,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6218 .unlock_reg = 0xe6060000, /* PMMR */
6219
6220 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6221
6222 .pins = pinmux_pins,
6223 .nr_pins = ARRAY_SIZE(pinmux_pins),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]6224 .groups = pinmux_groups.common,
6225 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6226 ARRAY_SIZE(pinmux_groups.automotive),
6227 .functions = pinmux_functions.common,
6228 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6229 ARRAY_SIZE(pinmux_functions.automotive),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6230
6231 .cfg_regs = pinmux_config_regs,
6232 .drive_regs = pinmux_drive_regs,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6233 .bias_regs = pinmux_bias_regs,
6234 .ioctrl_regs = pinmux_ioctrl_regs,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6235
6236 .pinmux_data = pinmux_data,
6237 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6238};
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]6239#endif