blob: 816402fdbf2ecc78d92cc7c5e9a44dc392ac54dd [file] [log] [blame]
Kuan Lim Leeeb66fc32023-09-19 15:30:36 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2022 StarFive, Inc. All rights reserved.
4 * Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
5 */
6
7#include <common.h>
8#include <clk.h>
9#include <dm.h>
10#include <time.h>
11#include <timer.h>
12#include <asm/io.h>
13#include <dm/device-internal.h>
14#include <linux/err.h>
15
16#define STF_TIMER_INT_STATUS 0x00
17#define STF_TIMER_CTL 0x04
18#define STF_TIMER_LOAD 0x08
19#define STF_TIMER_ENABLE 0x10
20#define STF_TIMER_RELOAD 0x14
21#define STF_TIMER_VALUE 0x18
22#define STF_TIMER_INT_CLR 0x20
23#define STF_TIMER_INT_MASK 0x24
24
25struct starfive_timer_priv {
26 void __iomem *base;
27 u32 timer_size;
28};
29
30static u64 notrace starfive_get_count(struct udevice *dev)
31{
32 struct starfive_timer_priv *priv = dev_get_priv(dev);
33
34 /* Read decrement timer value and convert to increment value */
35 return priv->timer_size - readl(priv->base + STF_TIMER_VALUE);
36}
37
38static const struct timer_ops starfive_ops = {
39 .get_count = starfive_get_count,
40};
41
42static int starfive_probe(struct udevice *dev)
43{
44 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
45 struct starfive_timer_priv *priv = dev_get_priv(dev);
46 int timer_channel;
47 struct clk clk;
48 int ret;
49
50 priv->base = dev_read_addr_ptr(dev);
51 if (IS_ERR(priv->base))
52 return PTR_ERR(priv->base);
53
54 timer_channel = dev_read_u32_default(dev, "channel", 0);
55 priv->base = priv->base + (0x40 * timer_channel);
56
57 /* Get clock rate from channel selectecd*/
58 ret = clk_get_by_index(dev, timer_channel, &clk);
59 if (ret)
60 return ret;
61
62 ret = clk_enable(&clk);
63 if (ret)
64 return ret;
65 uc_priv->clock_rate = clk_get_rate(&clk);
66
67 /* Initiate timer, channel 0 */
68 /* Unmask Interrupt Mask */
69 writel(0, priv->base + STF_TIMER_INT_MASK);
70 /* Single run mode Setting */
71 if (dev_read_bool(dev, "single-run"))
72 writel(1, priv->base + STF_TIMER_CTL);
73 /* Set Reload value */
74 priv->timer_size = dev_read_u32_default(dev, "timer-size", 0xffffffff);
75 writel(priv->timer_size, priv->base + STF_TIMER_LOAD);
76 /* Enable to start timer */
77 writel(1, priv->base + STF_TIMER_ENABLE);
78
79 return 0;
80}
81
82static const struct udevice_id starfive_ids[] = {
83 { .compatible = "starfive,jh8100-timers" },
84 { }
85};
86
87U_BOOT_DRIVER(jh8100_starfive_timer) = {
88 .name = "jh8100_starfive_timer",
89 .id = UCLASS_TIMER,
90 .of_match = starfive_ids,
91 .probe = starfive_probe,
92 .ops = &starfive_ops,
93 .priv_auto = sizeof(struct starfive_timer_priv),
94};