blob: 3c48a9141d0a8558103f2a51ac86bd0e90200205 [file] [log] [blame]
Michael Walle36ba7642020-10-15 23:08:57 +02001// SPDX-License-Identifier: GPL-2.0+
2
3#include <common.h>
Michael Walle3b185bc2021-11-15 23:45:46 +01004#include <dm.h>
Michael Walle36ba7642020-10-15 23:08:57 +02005#include <malloc.h>
6#include <errno.h>
7#include <fsl_ddr.h>
8#include <fdt_support.h>
Simon Glass3ba929a2020-10-30 21:38:53 -06009#include <asm/global_data.h>
Michael Walle36ba7642020-10-15 23:08:57 +020010#include <linux/libfdt.h>
11#include <env_internal.h>
12#include <asm/arch-fsl-layerscape/soc.h>
13#include <asm/arch-fsl-layerscape/fsl_icid.h>
14#include <i2c.h>
15#include <asm/arch/soc.h>
16#include <fsl_immap.h>
17#include <netdev.h>
Michael Walle324b7b42021-11-15 23:45:49 +010018#include <wdt.h>
Michael Walle36ba7642020-10-15 23:08:57 +020019
Michael Walle3b185bc2021-11-15 23:45:46 +010020#include <sl28cpld.h>
Michael Walle36ba7642020-10-15 23:08:57 +020021#include <fdtdec.h>
22#include <miiphy.h>
23
24DECLARE_GLOBAL_DATA_PTR;
25
Michael Walle101410e2021-01-08 00:08:59 +010026int board_early_init_f(void)
27{
28 fsl_lsch3_early_init_f();
29 return 0;
30}
31
Michael Walle36ba7642020-10-15 23:08:57 +020032int board_init(void)
33{
34 if (CONFIG_IS_ENABLED(FSL_CAAM))
35 sec_init();
36
37 return 0;
38}
39
40int board_eth_init(struct bd_info *bis)
41{
42 return pci_eth_init(bis);
43}
44
Michael Walle3b185bc2021-11-15 23:45:46 +010045static int __sl28cpld_read(uint reg)
46{
47 struct udevice *dev;
48 int ret;
49
50 ret = uclass_get_device_by_driver(UCLASS_NOP,
51 DM_DRIVER_GET(sl28cpld), &dev);
52 if (ret)
53 return ret;
54
55 return sl28cpld_read(dev, reg);
56}
57
58static void print_cpld_version(void)
59{
60 int version = __sl28cpld_read(SL28CPLD_VERSION);
61
62 if (version < 0)
63 printf("CPLD: error reading version (%d)\n", version);
64 else
65 printf("CPLD: v%d\n", version);
66}
67
Michael Walle36ba7642020-10-15 23:08:57 +020068int checkboard(void)
69{
70 printf("EL: %d\n", current_el());
Michael Walle3b185bc2021-11-15 23:45:46 +010071 if (CONFIG_IS_ENABLED(SL28CPLD))
72 print_cpld_version();
73
Michael Walle36ba7642020-10-15 23:08:57 +020074 return 0;
75}
76
Michael Walle324b7b42021-11-15 23:45:49 +010077static void stop_recovery_watchdog(void)
78{
79 struct udevice *dev;
80 int ret;
81
82 ret = uclass_get_device_by_driver(UCLASS_WDT,
83 DM_DRIVER_GET(sl28cpld_wdt), &dev);
84 if (!ret)
85 wdt_stop(dev);
86}
87
88int fsl_board_late_init(void)
89{
90 /*
91 * Usually, the after a board reset, the watchdog is enabled by
92 * default. This is to supervise the bootloader boot-up. Therefore,
93 * to prevent a watchdog reset if we don't actively kick it, we have
94 * to disable it.
95 *
96 * If the watchdog isn't enabled at reset (which is a configuration
97 * option) disabling it doesn't hurt either.
98 */
99 if (!CONFIG_IS_ENABLED(WATCHDOG_AUTOSTART))
100 stop_recovery_watchdog();
101
102 return 0;
103}
104
Michael Walle36ba7642020-10-15 23:08:57 +0200105void detail_board_ddr_info(void)
106{
Michael Walle36ba7642020-10-15 23:08:57 +0200107 print_ddr_info(0);
108}
109
110int ft_board_setup(void *blob, struct bd_info *bd)
111{
112 u64 base[CONFIG_NR_DRAM_BANKS];
113 u64 size[CONFIG_NR_DRAM_BANKS];
114 int nbanks = CONFIG_NR_DRAM_BANKS;
Michael Walle76427fb2020-11-18 17:46:02 +0100115 int node;
Michael Walle36ba7642020-10-15 23:08:57 +0200116 int i;
117
118 ft_cpu_setup(blob, bd);
119
120 /* fixup DT for the two GPP DDR banks */
121 for (i = 0; i < nbanks; i++) {
122 base[i] = gd->bd->bi_dram[i].start;
123 size[i] = gd->bd->bi_dram[i].size;
124 }
125
126 fdt_fixup_memory_banks(blob, base, size, nbanks);
127
128 fdt_fixup_icid(blob);
129
Michael Walle76427fb2020-11-18 17:46:02 +0100130 if (CONFIG_IS_ENABLED(SL28_SPL_LOADS_OPTEE_BL32)) {
131 node = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz");
132 if (node)
Marek BehĂșnf872e832021-11-26 14:57:08 +0100133 fdt_set_node_status(blob, node, FDT_STATUS_OKAY);
Michael Walle76427fb2020-11-18 17:46:02 +0100134 }
135
Michael Walle36ba7642020-10-15 23:08:57 +0200136 return 0;
137}