| Aaron Williams | 4fd1e55 | 2021-04-23 19:56:32 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2020 Marvell International Ltd. |
| 4 | * |
| 5 | * Definitions for enumerations used with Octeon CSRs. |
| 6 | */ |
| 7 | |
| 8 | #ifndef __CVMX_CSR_ENUMS_H__ |
| 9 | #define __CVMX_CSR_ENUMS_H__ |
| 10 | |
| 11 | typedef enum { |
| 12 | CVMX_IPD_OPC_MODE_STT = 0LL, |
| 13 | CVMX_IPD_OPC_MODE_STF = 1LL, |
| 14 | CVMX_IPD_OPC_MODE_STF1_STT = 2LL, |
| 15 | CVMX_IPD_OPC_MODE_STF2_STT = 3LL |
| 16 | } cvmx_ipd_mode_t; |
| 17 | |
| 18 | /** |
| 19 | * Enumeration representing the amount of packet processing |
| 20 | * and validation performed by the input hardware. |
| 21 | */ |
| 22 | typedef enum { |
| 23 | CVMX_PIP_PORT_CFG_MODE_NONE = 0ull, |
| 24 | CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull, |
| 25 | CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull |
| 26 | } cvmx_pip_port_parse_mode_t; |
| 27 | |
| 28 | /** |
| 29 | * This enumeration controls how a QoS watcher matches a packet. |
| 30 | * |
| 31 | * @deprecated This enumeration was used with cvmx_pip_config_watcher which has |
| 32 | * been deprecated. |
| 33 | */ |
| 34 | typedef enum { |
| 35 | CVMX_PIP_QOS_WATCH_DISABLE = 0ull, |
| 36 | CVMX_PIP_QOS_WATCH_PROTNH = 1ull, |
| 37 | CVMX_PIP_QOS_WATCH_TCP = 2ull, |
| 38 | CVMX_PIP_QOS_WATCH_UDP = 3ull |
| 39 | } cvmx_pip_qos_watch_types; |
| 40 | |
| 41 | /** |
| 42 | * This enumeration is used in PIP tag config to control how |
| 43 | * POW tags are generated by the hardware. |
| 44 | */ |
| 45 | typedef enum { |
| 46 | CVMX_PIP_TAG_MODE_TUPLE = 0ull, |
| 47 | CVMX_PIP_TAG_MODE_MASK = 1ull, |
| 48 | CVMX_PIP_TAG_MODE_IP_OR_MASK = 2ull, |
| 49 | CVMX_PIP_TAG_MODE_TUPLE_XOR_MASK = 3ull |
| 50 | } cvmx_pip_tag_mode_t; |
| 51 | |
| 52 | /** |
| 53 | * Tag type definitions |
| 54 | */ |
| 55 | typedef enum { |
| 56 | CVMX_POW_TAG_TYPE_ORDERED = 0L, |
| 57 | CVMX_POW_TAG_TYPE_ATOMIC = 1L, |
| 58 | CVMX_POW_TAG_TYPE_NULL = 2L, |
| 59 | CVMX_POW_TAG_TYPE_NULL_NULL = 3L |
| 60 | } cvmx_pow_tag_type_t; |
| 61 | |
| 62 | /** |
| 63 | * LCR bits 0 and 1 control the number of bits per character. See the following table for encodings: |
| 64 | * |
| 65 | * - 00 = 5 bits (bits 0-4 sent) |
| 66 | * - 01 = 6 bits (bits 0-5 sent) |
| 67 | * - 10 = 7 bits (bits 0-6 sent) |
| 68 | * - 11 = 8 bits (all bits sent) |
| 69 | */ |
| 70 | typedef enum { |
| 71 | CVMX_UART_BITS5 = 0, |
| 72 | CVMX_UART_BITS6 = 1, |
| 73 | CVMX_UART_BITS7 = 2, |
| 74 | CVMX_UART_BITS8 = 3 |
| 75 | } cvmx_uart_bits_t; |
| 76 | |
| 77 | typedef enum { |
| 78 | CVMX_UART_IID_NONE = 1, |
| 79 | CVMX_UART_IID_RX_ERROR = 6, |
| 80 | CVMX_UART_IID_RX_DATA = 4, |
| 81 | CVMX_UART_IID_RX_TIMEOUT = 12, |
| 82 | CVMX_UART_IID_TX_EMPTY = 2, |
| 83 | CVMX_UART_IID_MODEM = 0, |
| 84 | CVMX_UART_IID_BUSY = 7 |
| 85 | } cvmx_uart_iid_t; |
| 86 | |
| 87 | #endif /* __CVMX_CSR_ENUMS_H__ */ |