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Yusuke Godacf236022008-03-11 12:55:12 +09001/*
2 * Configuation settings for the Renesas R7780MP board
3 *
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +09004 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Yusuke Godacf236022008-03-11 12:55:12 +09005 * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Yusuke Godacf236022008-03-11 12:55:12 +09008 */
9
10#ifndef __R7780RP_H
11#define __R7780RP_H
12
13#undef DEBUG
Yusuke Godacf236022008-03-11 12:55:12 +090014#define CONFIG_CPU_SH7780 1
15#define CONFIG_R7780MP 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020016#define CONFIG_SYS_R7780MP_OLD_FLASH 1
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +090017#define __LITTLE_ENDIAN__ 1
Yusuke Godacf236022008-03-11 12:55:12 +090018
19/*
20 * Command line configuration.
21 */
22#define CONFIG_CMD_SDRAM
23#define CONFIG_CMD_FLASH
24#define CONFIG_CMD_MEMORY
25#define CONFIG_CMD_PCI
Yusuke Godacf236022008-03-11 12:55:12 +090026#define CONFIG_CMD_PING
Mike Frysinger78dcaf42009-01-28 19:08:14 -050027#define CONFIG_CMD_SAVEENV
Yusuke Godacf236022008-03-11 12:55:12 +090028#define CONFIG_CMD_NFS
29#define CONFIG_CMD_IDE
30#define CONFIG_CMD_EXT2
31#define CONFIG_DOS_PARTITION
32
Jean-Christophe PLAGNIOL-VILLARD6ce9ea62008-08-13 01:40:38 +020033#define CONFIG_SCIF_CONSOLE 1
Yusuke Godacf236022008-03-11 12:55:12 +090034#define CONFIG_BAUDRATE 115200
35#define CONFIG_CONS_SCIF0 1
36
37#define CONFIG_BOOTDELAY 3
38#define CONFIG_BOOTARGS "console=ttySC0,115200"
39#define CONFIG_ENV_OVERWRITE 1
40
41/* check for keypress on bootdelay==0 */
42/*#define CONFIG_ZERO_BOOTDELAY_CHECK*/
43
Nobuhiro Iwamatsub816b982011-01-17 20:50:26 +090044#define CONFIG_SYS_TEXT_BASE 0x0FFC0000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020045#define CONFIG_SYS_SDRAM_BASE (0x08000000)
46#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
Yusuke Godacf236022008-03-11 12:55:12 +090047
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020048#define CONFIG_SYS_LONGHELP
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020049#define CONFIG_SYS_CBSIZE 256
50#define CONFIG_SYS_PBSIZE 256
51#define CONFIG_SYS_MAXARGS 16
52#define CONFIG_SYS_BARGSIZE 512
Yusuke Godacf236022008-03-11 12:55:12 +090053
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020054#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
Wolfgang Denk0708bc62010-10-07 21:51:12 +020055#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
Yusuke Godacf236022008-03-11 12:55:12 +090056
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +090057/* Flash board support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020058#define CONFIG_SYS_FLASH_BASE (0xA0000000)
59#ifdef CONFIG_SYS_R7780MP_OLD_FLASH
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +090060/* NOR Flash (S29PL127J60TFI130) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
62# define CONFIG_SYS_MAX_FLASH_BANKS (2)
63# define CONFIG_SYS_MAX_FLASH_SECT 270
64# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
65 CONFIG_SYS_FLASH_BASE + 0x100000,\
66 CONFIG_SYS_FLASH_BASE + 0x400000,\
67 CONFIG_SYS_FLASH_BASE + 0x700000, }
68#else /* CONFIG_SYS_R7780MP_OLD_FLASH */
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +090069/* NOR Flash (Spantion S29GL256P) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020070# define CONFIG_SYS_MAX_FLASH_BANKS (1)
71# define CONFIG_SYS_MAX_FLASH_SECT 256
72# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
73#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */
Yusuke Godacf236022008-03-11 12:55:12 +090074
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020075#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
Yusuke Godacf236022008-03-11 12:55:12 +090076/* Address of u-boot image in Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020077#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
78#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
Yusuke Godacf236022008-03-11 12:55:12 +090079/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020080#define CONFIG_SYS_MALLOC_LEN (1204 * 1024)
Yusuke Godacf236022008-03-11 12:55:12 +090081
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020082#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
83#define CONFIG_SYS_RX_ETH_BUFFER (8)
Yusuke Godacf236022008-03-11 12:55:12 +090084
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020085#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +020086#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020087#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
88#undef CONFIG_SYS_FLASH_QUIET_TEST
Yusuke Godacf236022008-03-11 12:55:12 +090089/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020090#define CONFIG_SYS_FLASH_EMPTY_INFO
Yusuke Godacf236022008-03-11 12:55:12 +090091
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +020092#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020093#define CONFIG_ENV_SECT_SIZE (256 * 1024)
94#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020095#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
96#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
97#define CONFIG_SYS_FLASH_WRITE_TOUT 500
Yusuke Godacf236022008-03-11 12:55:12 +090098
99/* Board Clock */
100#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +0900101#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
102#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARD32e6acc2009-06-04 12:06:48 +0200103#define CONFIG_SYS_TMU_CLK_DIV 4
Yusuke Godacf236022008-03-11 12:55:12 +0900104
105/* PCI Controller */
106#if defined(CONFIG_CMD_PCI)
107#define CONFIG_PCI
108#define CONFIG_SH4_PCI
Nobuhiro Iwamatsu5aa5d672008-03-24 02:11:26 +0900109#define CONFIG_SH7780_PCI
Yoshihiro Shimoda30e055b2009-02-25 14:26:42 +0900110#define CONFIG_SH7780_PCI_LSR 0x07f00001
111#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
112#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
Yusuke Godacf236022008-03-11 12:55:12 +0900113#define CONFIG_PCI_PNP
114#define CONFIG_PCI_SCAN_SHOW 1
115#define __io
116#define __mem_pci
117
118#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
119#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
120#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
121
122#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
123#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
124#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
Nobuhiro Iwamatsu41773f52009-07-08 11:42:19 +0900125#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
126#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
127#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
Yusuke Godacf236022008-03-11 12:55:12 +0900128#endif /* CONFIG_CMD_PCI */
129
130#if defined(CONFIG_CMD_NET)
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +0900131/*
Nobuhiro Iwamatsu3ac02122008-06-17 16:28:01 +0900132#define CONFIG_RTL8169
133*/
Marcel Ziswilere7422af2009-09-09 21:09:00 +0200134/* AX88796L Support(NE2000 base chip) */
Yusuke Godacf236022008-03-11 12:55:12 +0900135#define CONFIG_DRIVER_AX88796L
136#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
137#endif
138
139/* Compact flash Support */
140#if defined(CONFIG_CMD_IDE)
141#define CONFIG_IDE_RESET 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142#define CONFIG_SYS_PIO_MODE 1
143#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
144#define CONFIG_SYS_IDE_MAXDEVICE 1
145#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
146#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
147#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
148#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
149#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
Albert Aribaud036c6b42010-08-08 05:17:05 +0530150#define CONFIG_IDE_SWAP_IO
Yusuke Godacf236022008-03-11 12:55:12 +0900151#endif /* CONFIG_CMD_IDE */
152
153#endif /* __R7780RP_H */