| Tom Rini | 6b642ac | 2024-10-01 12:20:28 -0600 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: DesignWare based PCIe Endpoint controller on Rockchip SoCs |
| 8 | |
| 9 | maintainers: |
| 10 | - Niklas Cassel <cassel@kernel.org> |
| 11 | |
| 12 | description: |+ |
| 13 | RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare |
| 14 | PCIe IP and thus inherits all the common properties defined in |
| 15 | snps,dw-pcie-ep.yaml. |
| 16 | |
| 17 | allOf: |
| 18 | - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# |
| 19 | - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# |
| 20 | |
| 21 | properties: |
| 22 | compatible: |
| 23 | enum: |
| 24 | - rockchip,rk3568-pcie-ep |
| 25 | - rockchip,rk3588-pcie-ep |
| 26 | |
| 27 | reg: |
| 28 | items: |
| 29 | - description: Data Bus Interface (DBI) registers |
| 30 | - description: Data Bus Interface (DBI) shadow registers |
| 31 | - description: Rockchip designed configuration registers |
| 32 | - description: Memory region used to map remote RC address space |
| 33 | - description: Internal Address Translation Unit (iATU) registers |
| 34 | |
| 35 | reg-names: |
| 36 | items: |
| 37 | - const: dbi |
| 38 | - const: dbi2 |
| 39 | - const: apb |
| 40 | - const: addr_space |
| 41 | - const: atu |
| 42 | |
| 43 | required: |
| 44 | - interrupts |
| 45 | - interrupt-names |
| 46 | |
| 47 | unevaluatedProperties: false |
| 48 | |
| 49 | examples: |
| 50 | - | |
| 51 | #include <dt-bindings/clock/rockchip,rk3588-cru.h> |
| 52 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 53 | #include <dt-bindings/interrupt-controller/irq.h> |
| 54 | #include <dt-bindings/power/rk3588-power.h> |
| 55 | #include <dt-bindings/reset/rockchip,rk3588-cru.h> |
| 56 | |
| 57 | soc { |
| 58 | #address-cells = <2>; |
| 59 | #size-cells = <2>; |
| 60 | |
| 61 | pcie3x4_ep: pcie-ep@fe150000 { |
| 62 | compatible = "rockchip,rk3588-pcie-ep"; |
| 63 | reg = <0xa 0x40000000 0x0 0x00100000>, |
| 64 | <0xa 0x40100000 0x0 0x00100000>, |
| 65 | <0x0 0xfe150000 0x0 0x00010000>, |
| 66 | <0x9 0x00000000 0x0 0x40000000>, |
| 67 | <0xa 0x40300000 0x0 0x00100000>; |
| 68 | reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; |
| 69 | clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, |
| 70 | <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, |
| 71 | <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; |
| 72 | clock-names = "aclk_mst", "aclk_slv", |
| 73 | "aclk_dbi", "pclk", |
| 74 | "aux", "pipe"; |
| 75 | interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, |
| 76 | <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, |
| 77 | <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, |
| 78 | <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, |
| 79 | <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>, |
| 80 | <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>, |
| 81 | <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>, |
| 82 | <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>, |
| 83 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; |
| 84 | interrupt-names = "sys", "pmc", "msg", "legacy", "err", |
| 85 | "dma0", "dma1", "dma2", "dma3"; |
| 86 | max-link-speed = <3>; |
| 87 | num-lanes = <4>; |
| 88 | phys = <&pcie30phy>; |
| 89 | phy-names = "pcie-phy"; |
| 90 | power-domains = <&power RK3588_PD_PCIE>; |
| 91 | resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; |
| 92 | reset-names = "pwr", "pipe"; |
| 93 | }; |
| 94 | }; |
| 95 | ... |