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git01.mediatek.com / filogic / uboot / 9dc8e16966d20b450b3d7b682a35c4ba63f5f9dc / . / configs / chromebook_speedy_defconfig
blob: 0295610ab8a30b1b0f95b6a29e4b1b4a7ae65a36 [file] [log] [blame]
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
Tom Rinid391d8b2021-12-11 14:55:51 -0500[diff] [blame]3CONFIG_SYS_ARCH_TIMER=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]4# CONFIG_SPL_USE_ARCH_MEMCPY is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]5CONFIG_ARCH_ROCKCHIP=y
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]6CONFIG_TEXT_BASE=0x00100000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]7CONFIG_NR_DRAM_BANKS=1
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]8CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
9CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
Tom Rinia77d6f82023-05-01 11:50:26 -0400[diff] [blame]10CONFIG_SF_DEFAULT_SPEED=20000000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]11CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]12CONFIG_SPL_TEXT_BASE=0xff704000
Alper Nebi Yasaka231a242023-07-07 22:16:35 +0300[diff] [blame]13CONFIG_DM_RESET=y
Tom Rini3d2b97c2023-05-29 10:43:26 -0400[diff] [blame]14CONFIG_SYS_MONITOR_LEN=614400
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]15CONFIG_ROCKCHIP_RK3288=y
Simon Glassb58bfe02021-08-08 12:20:09 -0600[diff] [blame]16# CONFIG_SPL_MMC is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]17CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]18CONFIG_SPL_STACK_R_ADDR=0x80000
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]19CONFIG_SPL_STACK=0xff718000
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]20CONFIG_DEBUG_UART_BASE=0xff690000
21CONFIG_DEBUG_UART_CLOCK=24000000
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]22CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassa5820472021-08-08 12:20:14 -0600[diff] [blame]23CONFIG_SPL_SPI=y
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]24CONFIG_SYS_LOAD_ADDR=0x800800
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]25CONFIG_SPL_PAYLOAD="u-boot.img"
Tom Rini84610272020-07-28 08:46:52 -0400[diff] [blame]26CONFIG_DEBUG_UART=y
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]27CONFIG_USE_PREBOOT=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]28CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]29CONFIG_SILENT_CONSOLE=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]30# CONFIG_DISPLAY_CPUINFO is not set
31CONFIG_DISPLAY_BOARDINFO_LATE=y
Urja Rannikkoe8c4c962020-05-13 19:15:21 +0000[diff] [blame]32CONFIG_BOARD_EARLY_INIT_R=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]33CONFIG_SPL_PAD_TO=0x7f8000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]34CONFIG_SPL_NO_BSS_LIMIT=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]35# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]36# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]37CONFIG_SPL_STACK_R=y
38CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]39# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
Simon Glassefc12232021-07-14 17:05:32 -0500[diff] [blame]40# CONFIG_SPL_CRC32 is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]41CONFIG_SPL_SPI_LOAD=y
Tom Rinie22fa4f2021-08-10 15:08:46 -0400[diff] [blame]42CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
Tom Rinif3c2f992022-06-25 19:29:46 -0400[diff] [blame]43CONFIG_SYS_BOOTM_LEN=0x4000000
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]44CONFIG_CMD_GPIO=y
45CONFIG_CMD_GPT=y
46CONFIG_CMD_I2C=y
47CONFIG_CMD_MMC=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]48CONFIG_CMD_SF_TEST=y
49CONFIG_CMD_SPI=y
50CONFIG_CMD_USB=y
51# CONFIG_CMD_SETEXPR is not set
52CONFIG_CMD_CACHE=y
53CONFIG_CMD_TIME=y
54CONFIG_CMD_PMIC=y
55CONFIG_CMD_REGULATOR=y
56# CONFIG_SPL_DOS_PARTITION is not set
57# CONFIG_SPL_EFI_PARTITION is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]58CONFIG_SPL_OF_CONTROL=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]59CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
60CONFIG_SPL_OF_PLATDATA=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]61CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]62CONFIG_REGMAP=y
63CONFIG_SPL_REGMAP=y
64CONFIG_SYSCON=y
65CONFIG_SPL_SYSCON=y
66# CONFIG_SPL_SIMPLE_BUS is not set
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]67# CONFIG_SPL_BLK is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]68CONFIG_CLK=y
69CONFIG_SPL_CLK=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]70CONFIG_ROCKCHIP_GPIO=y
71CONFIG_I2C_CROS_EC_TUNNEL=y
72CONFIG_SYS_I2C_ROCKCHIP=y
73CONFIG_I2C_MUX=y
74CONFIG_DM_KEYBOARD=y
75CONFIG_CROS_EC_KEYB=y
76CONFIG_CROS_EC=y
77CONFIG_CROS_EC_SPI=y
78CONFIG_PWRSEQ=y
Jaehoon Chunge711c972021-02-16 10:16:56 +0900[diff] [blame]79CONFIG_MMC_PWRSEQ=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]80# CONFIG_SPL_DM_MMC is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]81CONFIG_MMC_DW=y
82CONFIG_MMC_DW_ROCKCHIP=y
Miquel Raynal2e35dbb2019-10-03 19:50:05 +0200[diff] [blame]83CONFIG_MTD=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]84CONFIG_SF_DEFAULT_BUS=2
Urja Rannikko7a19eec2019-05-13 13:51:03 +0000[diff] [blame]85CONFIG_SPI_FLASH_GIGADEVICE=y
Alper Nebi Yasak1a1640d2023-07-21 11:46:00 +0300[diff] [blame]86CONFIG_SPI_FLASH_WINBOND=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]87CONFIG_PINCTRL=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]88CONFIG_PINCONF=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]89CONFIG_SPL_PINCTRL=y
Urja Rannikkoaa02ec02020-05-13 19:15:23 +0000[diff] [blame]90# CONFIG_SPL_PINCTRL_FULL is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]91CONFIG_DM_PMIC=y
92# CONFIG_SPL_PMIC_CHILDREN is not set
93CONFIG_PMIC_RK8XX=y
94CONFIG_DM_REGULATOR_FIXED=y
95CONFIG_REGULATOR_RK8XX=y
96CONFIG_PWM_ROCKCHIP=y
97CONFIG_RAM=y
98CONFIG_SPL_RAM=y
99CONFIG_DEBUG_UART_SHIFT=2
Tom Rinidc172ee2022-12-04 09:39:03 -0500[diff] [blame]100CONFIG_SYS_NS16550_MEM32=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]101CONFIG_ROCKCHIP_SERIAL=y
102CONFIG_ROCKCHIP_SPI=y
103CONFIG_SYSRESET=y
104CONFIG_USB=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]105# CONFIG_SPL_DM_USB is not set
106CONFIG_USB_DWC2=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]107CONFIG_ROCKCHIP_USB2_PHY=y
Simon Glass52cb5042022-10-18 07:46:31 -0600[diff] [blame]108CONFIG_VIDEO=y
Anatolij Gustschindba36702020-02-04 22:43:06 +0100[diff] [blame]109# CONFIG_VIDEO_BPP8 is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]110CONFIG_CONSOLE_TRUETYPE=y
111CONFIG_DISPLAY=y
112CONFIG_VIDEO_ROCKCHIP=y
113CONFIG_DISPLAY_ROCKCHIP_EDP=y
114CONFIG_DISPLAY_ROCKCHIP_HDMI=y
115# CONFIG_USE_PRIVATE_LIBGCC is not set
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]116CONFIG_SPL_TINY_MEMSET=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]117CONFIG_CMD_DHRYSTONE=y
118CONFIG_ERRNO_STR=y