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Chandan Nath4ba33452011-10-14 02:58:23 +00001/*
2 * clocks_am33xx.h
3 *
4 * AM33xx clock define
5 *
6 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef _CLOCKS_AM33XX_H_
20#define _CLOCKS_AM33XX_H_
21
Steve Sakoman772be792012-05-30 07:46:00 +000022#define OSC (V_OSCK/1000000)
Chandan Nath4ba33452011-10-14 02:58:23 +000023
24/* MAIN PLL Fdll = 550 MHZ, */
25#define MPUPLL_M 550
Steve Sakoman772be792012-05-30 07:46:00 +000026#define MPUPLL_N (OSC-1)
Chandan Nath4ba33452011-10-14 02:58:23 +000027#define MPUPLL_M2 1
28
29/* Core PLL Fdll = 1 GHZ, */
30#define COREPLL_M 1000
Steve Sakoman772be792012-05-30 07:46:00 +000031#define COREPLL_N (OSC-1)
Chandan Nath4ba33452011-10-14 02:58:23 +000032
33#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
34#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
35#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
36
37/*
38 * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
39 * frequency needs to be set to 960 MHZ. Hence,
40 * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
41 */
42#define PERPLL_M 960
Steve Sakoman772be792012-05-30 07:46:00 +000043#define PERPLL_N (OSC-1)
Chandan Nath4ba33452011-10-14 02:58:23 +000044#define PERPLL_M2 5
45
46/* DDR Freq is 266 MHZ for now */
47/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
48#define DDRPLL_M 266
Steve Sakoman772be792012-05-30 07:46:00 +000049#define DDRPLL_N (OSC-1)
Chandan Nath4ba33452011-10-14 02:58:23 +000050#define DDRPLL_M2 1
51
52extern void pll_init(void);
53extern void enable_emif_clocks(void);
54
55#endif /* endif _CLOCKS_AM33XX_H_ */