blob: 68548b00d94864aaabd3efc323bb03e46a410146 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
4 *
5 * (C) Copyright 2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00009 */
10
11#ifndef _PCI_H
12#define _PCI_H
13
Minghuan Lianc5bc6aa2015-07-10 11:35:08 +080014#define PCI_CFG_SPACE_SIZE 256
15#define PCI_CFG_SPACE_EXP_SIZE 4096
16
wdenkc6097192002-11-03 00:24:07 +000017/*
18 * Under PCI, each device has 256 bytes of configuration address space,
19 * of which the first 64 bytes are standardized as follows:
20 */
21#define PCI_VENDOR_ID 0x00 /* 16 bits */
22#define PCI_DEVICE_ID 0x02 /* 16 bits */
23#define PCI_COMMAND 0x04 /* 16 bits */
24#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
25#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
26#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
27#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
28#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
29#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
30#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
31#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
32#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
33#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
34
35#define PCI_STATUS 0x06 /* 16 bits */
36#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
37#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
38#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
39#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
40#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
41#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
42#define PCI_STATUS_DEVSEL_FAST 0x000
43#define PCI_STATUS_DEVSEL_MEDIUM 0x200
44#define PCI_STATUS_DEVSEL_SLOW 0x400
45#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
46#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
47#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
48#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
49#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
50
51#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
52 revision */
53#define PCI_REVISION_ID 0x08 /* Revision ID */
54#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
55#define PCI_CLASS_DEVICE 0x0a /* Device class */
56#define PCI_CLASS_CODE 0x0b /* Device class code */
Bill Richardsoneece4322012-10-20 11:44:34 +000057#define PCI_CLASS_CODE_TOO_OLD 0x00
58#define PCI_CLASS_CODE_STORAGE 0x01
59#define PCI_CLASS_CODE_NETWORK 0x02
60#define PCI_CLASS_CODE_DISPLAY 0x03
61#define PCI_CLASS_CODE_MULTIMEDIA 0x04
62#define PCI_CLASS_CODE_MEMORY 0x05
63#define PCI_CLASS_CODE_BRIDGE 0x06
64#define PCI_CLASS_CODE_COMM 0x07
65#define PCI_CLASS_CODE_PERIPHERAL 0x08
66#define PCI_CLASS_CODE_INPUT 0x09
67#define PCI_CLASS_CODE_DOCKING 0x0A
68#define PCI_CLASS_CODE_PROCESSOR 0x0B
69#define PCI_CLASS_CODE_SERIAL 0x0C
70#define PCI_CLASS_CODE_WIRELESS 0x0D
71#define PCI_CLASS_CODE_I2O 0x0E
72#define PCI_CLASS_CODE_SATELLITE 0x0F
73#define PCI_CLASS_CODE_CRYPTO 0x10
74#define PCI_CLASS_CODE_DATA 0x11
75/* Base Class 0x12 - 0xFE is reserved */
76#define PCI_CLASS_CODE_OTHER 0xFF
77
wdenkc6097192002-11-03 00:24:07 +000078#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
Bill Richardsoneece4322012-10-20 11:44:34 +000079#define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00
80#define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01
81#define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00
82#define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01
83#define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02
84#define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03
85#define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04
86#define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05
87#define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06
88#define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07
89#define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80
90#define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00
91#define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01
92#define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02
93#define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03
94#define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04
95#define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05
96#define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06
97#define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80
98#define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00
99#define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01
100#define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02
101#define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80
102#define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00
103#define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01
104#define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02
105#define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80
106#define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00
107#define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01
108#define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80
109#define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00
110#define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01
111#define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02
112#define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03
113#define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04
114#define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05
115#define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06
116#define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07
117#define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08
118#define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09
119#define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A
120#define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80
121#define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00
122#define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01
123#define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02
124#define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03
125#define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04
126#define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05
127#define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80
128#define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00
129#define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01
130#define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02
131#define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03
132#define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04
133#define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05
134#define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80
135#define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00
136#define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01
137#define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02
138#define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03
139#define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04
140#define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80
141#define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00
142#define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80
143#define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00
144#define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01
145#define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02
146#define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10
147#define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20
148#define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30
149#define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40
150#define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00
151#define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01
152#define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02
153#define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03
154#define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04
155#define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05
156#define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06
157#define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07
158#define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08
159#define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09
160#define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00
161#define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01
162#define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10
163#define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11
164#define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12
165#define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20
166#define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21
167#define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80
168#define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00
169#define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01
170#define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02
171#define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03
172#define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04
173#define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00
174#define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
175#define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80
176#define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00
177#define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01
178#define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10
179#define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20
180#define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80
wdenkc6097192002-11-03 00:24:07 +0000181
182#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
183#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
184#define PCI_HEADER_TYPE 0x0e /* 8 bits */
185#define PCI_HEADER_TYPE_NORMAL 0
186#define PCI_HEADER_TYPE_BRIDGE 1
187#define PCI_HEADER_TYPE_CARDBUS 2
188
189#define PCI_BIST 0x0f /* 8 bits */
190#define PCI_BIST_CODE_MASK 0x0f /* Return result */
191#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
192#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
193
194/*
195 * Base addresses specify locations in memory or I/O space.
196 * Decoded size can be determined by writing a value of
197 * 0xffffffff to the register, and reading it back. Only
198 * 1 bits are decoded.
199 */
200#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
201#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
202#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
203#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
204#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
205#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
206#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
207#define PCI_BASE_ADDRESS_SPACE_IO 0x01
208#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
209#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
210#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
211#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
212#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
213#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
Kumar Galaad714f52008-10-21 08:36:08 -0500214#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
215#define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
wdenkc6097192002-11-03 00:24:07 +0000216/* bit 1 is reserved if address_space = 1 */
217
218/* Header type 0 (normal devices) */
219#define PCI_CARDBUS_CIS 0x28
220#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
221#define PCI_SUBSYSTEM_ID 0x2e
222#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
223#define PCI_ROM_ADDRESS_ENABLE 0x01
Kumar Galaad714f52008-10-21 08:36:08 -0500224#define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
wdenkc6097192002-11-03 00:24:07 +0000225
226#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
227
228/* 0x35-0x3b are reserved */
229#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
230#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
231#define PCI_MIN_GNT 0x3e /* 8 bits */
232#define PCI_MAX_LAT 0x3f /* 8 bits */
233
Simon Glass84f57332015-07-27 15:47:17 -0600234#define PCI_INTERRUPT_LINE_DISABLE 0xff
235
wdenkc6097192002-11-03 00:24:07 +0000236/* Header type 1 (PCI-to-PCI bridges) */
237#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
238#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
239#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
240#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
241#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
242#define PCI_IO_LIMIT 0x1d
243#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
244#define PCI_IO_RANGE_TYPE_16 0x00
245#define PCI_IO_RANGE_TYPE_32 0x01
246#define PCI_IO_RANGE_MASK ~0x0f
247#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
248#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
249#define PCI_MEMORY_LIMIT 0x22
250#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
251#define PCI_MEMORY_RANGE_MASK ~0x0f
252#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
253#define PCI_PREF_MEMORY_LIMIT 0x26
254#define PCI_PREF_RANGE_TYPE_MASK 0x0f
255#define PCI_PREF_RANGE_TYPE_32 0x00
256#define PCI_PREF_RANGE_TYPE_64 0x01
257#define PCI_PREF_RANGE_MASK ~0x0f
258#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
259#define PCI_PREF_LIMIT_UPPER32 0x2c
260#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
261#define PCI_IO_LIMIT_UPPER16 0x32
262/* 0x34 same as for htype 0 */
263/* 0x35-0x3b is reserved */
264#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
265/* 0x3c-0x3d are same as for htype 0 */
266#define PCI_BRIDGE_CONTROL 0x3e
267#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
268#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
269#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
270#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
271#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
272#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
273#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
274
Stefan Roese326c9712005-08-01 16:41:48 +0200275/* From 440ep */
276#define PCI_ERREN 0x48 /* Error Enable */
277#define PCI_ERRSTS 0x49 /* Error Status */
278#define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */
279#define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */
280#define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */
281#define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */
282#define PCI_CAPID 0x58 /* Capability Identifier */
283#define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */
284#define PCI_PMC 0x5A /* Power Management Capabilities */
285#define PCI_PMCSR 0x5C /* Power Management Control Status */
286#define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */
287#define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */
288#define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */
289
wdenkc6097192002-11-03 00:24:07 +0000290/* Header type 2 (CardBus bridges) */
291#define PCI_CB_CAPABILITY_LIST 0x14
292/* 0x15 reserved */
293#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
294#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
295#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
296#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
297#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
298#define PCI_CB_MEMORY_BASE_0 0x1c
299#define PCI_CB_MEMORY_LIMIT_0 0x20
300#define PCI_CB_MEMORY_BASE_1 0x24
301#define PCI_CB_MEMORY_LIMIT_1 0x28
302#define PCI_CB_IO_BASE_0 0x2c
303#define PCI_CB_IO_BASE_0_HI 0x2e
304#define PCI_CB_IO_LIMIT_0 0x30
305#define PCI_CB_IO_LIMIT_0_HI 0x32
306#define PCI_CB_IO_BASE_1 0x34
307#define PCI_CB_IO_BASE_1_HI 0x36
308#define PCI_CB_IO_LIMIT_1 0x38
309#define PCI_CB_IO_LIMIT_1_HI 0x3a
310#define PCI_CB_IO_RANGE_MASK ~0x03
311/* 0x3c-0x3d are same as for htype 0 */
312#define PCI_CB_BRIDGE_CONTROL 0x3e
313#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
314#define PCI_CB_BRIDGE_CTL_SERR 0x02
315#define PCI_CB_BRIDGE_CTL_ISA 0x04
316#define PCI_CB_BRIDGE_CTL_VGA 0x08
317#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
318#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
319#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
320#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
321#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
322#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
323#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
324#define PCI_CB_SUBSYSTEM_ID 0x42
325#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
326/* 0x48-0x7f reserved */
327
328/* Capability lists */
329
330#define PCI_CAP_LIST_ID 0 /* Capability ID */
331#define PCI_CAP_ID_PM 0x01 /* Power Management */
332#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
333#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
334#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
335#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
336#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
Kumar Galaa0a5dbd2009-08-05 07:49:27 -0500337#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
wdenkc6097192002-11-03 00:24:07 +0000338#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
339#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
340#define PCI_CAP_SIZEOF 4
341
342/* Power Management Registers */
343
344#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
345#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
346#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
347#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
348#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
349#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
350#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
351#define PCI_PM_CTRL 4 /* PM control and status register */
352#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
353#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
354#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
355#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
356#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
357#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
358#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
359#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
360#define PCI_PM_DATA_REGISTER 7 /* (??) */
361#define PCI_PM_SIZEOF 8
362
363/* AGP registers */
364
365#define PCI_AGP_VERSION 2 /* BCD version number */
366#define PCI_AGP_RFU 3 /* Rest of capability flags */
367#define PCI_AGP_STATUS 4 /* Status register */
368#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
369#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
370#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
371#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
372#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
373#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
374#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
375#define PCI_AGP_COMMAND 8 /* Control register */
376#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
377#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
378#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
379#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
380#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
381#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
382#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
383#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
384#define PCI_AGP_SIZEOF 12
385
Matthew McClintock3fc12c52006-06-28 10:44:49 -0500386/* PCI-X registers */
387
388#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
389#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
390#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
391#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
392#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
393
394
wdenkc6097192002-11-03 00:24:07 +0000395/* Slot Identification */
396
397#define PCI_SID_ESR 2 /* Expansion Slot Register */
398#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
399#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
400#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
401
402/* Message Signalled Interrupts registers */
403
404#define PCI_MSI_FLAGS 2 /* Various flags */
405#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
406#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
407#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
408#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
409#define PCI_MSI_RFU 3 /* Rest of capability flags */
410#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
411#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
412#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
413#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
414
415#define PCI_MAX_PCI_DEVICES 32
416#define PCI_MAX_PCI_FUNCTIONS 8
417
Zhao Qiang5d39f742013-10-12 13:46:33 +0800418#define PCI_FIND_CAP_TTL 0x48
419#define CAP_START_POS 0x40
420
Minghuan Lianc5bc6aa2015-07-10 11:35:08 +0800421/* Extended Capabilities (PCI-X 2.0 and Express) */
422#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
423#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
424#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
425
426#define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
427#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */
428#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
429#define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
430#define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
431#define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
432#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
433#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
434#define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
435#define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
436#define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
437#define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
438#define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
439#define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
440#define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */
441#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
442#define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
443#define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
444#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
445#define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */
446#define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */
447#define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */
448#define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */
449#define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
450#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
451#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
452#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
453
wdenkc6097192002-11-03 00:24:07 +0000454/* Include the ID list */
455
456#include <pci_ids.h>
457
Paul Burton162116e2013-11-08 11:18:47 +0000458#ifndef __ASSEMBLY__
459
Kumar Galaad714f52008-10-21 08:36:08 -0500460#ifdef CONFIG_SYS_PCI_64BIT
461typedef u64 pci_addr_t;
462typedef u64 pci_size_t;
463#else
464typedef u32 pci_addr_t;
465typedef u32 pci_size_t;
466#endif
467
wdenkc6097192002-11-03 00:24:07 +0000468struct pci_region {
Kumar Galaad714f52008-10-21 08:36:08 -0500469 pci_addr_t bus_start; /* Start on the bus */
470 phys_addr_t phys_start; /* Start in physical address space */
471 pci_size_t size; /* Size */
472 unsigned long flags; /* Resource flags */
wdenkc6097192002-11-03 00:24:07 +0000473
Kumar Galaad714f52008-10-21 08:36:08 -0500474 pci_addr_t bus_lower;
wdenkc6097192002-11-03 00:24:07 +0000475};
476
477#define PCI_REGION_MEM 0x00000000 /* PCI memory space */
478#define PCI_REGION_IO 0x00000001 /* PCI IO space */
479#define PCI_REGION_TYPE 0x00000001
Kumar Galae5ce4202006-01-11 13:24:15 -0600480#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
wdenkc6097192002-11-03 00:24:07 +0000481
Kumar Galaefa1f1d2009-02-06 09:49:31 -0600482#define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */
wdenkc6097192002-11-03 00:24:07 +0000483#define PCI_REGION_RO 0x00000200 /* Read-only memory */
484
Simon Glass64f11d02013-06-11 11:14:33 -0700485static inline void pci_set_region(struct pci_region *reg,
Kumar Galaad714f52008-10-21 08:36:08 -0500486 pci_addr_t bus_start,
Becky Bruce0a628572008-05-07 13:24:57 -0500487 phys_addr_t phys_start,
Kumar Galaad714f52008-10-21 08:36:08 -0500488 pci_size_t size,
wdenkc6097192002-11-03 00:24:07 +0000489 unsigned long flags) {
490 reg->bus_start = bus_start;
491 reg->phys_start = phys_start;
492 reg->size = size;
493 reg->flags = flags;
494}
495
496typedef int pci_dev_t;
497
Simon Glassb94dc892015-03-05 12:25:25 -0700498#define PCI_BUS(d) (((d) >> 16) & 0xff)
499#define PCI_DEV(d) (((d) >> 11) & 0x1f)
500#define PCI_FUNC(d) (((d) >> 8) & 0x7)
501#define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8)
502#define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)
503#define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))
504#define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))
505#define PCI_VENDEV(v, d) (((v) << 16) | (d))
506#define PCI_ANY_ID (~0)
wdenkc6097192002-11-03 00:24:07 +0000507
508struct pci_device_id {
Simon Glass318d71c2015-07-06 16:47:44 -0600509 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
510 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
511 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
512 unsigned long driver_data; /* Data private to the driver */
wdenkc6097192002-11-03 00:24:07 +0000513};
514
515struct pci_controller;
516
517struct pci_config_table {
518 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
519 unsigned int class; /* Class ID, or PCI_ANY_ID */
520 unsigned int bus; /* Bus number, or PCI_ANY_ID */
521 unsigned int dev; /* Device number, or PCI_ANY_ID */
522 unsigned int func; /* Function number, or PCI_ANY_ID */
523
524 void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
525 struct pci_config_table *);
526 unsigned long priv[3];
527};
528
Wolfgang Denk3d7f5e02006-03-12 16:54:11 +0100529extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
530 struct pci_config_table *);
wdenkc6097192002-11-03 00:24:07 +0000531extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
532 struct pci_config_table *);
533
534#define MAX_PCI_REGIONS 7
535
Anton Vorontsov1a8206c2009-01-08 04:26:12 +0300536#define INDIRECT_TYPE_NO_PCIE_LINK 1
537
wdenkc6097192002-11-03 00:24:07 +0000538/*
539 * Structure of a PCI controller (host bridge)
Simon Glassc19e4422015-11-26 19:51:21 -0700540 *
541 * With driver model this is dev_get_uclass_priv(bus)
wdenkc6097192002-11-03 00:24:07 +0000542 */
543struct pci_controller {
Simon Glassb94dc892015-03-05 12:25:25 -0700544#ifdef CONFIG_DM_PCI
545 struct udevice *bus;
546 struct udevice *ctlr;
547#else
wdenkc6097192002-11-03 00:24:07 +0000548 struct pci_controller *next;
Simon Glassb94dc892015-03-05 12:25:25 -0700549#endif
wdenkc6097192002-11-03 00:24:07 +0000550
551 int first_busno;
552 int last_busno;
553
554 volatile unsigned int *cfg_addr;
555 volatile unsigned char *cfg_data;
556
Anton Vorontsov1a8206c2009-01-08 04:26:12 +0300557 int indirect_type;
558
Simon Glassd82fbe92015-06-07 08:50:40 -0600559 /*
560 * TODO(sjg@chromium.org): With driver model we use struct
561 * pci_controller for both the controller and any bridge devices
562 * attached to it. But there is only one region list and it is in the
563 * top-level controller.
564 *
565 * This could be changed so that struct pci_controller is only used
566 * for PCI controllers and a separate UCLASS (or perhaps
567 * UCLASS_PCI_GENERIC) is used for bridges.
568 */
wdenkc6097192002-11-03 00:24:07 +0000569 struct pci_region regions[MAX_PCI_REGIONS];
570 int region_count;
571
572 struct pci_config_table *config_table;
573
574 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
Simon Glassb94dc892015-03-05 12:25:25 -0700575#ifndef CONFIG_DM_PCI
wdenkc6097192002-11-03 00:24:07 +0000576 /* Low-level architecture-dependent routines */
577 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
578 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
579 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
580 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
581 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
582 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
Simon Glassb94dc892015-03-05 12:25:25 -0700583#endif
wdenkc6097192002-11-03 00:24:07 +0000584
585 /* Used by auto config */
Kumar Galae5ce4202006-01-11 13:24:15 -0600586 struct pci_region *pci_mem, *pci_io, *pci_prefetch;
wdenkc6097192002-11-03 00:24:07 +0000587
588 /* Used by ppc405 autoconfig*/
589 struct pci_region *pci_fb;
Simon Glassb94dc892015-03-05 12:25:25 -0700590#ifndef CONFIG_DM_PCI
wdenk452cfd62002-11-19 11:04:11 +0000591 int current_busno;
Leo Liue87bc032011-01-19 19:50:47 +0800592
593 void *priv_data;
Simon Glassb94dc892015-03-05 12:25:25 -0700594#endif
wdenkc6097192002-11-03 00:24:07 +0000595};
596
Simon Glassb94dc892015-03-05 12:25:25 -0700597#ifndef CONFIG_DM_PCI
Simon Glass64f11d02013-06-11 11:14:33 -0700598static inline void pci_set_ops(struct pci_controller *hose,
wdenkc6097192002-11-03 00:24:07 +0000599 int (*read_byte)(struct pci_controller*,
600 pci_dev_t, int where, u8 *),
601 int (*read_word)(struct pci_controller*,
602 pci_dev_t, int where, u16 *),
603 int (*read_dword)(struct pci_controller*,
604 pci_dev_t, int where, u32 *),
605 int (*write_byte)(struct pci_controller*,
606 pci_dev_t, int where, u8),
607 int (*write_word)(struct pci_controller*,
608 pci_dev_t, int where, u16),
609 int (*write_dword)(struct pci_controller*,
610 pci_dev_t, int where, u32)) {
611 hose->read_byte = read_byte;
612 hose->read_word = read_word;
613 hose->read_dword = read_dword;
614 hose->write_byte = write_byte;
615 hose->write_word = write_word;
616 hose->write_dword = write_dword;
617}
Simon Glassb94dc892015-03-05 12:25:25 -0700618#endif
wdenkc6097192002-11-03 00:24:07 +0000619
Gabor Juhosb4458732013-05-30 07:06:12 +0000620#ifdef CONFIG_PCI_INDIRECT_BRIDGE
wdenkc6097192002-11-03 00:24:07 +0000621extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
Gabor Juhosb4458732013-05-30 07:06:12 +0000622#endif
wdenkc6097192002-11-03 00:24:07 +0000623
Simon Glassb967ca82015-11-29 13:18:05 -0700624#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
Becky Bruce0a628572008-05-07 13:24:57 -0500625extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
Kumar Galaad714f52008-10-21 08:36:08 -0500626 pci_addr_t addr, unsigned long flags);
627extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
628 phys_addr_t addr, unsigned long flags);
wdenkc6097192002-11-03 00:24:07 +0000629
630#define pci_phys_to_bus(dev, addr, flags) \
631 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
632#define pci_bus_to_phys(dev, addr, flags) \
633 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
634
Becky Bruce0709bfc2009-02-03 18:10:50 -0600635#define pci_virt_to_bus(dev, addr, flags) \
636 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
637 (virt_to_phys(addr)), (flags))
638#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
639 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
640 (addr), (flags)), \
641 (len), (map_flags))
642
643#define pci_phys_to_mem(dev, addr) \
644 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
645#define pci_mem_to_phys(dev, addr) \
646 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
647#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
648#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
649
650#define pci_virt_to_mem(dev, addr) \
651 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
652#define pci_mem_to_virt(dev, addr, len, map_flags) \
653 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
654#define pci_virt_to_io(dev, addr) \
655 pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
656#define pci_io_to_virt(dev, addr, len, map_flags) \
657 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
wdenkc6097192002-11-03 00:24:07 +0000658
Simon Glassf2b223f2015-08-22 15:58:55 -0600659/* For driver model these are defined in macros in pci_compat.c */
wdenkc6097192002-11-03 00:24:07 +0000660extern int pci_hose_read_config_byte(struct pci_controller *hose,
661 pci_dev_t dev, int where, u8 *val);
662extern int pci_hose_read_config_word(struct pci_controller *hose,
663 pci_dev_t dev, int where, u16 *val);
664extern int pci_hose_read_config_dword(struct pci_controller *hose,
665 pci_dev_t dev, int where, u32 *val);
666extern int pci_hose_write_config_byte(struct pci_controller *hose,
667 pci_dev_t dev, int where, u8 val);
668extern int pci_hose_write_config_word(struct pci_controller *hose,
669 pci_dev_t dev, int where, u16 val);
670extern int pci_hose_write_config_dword(struct pci_controller *hose,
671 pci_dev_t dev, int where, u32 val);
Simon Glasseca7b0d2015-11-26 19:51:30 -0700672#endif
wdenkc6097192002-11-03 00:24:07 +0000673
Simon Glassb94dc892015-03-05 12:25:25 -0700674#ifndef CONFIG_DM_PCI
wdenkc6097192002-11-03 00:24:07 +0000675extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
676extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
677extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
678extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
679extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
680extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
Simon Glassb94dc892015-03-05 12:25:25 -0700681#endif
wdenkc6097192002-11-03 00:24:07 +0000682
Simon Glasseca7b0d2015-11-26 19:51:30 -0700683void pciauto_region_init(struct pci_region *res);
684void pciauto_region_align(struct pci_region *res, pci_size_t size);
685void pciauto_config_init(struct pci_controller *hose);
686int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
687 pci_addr_t *bar);
688
689#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
wdenkc6097192002-11-03 00:24:07 +0000690extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
691 pci_dev_t dev, int where, u8 *val);
692extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
693 pci_dev_t dev, int where, u16 *val);
694extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
695 pci_dev_t dev, int where, u8 val);
696extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
697 pci_dev_t dev, int where, u16 val);
698
Becky Bruce0709bfc2009-02-03 18:10:50 -0600699extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
wdenkc6097192002-11-03 00:24:07 +0000700extern void pci_register_hose(struct pci_controller* hose);
701extern struct pci_controller* pci_bus_to_hose(int bus);
Kumar Galadb943ed2010-12-17 05:57:25 -0600702extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
wdenkc6097192002-11-03 00:24:07 +0000703
Thierry Reding699b6d32014-11-12 18:26:49 -0700704extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
wdenkc6097192002-11-03 00:24:07 +0000705extern int pci_hose_scan(struct pci_controller *hose);
706extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
707
wdenkc6097192002-11-03 00:24:07 +0000708extern void pciauto_setup_device(struct pci_controller *hose,
709 pci_dev_t dev, int bars_num,
710 struct pci_region *mem,
Kumar Galae5ce4202006-01-11 13:24:15 -0600711 struct pci_region *prefetch,
wdenkc6097192002-11-03 00:24:07 +0000712 struct pci_region *io);
Linus Walleij00532722012-03-25 12:13:15 +0000713extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
714 pci_dev_t dev, int sub_bus);
715extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
716 pci_dev_t dev, int sub_bus);
Linus Walleij00532722012-03-25 12:13:15 +0000717extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
wdenkc6097192002-11-03 00:24:07 +0000718
719extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
720extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
Simon Glass62034ff2015-01-27 22:13:27 -0700721pci_dev_t pci_find_class(unsigned int find_class, int index);
wdenkc6097192002-11-03 00:24:07 +0000722
723extern int pci_hose_config_device(struct pci_controller *hose,
724 pci_dev_t dev,
725 unsigned long io,
Kumar Galaad714f52008-10-21 08:36:08 -0500726 pci_addr_t mem,
wdenkc6097192002-11-03 00:24:07 +0000727 unsigned long command);
728
Zhao Qiang5d39f742013-10-12 13:46:33 +0800729extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
730 int cap);
731extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
732 u8 hdr_type);
733extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
734 int cap);
735
Minghuan Lianc5bc6aa2015-07-10 11:35:08 +0800736int pci_find_next_ext_capability(struct pci_controller *hose,
737 pci_dev_t dev, int start, int cap);
738int pci_hose_find_ext_capability(struct pci_controller *hose,
739 pci_dev_t dev, int cap);
740
Tim Harvey231c0762014-08-07 22:49:56 -0700741#ifdef CONFIG_PCI_FIXUP_DEV
742extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
743 unsigned short vendor,
744 unsigned short device,
745 unsigned short class);
746#endif
Simon Glasseca7b0d2015-11-26 19:51:30 -0700747#endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */
Tim Harvey231c0762014-08-07 22:49:56 -0700748
Peter Tyser22ccb7f2010-10-29 17:59:27 -0500749const char * pci_class_str(u8 class);
Anton Vorontsov597b8c42009-02-19 18:20:41 +0300750int pci_last_busno(void);
751
Jon Loeligerc934adb2006-10-19 11:33:52 -0500752#ifdef CONFIG_MPC85xx
753extern void pci_mpc85xx_init (struct pci_controller *hose);
754#endif
Paul Burton162116e2013-11-08 11:18:47 +0000755
Simon Glasseca7b0d2015-11-26 19:51:30 -0700756#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
Simon Glass6ac5af42014-11-14 18:18:30 -0700757/**
758 * pci_write_bar32() - Write the address of a BAR including control bits
759 *
Simon Glasse2b6b562016-01-18 20:19:15 -0700760 * This writes a raw address (with control bits) to a bar. This can be used
761 * with devices which require hard-coded addresses, not part of the normal
762 * PCI enumeration process.
Simon Glass6ac5af42014-11-14 18:18:30 -0700763 *
764 * @hose: PCI hose to use
765 * @dev: PCI device to update
766 * @barnum: BAR number (0-5)
767 * @addr: BAR address with control bits
768 */
769void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
Simon Glasse2b6b562016-01-18 20:19:15 -0700770 u32 addr);
Simon Glass6ac5af42014-11-14 18:18:30 -0700771
772/**
773 * pci_read_bar32() - read the address of a bar
774 *
775 * @hose: PCI hose to use
776 * @dev: PCI device to inspect
777 * @barnum: BAR number (0-5)
778 * @return address of the bar, masking out any control bits
779 * */
780u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
781
Simon Glass1c1695b2015-01-14 21:37:04 -0700782/**
Simon Glass75532d82015-03-05 12:25:24 -0700783 * pci_hose_find_devices() - Find devices by vendor/device ID
784 *
785 * @hose: PCI hose to search
786 * @busnum: Bus number to search
787 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
788 * @indexp: Pointer to device index to find. To find the first matching
789 * device, pass 0; to find the second, pass 1, etc. This
790 * parameter is decremented for each non-matching device so
791 * can be called repeatedly.
792 */
793pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
794 struct pci_device_id *ids, int *indexp);
Simon Glasseca7b0d2015-11-26 19:51:30 -0700795#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
Simon Glass75532d82015-03-05 12:25:24 -0700796
Simon Glassb94dc892015-03-05 12:25:25 -0700797/* Access sizes for PCI reads and writes */
798enum pci_size_t {
799 PCI_SIZE_8,
800 PCI_SIZE_16,
801 PCI_SIZE_32,
802};
803
804struct udevice;
805
806#ifdef CONFIG_DM_PCI
807/**
808 * struct pci_child_platdata - information stored about each PCI device
809 *
810 * Every device on a PCI bus has this per-child data.
811 *
Simon Glassde44acf2015-09-28 23:32:01 -0600812 * It can be accessed using dev_get_parent_priv(dev) if dev->parent is a
Simon Glassb94dc892015-03-05 12:25:25 -0700813 * PCI bus (i.e. UCLASS_PCI)
814 *
815 * @devfn: Encoded device and function index - see PCI_DEVFN()
816 * @vendor: PCI vendor ID (see pci_ids.h)
817 * @device: PCI device ID (see pci_ids.h)
818 * @class: PCI class, 3 bytes: (base, sub, prog-if)
819 */
820struct pci_child_platdata {
821 int devfn;
822 unsigned short vendor;
823 unsigned short device;
824 unsigned int class;
825};
826
827/* PCI bus operations */
828struct dm_pci_ops {
829 /**
830 * read_config() - Read a PCI configuration value
831 *
832 * PCI buses must support reading and writing configuration values
833 * so that the bus can be scanned and its devices configured.
834 *
835 * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always.
836 * If bridges exist it is possible to use the top-level bus to
837 * access a sub-bus. In that case @bus will be the top-level bus
838 * and PCI_BUS(bdf) will be a different (higher) value
839 *
840 * @bus: Bus to read from
841 * @bdf: Bus, device and function to read
842 * @offset: Byte offset within the device's configuration space
843 * @valuep: Place to put the returned value
844 * @size: Access size
845 * @return 0 if OK, -ve on error
846 */
847 int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
848 ulong *valuep, enum pci_size_t size);
849 /**
850 * write_config() - Write a PCI configuration value
851 *
852 * @bus: Bus to write to
853 * @bdf: Bus, device and function to write
854 * @offset: Byte offset within the device's configuration space
855 * @value: Value to write
856 * @size: Access size
857 * @return 0 if OK, -ve on error
858 */
859 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
860 ulong value, enum pci_size_t size);
861};
862
863/* Get access to a PCI bus' operations */
864#define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
865
866/**
Simon Glasseaa14892015-11-29 13:17:47 -0700867 * dm_pci_get_bdf() - Get the BDF value for a device
Simon Glassc9118d42015-07-06 16:47:46 -0600868 *
869 * @dev: Device to check
870 * @return bus/device/function value (see PCI_BDF())
871 */
Simon Glasseaa14892015-11-29 13:17:47 -0700872pci_dev_t dm_pci_get_bdf(struct udevice *dev);
Simon Glassc9118d42015-07-06 16:47:46 -0600873
874/**
Simon Glassb94dc892015-03-05 12:25:25 -0700875 * pci_bind_bus_devices() - scan a PCI bus and bind devices
876 *
877 * Scan a PCI bus looking for devices. Bind each one that is found. If
878 * devices are already bound that match the scanned devices, just update the
879 * child data so that the device can be used correctly (this happens when
880 * the device tree describes devices we expect to see on the bus).
881 *
882 * Devices that are bound in this way will use a generic PCI driver which
883 * does nothing. The device can still be accessed but will not provide any
884 * driver interface.
885 *
886 * @bus: Bus containing devices to bind
887 * @return 0 if OK, -ve on error
888 */
889int pci_bind_bus_devices(struct udevice *bus);
890
891/**
892 * pci_auto_config_devices() - configure bus devices ready for use
893 *
894 * This works through all devices on a bus by scanning the driver model
895 * data structures (normally these have been set up by pci_bind_bus_devices()
896 * earlier).
897 *
898 * Space is allocated for each PCI base address register (BAR) so that the
899 * devices are mapped into memory and I/O space ready for use.
900 *
901 * @bus: Bus containing devices to bind
902 * @return 0 if OK, -ve on error
903 */
904int pci_auto_config_devices(struct udevice *bus);
905
906/**
Simon Glass84283d52015-11-29 13:17:48 -0700907 * dm_pci_bus_find_bdf() - Find a device given its PCI bus address
Simon Glassb94dc892015-03-05 12:25:25 -0700908 *
909 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
910 * @devp: Returns the device for this address, if found
911 * @return 0 if OK, -ENODEV if not found
912 */
Simon Glass84283d52015-11-29 13:17:48 -0700913int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
Simon Glassb94dc892015-03-05 12:25:25 -0700914
915/**
916 * pci_bus_find_devfn() - Find a device on a bus
917 *
918 * @find_devfn: PCI device address (device and function only)
919 * @devp: Returns the device for this address, if found
920 * @return 0 if OK, -ENODEV if not found
921 */
922int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
923 struct udevice **devp);
924
925/**
Simon Glass04c8b6a2015-08-10 07:05:04 -0600926 * pci_find_first_device() - return the first available PCI device
927 *
928 * This function and pci_find_first_device() allow iteration through all
929 * available PCI devices on all buses. Assuming there are any, this will
930 * return the first one.
931 *
932 * @devp: Set to the first available device, or NULL if no more are left
933 * or we got an error
934 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
935 */
936int pci_find_first_device(struct udevice **devp);
937
938/**
939 * pci_find_next_device() - return the next available PCI device
940 *
941 * Finds the next available PCI device after the one supplied, or sets @devp
942 * to NULL if there are no more.
943 *
944 * @devp: On entry, the last device returned. Set to the next available
945 * device, or NULL if no more are left or we got an error
946 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
947 */
948int pci_find_next_device(struct udevice **devp);
949
950/**
Simon Glassb94dc892015-03-05 12:25:25 -0700951 * pci_get_ff() - Returns a mask for the given access size
952 *
953 * @size: Access size
954 * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for
955 * PCI_SIZE_32
956 */
957int pci_get_ff(enum pci_size_t size);
958
959/**
960 * pci_bus_find_devices () - Find devices on a bus
961 *
962 * @bus: Bus to search
963 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
964 * @indexp: Pointer to device index to find. To find the first matching
965 * device, pass 0; to find the second, pass 1, etc. This
966 * parameter is decremented for each non-matching device so
967 * can be called repeatedly.
968 * @devp: Returns matching device if found
969 * @return 0 if found, -ENODEV if not
970 */
971int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
972 int *indexp, struct udevice **devp);
973
974/**
975 * pci_find_device_id() - Find a device on any bus
976 *
977 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
978 * @index: Index number of device to find, 0 for the first match, 1 for
979 * the second, etc.
980 * @devp: Returns matching device if found
981 * @return 0 if found, -ENODEV if not
982 */
983int pci_find_device_id(struct pci_device_id *ids, int index,
984 struct udevice **devp);
985
986/**
987 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices
988 *
989 * This probes the given bus which causes it to be scanned for devices. The
990 * devices will be bound but not probed.
991 *
992 * @hose specifies the PCI hose that will be used for the scan. This is
993 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is
994 * in @bdf, and is a subordinate bus reachable from @hose.
995 *
996 * @hose: PCI hose to scan
997 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)
998 * @return 0 if OK, -ve on error
999 */
Simon Glass37a3f94b2015-11-29 13:17:49 -07001000int dm_pci_hose_probe_bus(struct udevice *bus);
Simon Glassb94dc892015-03-05 12:25:25 -07001001
1002/**
1003 * pci_bus_read_config() - Read a configuration value from a device
1004 *
1005 * TODO(sjg@chromium.org): We should be able to pass just a device and have
1006 * it do the right thing. It would be good to have that function also.
1007 *
1008 * @bus: Bus to read from
1009 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1010 * @valuep: Place to put the returned value
1011 * @size: Access size
1012 * @return 0 if OK, -ve on error
1013 */
1014int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
1015 unsigned long *valuep, enum pci_size_t size);
1016
1017/**
1018 * pci_bus_write_config() - Write a configuration value to a device
1019 *
1020 * @bus: Bus to write from
1021 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1022 * @value: Value to write
1023 * @size: Access size
1024 * @return 0 if OK, -ve on error
1025 */
1026int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
1027 unsigned long value, enum pci_size_t size);
1028
Simon Glass94ef2422015-08-10 07:05:03 -06001029/**
1030 * Driver model PCI config access functions. Use these in preference to others
1031 * when you have a valid device
1032 */
1033int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
1034 enum pci_size_t size);
1035
1036int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep);
1037int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep);
1038int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep);
1039
1040int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
1041 enum pci_size_t size);
1042
1043int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
1044int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
1045int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
1046
Simon Glassb94dc892015-03-05 12:25:25 -07001047/*
1048 * The following functions provide access to the above without needing the
1049 * size parameter. We are trying to encourage the use of the 8/16/32-style
1050 * functions, rather than byte/word/dword. But both are supported.
1051 */
1052int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
Bin Meng02268592016-02-02 05:58:07 -08001053int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
1054int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
1055int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
1056int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
1057int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
Simon Glassb94dc892015-03-05 12:25:25 -07001058
Simon Glasseca7b0d2015-11-26 19:51:30 -07001059#ifdef CONFIG_DM_PCI_COMPAT
Simon Glassb94dc892015-03-05 12:25:25 -07001060/* Compatibility with old naming */
1061static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
1062 u32 value)
1063{
1064 return pci_write_config32(pcidev, offset, value);
1065}
1066
Simon Glassb94dc892015-03-05 12:25:25 -07001067/* Compatibility with old naming */
1068static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
1069 u16 value)
1070{
1071 return pci_write_config16(pcidev, offset, value);
1072}
1073
Simon Glassb94dc892015-03-05 12:25:25 -07001074/* Compatibility with old naming */
1075static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
1076 u8 value)
1077{
1078 return pci_write_config8(pcidev, offset, value);
1079}
1080
Simon Glassb94dc892015-03-05 12:25:25 -07001081/* Compatibility with old naming */
1082static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
1083 u32 *valuep)
1084{
1085 return pci_read_config32(pcidev, offset, valuep);
1086}
1087
Simon Glassb94dc892015-03-05 12:25:25 -07001088/* Compatibility with old naming */
1089static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
1090 u16 *valuep)
1091{
1092 return pci_read_config16(pcidev, offset, valuep);
1093}
1094
Simon Glassb94dc892015-03-05 12:25:25 -07001095/* Compatibility with old naming */
1096static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
1097 u8 *valuep)
1098{
1099 return pci_read_config8(pcidev, offset, valuep);
1100}
Simon Glasseca7b0d2015-11-26 19:51:30 -07001101#endif /* CONFIG_DM_PCI_COMPAT */
1102
1103/**
1104 * dm_pciauto_config_device() - configure a device ready for use
1105 *
1106 * Space is allocated for each PCI base address register (BAR) so that the
1107 * devices are mapped into memory and I/O space ready for use.
1108 *
1109 * @dev: Device to configure
1110 * @return 0 if OK, -ve on error
1111 */
1112int dm_pciauto_config_device(struct udevice *dev);
1113
Simon Glassd9e90bb2015-03-05 12:25:28 -07001114/**
Simon Glass27a733f2015-11-19 20:26:59 -07001115 * pci_conv_32_to_size() - convert a 32-bit read value to the given size
1116 *
1117 * Some PCI buses must always perform 32-bit reads. The data must then be
1118 * shifted and masked to reflect the required access size and offset. This
1119 * function performs this transformation.
1120 *
1121 * @value: Value to transform (32-bit value read from @offset & ~3)
1122 * @offset: Register offset that was read
1123 * @size: Required size of the result
1124 * @return the value that would have been obtained if the read had been
1125 * performed at the given offset with the correct size
1126 */
1127ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
1128
1129/**
1130 * pci_conv_size_to_32() - update a 32-bit value to prepare for a write
1131 *
1132 * Some PCI buses must always perform 32-bit writes. To emulate a smaller
1133 * write the old 32-bit data must be read, updated with the required new data
1134 * and written back as a 32-bit value. This function performs the
1135 * transformation from the old value to the new value.
1136 *
1137 * @value: Value to transform (32-bit value read from @offset & ~3)
1138 * @offset: Register offset that should be written
1139 * @size: Required size of the write
1140 * @return the value that should be written as a 32-bit access to @offset & ~3.
1141 */
1142ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1143 enum pci_size_t size);
1144
1145/**
Simon Glass6256d672015-11-19 20:27:00 -07001146 * pci_get_controller() - obtain the controller to use for a bus
1147 *
1148 * @dev: Device to check
1149 * @return pointer to the controller device for this bus
1150 */
1151struct udevice *pci_get_controller(struct udevice *dev);
1152
1153/**
Simon Glassdcdc0122015-11-19 20:27:01 -07001154 * pci_get_regions() - obtain pointers to all the region types
1155 *
1156 * @dev: Device to check
1157 * @iop: Returns a pointer to the I/O region, or NULL if none
1158 * @memp: Returns a pointer to the memory region, or NULL if none
1159 * @prefp: Returns a pointer to the pre-fetch region, or NULL if none
1160 * @return the number of non-NULL regions returned, normally 3
1161 */
1162int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1163 struct pci_region **memp, struct pci_region **prefp);
1164
1165/**
Simon Glasse2b6b562016-01-18 20:19:15 -07001166 * dm_pci_write_bar32() - Write the address of a BAR
1167 *
1168 * This writes a raw address to a bar
1169 *
1170 * @dev: PCI device to update
1171 * @barnum: BAR number (0-5)
1172 * @addr: BAR address
1173 */
1174void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
1175
1176/**
Simon Glass3452cb12015-11-29 13:17:53 -07001177 * dm_pci_read_bar32() - read a base address register from a device
1178 *
1179 * @dev: Device to check
1180 * @barnum: Bar number to read (numbered from 0)
1181 * @return: value of BAR
1182 */
1183u32 dm_pci_read_bar32(struct udevice *dev, int barnum);
1184
1185/**
Simon Glassc5f053b2015-11-29 13:18:03 -07001186 * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address
1187 *
1188 * @dev: Device containing the PCI address
1189 * @addr: PCI address to convert
1190 * @flags: Flags for the region type (PCI_REGION_...)
1191 * @return physical address corresponding to that PCI bus address
1192 */
1193phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
1194 unsigned long flags);
1195
1196/**
1197 * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
1198 *
1199 * @dev: Device containing the bus address
1200 * @addr: Physical address to convert
1201 * @flags: Flags for the region type (PCI_REGION_...)
1202 * @return PCI bus address corresponding to that physical address
1203 */
1204pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
1205 unsigned long flags);
1206
1207/**
1208 * dm_pci_map_bar() - get a virtual address associated with a BAR region
1209 *
1210 * Looks up a base address register and finds the physical memory address
1211 * that corresponds to it
1212 *
1213 * @dev: Device to check
1214 * @bar: Bar number to read (numbered from 0)
1215 * @flags: Flags for the region type (PCI_REGION_...)
1216 * @return: pointer to the virtual address to use
1217 */
1218void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
1219
1220#define dm_pci_virt_to_bus(dev, addr, flags) \
1221 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
1222#define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
1223 map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
1224 (len), (map_flags))
1225
1226#define dm_pci_phys_to_mem(dev, addr) \
1227 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
1228#define dm_pci_mem_to_phys(dev, addr) \
1229 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
1230#define dm_pci_phys_to_io(dev, addr) \
1231 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
1232#define dm_pci_io_to_phys(dev, addr) \
1233 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
1234
1235#define dm_pci_virt_to_mem(dev, addr) \
1236 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
1237#define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
1238 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
1239#define dm_pci_virt_to_io(dev, addr) \
1240 dm_dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
1241#define dm_pci_io_to_virt(dev, addr, len, map_flags) \
1242 dm_dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
1243
1244/**
Simon Glass70e0c582015-11-29 13:17:50 -07001245 * dm_pci_find_device() - find a device by vendor/device ID
1246 *
1247 * @vendor: Vendor ID
1248 * @device: Device ID
1249 * @index: 0 to find the first match, 1 for second, etc.
1250 * @devp: Returns pointer to the device, if found
1251 * @return 0 if found, -ve on error
1252 */
1253int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
1254 struct udevice **devp);
1255
1256/**
Simon Glassb639d512015-11-29 13:17:52 -07001257 * dm_pci_find_class() - find a device by class
1258 *
1259 * @find_class: 3-byte (24-bit) class value to find
1260 * @index: 0 to find the first match, 1 for second, etc.
1261 * @devp: Returns pointer to the device, if found
1262 * @return 0 if found, -ve on error
1263 */
1264int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
1265
1266/**
Simon Glassd9e90bb2015-03-05 12:25:28 -07001267 * struct dm_pci_emul_ops - PCI device emulator operations
1268 */
1269struct dm_pci_emul_ops {
1270 /**
1271 * get_devfn(): Check which device and function this emulators
1272 *
1273 * @dev: device to check
1274 * @return the device and function this emulates, or -ve on error
1275 */
1276 int (*get_devfn)(struct udevice *dev);
1277 /**
1278 * read_config() - Read a PCI configuration value
1279 *
1280 * @dev: Emulated device to read from
1281 * @offset: Byte offset within the device's configuration space
1282 * @valuep: Place to put the returned value
1283 * @size: Access size
1284 * @return 0 if OK, -ve on error
1285 */
1286 int (*read_config)(struct udevice *dev, uint offset, ulong *valuep,
1287 enum pci_size_t size);
1288 /**
1289 * write_config() - Write a PCI configuration value
1290 *
1291 * @dev: Emulated device to write to
1292 * @offset: Byte offset within the device's configuration space
1293 * @value: Value to write
1294 * @size: Access size
1295 * @return 0 if OK, -ve on error
1296 */
1297 int (*write_config)(struct udevice *dev, uint offset, ulong value,
1298 enum pci_size_t size);
1299 /**
1300 * read_io() - Read a PCI I/O value
1301 *
1302 * @dev: Emulated device to read from
1303 * @addr: I/O address to read
1304 * @valuep: Place to put the returned value
1305 * @size: Access size
1306 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1307 * other -ve value on error
1308 */
1309 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
1310 enum pci_size_t size);
1311 /**
1312 * write_io() - Write a PCI I/O value
1313 *
1314 * @dev: Emulated device to write from
1315 * @addr: I/O address to write
1316 * @value: Value to write
1317 * @size: Access size
1318 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1319 * other -ve value on error
1320 */
1321 int (*write_io)(struct udevice *dev, unsigned int addr,
1322 ulong value, enum pci_size_t size);
1323 /**
1324 * map_physmem() - Map a device into sandbox memory
1325 *
1326 * @dev: Emulated device to map
1327 * @addr: Memory address, normally corresponding to a PCI BAR.
1328 * The device should have been configured to have a BAR
1329 * at this address.
1330 * @lenp: On entry, the size of the area to map, On exit it is
1331 * updated to the size actually mapped, which may be less
1332 * if the device has less space
1333 * @ptrp: Returns a pointer to the mapped address. The device's
1334 * space can be accessed as @lenp bytes starting here
1335 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1336 * other -ve value on error
1337 */
1338 int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
1339 unsigned long *lenp, void **ptrp);
1340 /**
1341 * unmap_physmem() - undo a memory mapping
1342 *
1343 * This must be called after map_physmem() to undo the mapping.
1344 * Some devices can use this to check what has been written into
1345 * their mapped memory and perform an operations they require on it.
1346 * In this way, map/unmap can be used as a sort of handshake between
1347 * the emulated device and its users.
1348 *
1349 * @dev: Emuated device to unmap
1350 * @vaddr: Mapped memory address, as passed to map_physmem()
1351 * @len: Size of area mapped, as returned by map_physmem()
1352 * @return 0 if OK, -ve on error
1353 */
1354 int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
1355 unsigned long len);
1356};
1357
1358/* Get access to a PCI device emulator's operations */
1359#define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops)
1360
1361/**
1362 * sandbox_pci_get_emul() - Get the emulation device for a PCI device
1363 *
1364 * Searches for a suitable emulator for the given PCI bus device
1365 *
1366 * @bus: PCI bus to search
1367 * @find_devfn: PCI device and function address (PCI_DEVFN())
1368 * @emulp: Returns emulated device if found
1369 * @return 0 if found, -ENODEV if not found
1370 */
1371int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
1372 struct udevice **emulp);
1373
Simon Glass318d71c2015-07-06 16:47:44 -06001374#endif /* CONFIG_DM_PCI */
1375
1376/**
1377 * PCI_DEVICE - macro used to describe a specific pci device
1378 * @vend: the 16 bit PCI Vendor ID
1379 * @dev: the 16 bit PCI Device ID
1380 *
1381 * This macro is used to create a struct pci_device_id that matches a
1382 * specific device. The subvendor and subdevice fields will be set to
1383 * PCI_ANY_ID.
1384 */
1385#define PCI_DEVICE(vend, dev) \
1386 .vendor = (vend), .device = (dev), \
1387 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1388
1389/**
1390 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
1391 * @vend: the 16 bit PCI Vendor ID
1392 * @dev: the 16 bit PCI Device ID
1393 * @subvend: the 16 bit PCI Subvendor ID
1394 * @subdev: the 16 bit PCI Subdevice ID
1395 *
1396 * This macro is used to create a struct pci_device_id that matches a
1397 * specific device with subsystem information.
1398 */
1399#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1400 .vendor = (vend), .device = (dev), \
1401 .subvendor = (subvend), .subdevice = (subdev)
1402
1403/**
1404 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
1405 * @dev_class: the class, subclass, prog-if triple for this device
1406 * @dev_class_mask: the class mask for this device
1407 *
1408 * This macro is used to create a struct pci_device_id that matches a
1409 * specific PCI class. The vendor, device, subvendor, and subdevice
1410 * fields will be set to PCI_ANY_ID.
1411 */
1412#define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
1413 .class = (dev_class), .class_mask = (dev_class_mask), \
1414 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1415 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1416
1417/**
1418 * PCI_VDEVICE - macro used to describe a specific pci device in short form
1419 * @vend: the vendor name
1420 * @dev: the 16 bit PCI Device ID
1421 *
1422 * This macro is used to create a struct pci_device_id that matches a
1423 * specific PCI device. The subvendor, and subdevice fields will be set
1424 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1425 * private data.
1426 */
1427
1428#define PCI_VDEVICE(vend, dev) \
1429 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1430 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1431
1432/**
1433 * struct pci_driver_entry - Matches a driver to its pci_device_id list
1434 * @driver: Driver to use
1435 * @match: List of match records for this driver, terminated by {}
1436 */
1437struct pci_driver_entry {
1438 struct driver *driver;
1439 const struct pci_device_id *match;
1440};
1441
1442#define U_BOOT_PCI_DEVICE(__name, __match) \
1443 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
1444 .driver = llsym(struct driver, __name, driver), \
1445 .match = __match, \
1446 }
Simon Glassb94dc892015-03-05 12:25:25 -07001447
Paul Burton162116e2013-11-08 11:18:47 +00001448#endif /* __ASSEMBLY__ */
1449#endif /* _PCI_H */