| Bin Meng | ef4dc7e | 2014-12-17 15:50:41 +0800 | [diff] [blame] | 1 | CONFIG_X86=y |
| Bin Meng | 03b341b | 2015-04-27 23:22:24 +0800 | [diff] [blame] | 2 | CONFIG_VENDOR_INTEL=y |
| Bin Meng | ef4dc7e | 2014-12-17 15:50:41 +0800 | [diff] [blame] | 3 | CONFIG_DEFAULT_DEVICE_TREE="crownbay" |
| Joe Hershberger | a274ded | 2015-05-12 14:46:24 -0500 | [diff] [blame] | 4 | CONFIG_TARGET_CROWNBAY=y |
| Bin Meng | 3916df5 | 2015-06-17 11:15:39 +0800 | [diff] [blame] | 5 | CONFIG_SMP=y |
| 6 | CONFIG_MAX_CPUS=2 | ||||
| Bin Meng | 519dee0 | 2015-07-09 18:37:40 +0800 | [diff] [blame] | 7 | CONFIG_HAVE_VGA_BIOS=y |
| Bin Meng | 1530536 | 2015-04-24 18:10:06 +0800 | [diff] [blame] | 8 | CONFIG_GENERATE_PIRQ_TABLE=y |
| Bin Meng | 519dee0 | 2015-07-09 18:37:40 +0800 | [diff] [blame] | 9 | CONFIG_GENERATE_MP_TABLE=y |
| Simon Glass | e3ee2fb | 2016-02-22 22:55:43 -0700 | [diff] [blame] | 10 | CONFIG_FIT=y |
| Simon Glass | c08ebf6 | 2016-02-22 22:55:40 -0700 | [diff] [blame] | 11 | CONFIG_BOOTSTAGE=y |
| 12 | CONFIG_BOOTSTAGE_REPORT=y | ||||
| Bin Meng | 3916df5 | 2015-06-17 11:15:39 +0800 | [diff] [blame] | 13 | CONFIG_CMD_CPU=y |
| Joe Hershberger | 5a9d7f1 | 2015-06-22 16:15:30 -0500 | [diff] [blame] | 14 | # CONFIG_CMD_IMLS is not set |
| 15 | # CONFIG_CMD_FLASH is not set | ||||
| Thomas Chou | 3a077cd | 2015-11-11 21:39:33 +0800 | [diff] [blame] | 16 | CONFIG_CMD_GPIO=y |
| Joe Hershberger | 5a9d7f1 | 2015-06-22 16:15:30 -0500 | [diff] [blame] | 17 | # CONFIG_CMD_SETEXPR is not set |
| 18 | # CONFIG_CMD_NFS is not set | ||||
| Joe Hershberger | 17491a8 | 2015-06-22 16:15:29 -0500 | [diff] [blame] | 19 | CONFIG_CMD_BOOTSTAGE=y |
| Joe Hershberger | a274ded | 2015-05-12 14:46:24 -0500 | [diff] [blame] | 20 | CONFIG_OF_CONTROL=y |
| Bin Meng | 3916df5 | 2015-06-17 11:15:39 +0800 | [diff] [blame] | 21 | CONFIG_CPU=y |
| Joe Hershberger | 17491a8 | 2015-06-22 16:15:29 -0500 | [diff] [blame] | 22 | CONFIG_SPI_FLASH=y |
| Bin Meng | 27f5b19 | 2015-11-25 05:34:54 -0800 | [diff] [blame] | 23 | CONFIG_SPI_FLASH_GIGADEVICE=y |
| 24 | CONFIG_SPI_FLASH_MACRONIX=y | ||||
| 25 | CONFIG_SPI_FLASH_SST=y | ||||
| 26 | CONFIG_SPI_FLASH_WINBOND=y | ||||
| Bin Meng | 18ddcce | 2015-08-27 22:25:56 -0700 | [diff] [blame] | 27 | CONFIG_DM_ETH=y |
| Simon Glass | 9008a5b | 2015-08-19 09:33:43 -0600 | [diff] [blame] | 28 | CONFIG_E1000=y |
| Bin Meng | 0e0a8e6 | 2015-08-27 22:25:59 -0700 | [diff] [blame] | 29 | CONFIG_PCH_GBE=y |
| Bin Meng | 63c1098 | 2015-09-28 05:14:15 -0700 | [diff] [blame] | 30 | CONFIG_DM_PCI=y |
| 31 | CONFIG_DM_RTC=y | ||||
| Thomas Chou | a6cec01 | 2015-11-19 21:48:14 +0800 | [diff] [blame] | 32 | CONFIG_SYS_NS16550=y |
| Bin Meng | 72a049d | 2015-11-25 05:34:53 -0800 | [diff] [blame] | 33 | CONFIG_ICH_SPI=y |
| Bin Meng | 38de020 | 2015-11-13 00:11:22 -0800 | [diff] [blame] | 34 | CONFIG_TIMER=y |
| Bin Meng | d40efaa | 2015-08-27 22:25:55 -0700 | [diff] [blame] | 35 | CONFIG_USB=y |
| 36 | CONFIG_DM_USB=y | ||||
| Bin Meng | 63c1098 | 2015-09-28 05:14:15 -0700 | [diff] [blame] | 37 | CONFIG_VIDEO_VESA=y |
| 38 | CONFIG_FRAMEBUFFER_SET_VESA_MODE=y | ||||
| Bin Meng | 519dee0 | 2015-07-09 18:37:40 +0800 | [diff] [blame] | 39 | CONFIG_USE_PRIVATE_LIBGCC=y |