| Rajeshwari Shinde | 9b4ae50 | 2012-05-02 19:18:51 +0530 | [diff] [blame] | 1 | /* |
| Rajeshwari Shinde | dad39d4 | 2012-05-21 16:38:03 +0530 | [diff] [blame] | 2 | * SAMSUNG EXYNOS USB HOST EHCI Controller |
| Rajeshwari Shinde | 9b4ae50 | 2012-05-02 19:18:51 +0530 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2012 Samsung Electronics Co.Ltd |
| 5 | * Vivek Gautam <gautam.vivek@samsung.com> |
| 6 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| Rajeshwari Shinde | 9b4ae50 | 2012-05-02 19:18:51 +0530 | [diff] [blame] | 8 | */ |
| 9 | |
| Rajeshwari Shinde | dad39d4 | 2012-05-21 16:38:03 +0530 | [diff] [blame] | 10 | #ifndef __ASM_ARM_ARCH_EHCI_H__ |
| 11 | #define __ASM_ARM_ARCH_EHCI_H__ |
| Rajeshwari Shinde | 9b4ae50 | 2012-05-02 19:18:51 +0530 | [diff] [blame] | 12 | |
| 13 | #define CLK_24MHZ 5 |
| 14 | |
| Suriyan Ramasami | 97f4ef6 | 2014-10-29 09:22:43 -0700 | [diff] [blame] | 15 | #define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0) |
| 16 | #define PHYPWR_NORMAL_MASK_PHY1 (0x7 << 6) |
| 17 | #define PHYPWR_NORMAL_MASK_HSIC0 (0x7 << 9) |
| 18 | #define PHYPWR_NORMAL_MASK_HSIC1 (0x7 << 12) |
| 19 | #define RSTCON_HOSTPHY_SWRST (0xf << 3) |
| 20 | #define RSTCON_SWRST (0x1 << 0) |
| 21 | |
| Rajeshwari Shinde | 9b4ae50 | 2012-05-02 19:18:51 +0530 | [diff] [blame] | 22 | #define HOST_CTRL0_PHYSWRSTALL (1 << 31) |
| 23 | #define HOST_CTRL0_COMMONON_N (1 << 9) |
| 24 | #define HOST_CTRL0_SIDDQ (1 << 6) |
| 25 | #define HOST_CTRL0_FORCESLEEP (1 << 5) |
| 26 | #define HOST_CTRL0_FORCESUSPEND (1 << 4) |
| 27 | #define HOST_CTRL0_WORDINTERFACE (1 << 3) |
| 28 | #define HOST_CTRL0_UTMISWRST (1 << 2) |
| 29 | #define HOST_CTRL0_LINKSWRST (1 << 1) |
| 30 | #define HOST_CTRL0_PHYSWRST (1 << 0) |
| 31 | |
| 32 | #define HOST_CTRL0_FSEL_MASK (7 << 16) |
| 33 | |
| 34 | #define EHCICTRL_ENAINCRXALIGN (1 << 29) |
| 35 | #define EHCICTRL_ENAINCR4 (1 << 28) |
| 36 | #define EHCICTRL_ENAINCR8 (1 << 27) |
| 37 | #define EHCICTRL_ENAINCR16 (1 << 26) |
| 38 | |
| Inderpal Singh | 2eb6561 | 2014-01-08 09:19:56 +0530 | [diff] [blame] | 39 | #define HSIC_CTRL_REFCLKSEL (0x2) |
| 40 | #define HSIC_CTRL_REFCLKSEL_MASK (0x3) |
| 41 | #define HSIC_CTRL_REFCLKSEL_SHIFT (23) |
| 42 | |
| 43 | #define HSIC_CTRL_REFCLKDIV_12 (0x24) |
| 44 | #define HSIC_CTRL_REFCLKDIV_MASK (0x7f) |
| 45 | #define HSIC_CTRL_REFCLKDIV_SHIFT (16) |
| 46 | |
| 47 | #define HSIC_CTRL_SIDDQ (0x1 << 6) |
| 48 | #define HSIC_CTRL_FORCESLEEP (0x1 << 5) |
| 49 | #define HSIC_CTRL_FORCESUSPEND (0x1 << 4) |
| 50 | #define HSIC_CTRL_UTMISWRST (0x1 << 2) |
| 51 | #define HSIC_CTRL_PHYSWRST (0x1 << 0) |
| 52 | |
| Rajeshwari Shinde | 9b4ae50 | 2012-05-02 19:18:51 +0530 | [diff] [blame] | 53 | /* Register map for PHY control */ |
| Rajeshwari Shinde | dad39d4 | 2012-05-21 16:38:03 +0530 | [diff] [blame] | 54 | struct exynos_usb_phy { |
| Rajeshwari Shinde | 9b4ae50 | 2012-05-02 19:18:51 +0530 | [diff] [blame] | 55 | unsigned int usbphyctrl0; |
| 56 | unsigned int usbphytune0; |
| 57 | unsigned int reserved1[2]; |
| 58 | unsigned int hsicphyctrl1; |
| 59 | unsigned int hsicphytune1; |
| 60 | unsigned int reserved2[2]; |
| 61 | unsigned int hsicphyctrl2; |
| 62 | unsigned int hsicphytune2; |
| 63 | unsigned int reserved3[2]; |
| 64 | unsigned int ehcictrl; |
| 65 | unsigned int ohcictrl; |
| 66 | unsigned int usbotgsys; |
| 67 | unsigned int reserved4; |
| 68 | unsigned int usbotgtune; |
| 69 | }; |
| 70 | |
| Suriyan Ramasami | 97f4ef6 | 2014-10-29 09:22:43 -0700 | [diff] [blame] | 71 | struct exynos4412_usb_phy { |
| 72 | unsigned int usbphyctrl; |
| 73 | unsigned int usbphyclk; |
| 74 | unsigned int usbphyrstcon; |
| 75 | }; |
| 76 | |
| Rajeshwari Shinde | 9b4ae50 | 2012-05-02 19:18:51 +0530 | [diff] [blame] | 77 | /* Switch on the VBUS power. */ |
| 78 | int board_usb_vbus_init(void); |
| 79 | |
| Rajeshwari Shinde | dad39d4 | 2012-05-21 16:38:03 +0530 | [diff] [blame] | 80 | #endif /* __ASM_ARM_ARCH_EHCI_H__ */ |