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git01.mediatek.com / filogic / uboot / eaa39c6960f19c3c7f38641db379ee5d13016721 / . / board / ti / am57xx / mux_data.h
blob: f2f428ef9b8433221073586b0d2ac7ac2904297c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Felipe Balbi4750eb62014-11-10 14:02:44 -0600[diff] [blame]2/*
Nishanth Menoneaa39c62023-11-01 15:56:03 -0500[diff] [blame^]3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com
Felipe Balbi4750eb62014-11-10 14:02:44 -0600[diff] [blame]4 *
5 * Author: Felipe Balbi <balbi@ti.com>
6 *
7 * Based on board/ti/dra7xx/evm.c
Felipe Balbi4750eb62014-11-10 14:02:44 -0600[diff] [blame]8 */
9#ifndef _MUX_DATA_BEAGLE_X15_H_
10#define _MUX_DATA_BEAGLE_X15_H_
11
12#include <asm/arch/mux_dra7xx.h>
13
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]14const struct pad_conf_entry core_padconf_array_essential_x15[] = {
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]15 {GPMC_AD0, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad0.vin3a_d0 */
16 {GPMC_AD1, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad1.vin3a_d1 */
17 {GPMC_AD2, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad2.vin3a_d2 */
18 {GPMC_AD3, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad3.vin3a_d3 */
19 {GPMC_AD4, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad4.vin3a_d4 */
20 {GPMC_AD5, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad5.vin3a_d5 */
21 {GPMC_AD6, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad6.vin3a_d6 */
22 {GPMC_AD7, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad7.vin3a_d7 */
23 {GPMC_AD8, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad8.vin3a_d8 */
24 {GPMC_AD9, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad9.vin3a_d9 */
25 {GPMC_AD10, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad10.vin3a_d10 */
26 {GPMC_AD11, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad11.vin3a_d11 */
27 {GPMC_AD12, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad12.vin3a_d12 */
28 {GPMC_AD13, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad13.vin3a_d13 */
29 {GPMC_AD14, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad14.vin3a_d14 */
30 {GPMC_AD15, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad15.vin3a_d15 */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]31 {GPMC_A0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vin3a_d16 */
32 {GPMC_A1, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a1.vin3a_d17 */
33 {GPMC_A2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vin3a_d18 */
34 {GPMC_A3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vin3a_d19 */
35 {GPMC_A4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vin3a_d20 */
36 {GPMC_A5, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a5.vin3a_d21 */
37 {GPMC_A6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vin3a_d22 */
38 {GPMC_A7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vin3a_d23 */
39 {GPMC_A8, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a8.vin3a_hsync0 */
40 {GPMC_A9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vin3a_vsync0 */
41 {GPMC_A10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vin3a_de0 */
42 {GPMC_A11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a11.vin3a_fld0 */
43 {GPMC_A12, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a12.gpio2_2 */
44 {GPMC_A13, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.gpio2_3 */
45 {GPMC_A14, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a14.gpio2_4 */
46 {GPMC_A15, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.gpio2_5 */
47 {GPMC_A16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.gpio2_6 */
48 {GPMC_A17, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.gpio2_7 */
49 {GPMC_A18, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a18.gpio2_8 */
50 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
51 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
52 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
53 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
54 {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
55 {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
56 {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
57 {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
58 {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
59 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
60 {GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs0.gpio2_19 */
61 {GPMC_CS2, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.gpio2_20 */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]62 {GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_cs3.vin3a_clk0 */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]63 {GPMC_CLK, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_clk.dma_evt1 */
64 {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */
65 {GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */
66 {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */
67 {GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.dma_evt3 */
68 {GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben1.dma_evt4 */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]69 {GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* gpmc_wait0.gpio2_28 */
70 {VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)}, /* vin1b_clk1.gpio2_31 */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]71 {VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d2.gpio3_6 */
72 {VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d3.gpio3_7 */
73 {VIN1A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d4.gpio3_8 */
74 {VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d5.gpio3_9 */
75 {VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d6.gpio3_10 */
76 {VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d7.gpio3_11 */
77 {VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d8.gpio3_12 */
78 {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */
79 {VIN1A_D11, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d11.gpio3_15 */
80 {VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d12.gpio3_16 */
81 {VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d14.gpio3_18 */
82 {VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d16.gpio3_20 */
83 {VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d19.gpio3_23 */
84 {VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d20.gpio3_24 */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]85 {VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d22.gpio3_26 */
86 {VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_clk0.gpio3_28 */
87 {VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_de0.gpio3_29 */
88 {VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]89 {VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.pr1_uart0_cts_n */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]90 {VIN2A_VSYNC0, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_vsync0.pr1_uart0_rts_n */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]91 {VIN2A_D0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_d0.pr1_uart0_rxd */
92 {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */
93 {VIN2A_D2, (M8 | PIN_INPUT_PULLUP)}, /* vin2a_d2.uart10_rxd */
94 {VIN2A_D3, (M8 | PIN_OUTPUT)}, /* vin2a_d3.uart10_txd */
95 {VIN2A_D4, (M8 | PIN_INPUT_PULLUP)}, /* vin2a_d4.uart10_ctsn */
96 {VIN2A_D5, (M8 | PIN_OUTPUT_PULLUP)}, /* vin2a_d5.uart10_rtsn */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]97 {VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.gpio4_7 */
98 {VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.gpio4_8 */
99 {VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.gpio4_9 */
100 {VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.gpio4_10 */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]101 {VIN2A_D10, (M10 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.ehrpwm2B */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]102 {VIN2A_D11, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d11.ehrpwm2_tripzone_input */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]103 {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
104 {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
105 {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
106 {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
107 {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
108 {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
109 {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
110 {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
111 {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
112 {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
113 {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
114 {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]115 {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]116 {MDIO_MCLK, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
117 {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]118 {RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)}, /* RMII_MHZ_50_CLK.gpio5_17 */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]119 {UART3_RXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_rxd.gpio5_18 */
120 {UART3_TXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_txd.gpio5_19 */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]121 {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
122 {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
123 {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
124 {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
125 {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
126 {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
127 {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
128 {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
129 {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
130 {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
131 {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
132 {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]133 {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */
134 {USB2_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]135 {GPIO6_14, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_14.timer1 */
136 {GPIO6_15, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_15.timer2 */
137 {GPIO6_16, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_16.timer3 */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]138 {XREF_CLK0, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk0.clkout2 */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]139 {XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.gpio6_18 */
140 {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]141 {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]142 {MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkx.i2c3_sda */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]143 {MCASP1_FSX, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_fsx.i2c3_scl */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]144 {MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.i2c4_sda */
145 {MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.i2c4_scl */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]146 {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */
147 {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]148 {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
149 {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
150 {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
151 {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
152 {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
153 {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]154 {MCASP1_AXR8, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_axr8.gpio5_10 */
155 {MCASP1_AXR9, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_axr9.gpio5_11 */
156 {MCASP1_AXR10, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_axr10.gpio5_12 */
157 {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.gpio4_17 */
158 {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
159 {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr13.mcasp7_axr1 */
160 {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
161 {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]162 {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]163 {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
164 {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
165 {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr1.mcasp3_axr1 */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]166 {MCASP4_ACLKX, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_aclkx.uart8_rxd */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]167 {MCASP4_FSX, (M3 | PIN_OUTPUT)}, /* mcasp4_fsx.uart8_txd */
168 {MCASP4_AXR0, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_axr0.uart8_ctsn */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]169 {MCASP4_AXR1, (M3 | PIN_OUTPUT_PULLUP)}, /* mcasp4_axr1.uart8_rtsn */
170 {MCASP5_ACLKX, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_aclkx.uart9_rxd */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]171 {MCASP5_FSX, (M3 | PIN_OUTPUT)}, /* mcasp5_fsx.uart9_txd */
172 {MCASP5_AXR0, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_axr0.uart9_ctsn */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]173 {MCASP5_AXR1, (M3 | PIN_OUTPUT_PULLUP)}, /* mcasp5_axr1.uart9_rtsn */
Sekhar Nori709a52c2017-02-08 18:43:59 +0530[diff] [blame]174 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]175 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
176 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
177 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
178 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
179 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]180 {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]181 {GPIO6_10, (M10 | PIN_OUTPUT_PULLDOWN)}, /* gpio6_10.ehrpwm2A */
182 {GPIO6_11, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
Sekhar Nori709a52c2017-02-08 18:43:59 +0530[diff] [blame]183 {MMC3_CLK, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_clk.mmc3_clk */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]184 {MMC3_CMD, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_cmd.mmc3_cmd */
185 {MMC3_DAT0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat0.mmc3_dat0 */
186 {MMC3_DAT1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat1.mmc3_dat1 */
187 {MMC3_DAT2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat2.mmc3_dat2 */
188 {MMC3_DAT3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat3.mmc3_dat3 */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]189 {MMC3_DAT4, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat4.mmc3_dat4 */
190 {MMC3_DAT5, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat5.mmc3_dat5 */
191 {MMC3_DAT6, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat6.mmc3_dat6 */
192 {MMC3_DAT7, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat7.mmc3_dat7 */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]193 {SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */
194 {SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */
195 {SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]196 {SPI1_CS0, (M14 | PIN_INPUT)}, /* spi1_cs0.gpio7_10 */
197 {SPI1_CS1, (M14 | PIN_INPUT)}, /* spi1_cs1.gpio7_11 */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]198 {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */
Tomi Valkeinen939a8da2018-06-08 12:51:19 +0300[diff] [blame]199 {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]200 {SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.gpio7_14 */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]201 {SPI2_D1, (M14 | PIN_INPUT_SLEW)}, /* spi2_d1.gpio7_15 */
202 {SPI2_D0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_d0.gpio7_16 */
203 {SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.gpio7_17 */
204 {DCAN1_TX, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */
205 {DCAN1_RX, (M0 | PIN_INPUT | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */
206 {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
207 {UART1_TXD, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]208 {UART1_CTSN, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.gpio7_24 */
209 {UART1_RTSN, (M14 | PIN_INPUT)}, /* uart1_rtsn.gpio7_25 */
210 {UART2_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart2_rxd.gpio7_26 */
211 {UART2_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart2_txd.gpio7_27 */
212 {UART2_CTSN, (M2 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.uart3_rxd */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]213 {UART2_RTSN, (M1 | PIN_OUTPUT)}, /* uart2_rtsn.uart3_txd */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]214 {I2C1_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c1_sda.i2c1_sda */
215 {I2C1_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c1_scl.i2c1_scl */
216 {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
217 {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
218 {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */
219 {WAKEUP1, (M0 | PIN_INPUT)}, /* Wakeup1.Wakeup1 */
220 {WAKEUP2, (M0 | PIN_INPUT)}, /* Wakeup2.Wakeup2 */
221 {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */
222 {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */
223 {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */
224 {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]225 {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]226 {TDO, (M0 | PIN_OUTPUT)}, /* tdo.tdo */
227 {TCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* tclk.tclk */
228 {TRSTN, (M0 | PIN_INPUT)}, /* trstn.trstn */
229 {RTCK, (M0 | PIN_OUTPUT)}, /* rtck.rtck */
230 {EMU0, (M0 | PIN_INPUT)}, /* emu0.emu0 */
231 {EMU1, (M0 | PIN_INPUT)}, /* emu1.emu1 */
232 {NMIN_DSP, (M0 | PIN_INPUT)}, /* nmin_dsp.nmin_dsp */
233 {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */
234};
235
Caleb Robey61143db2020-01-02 08:17:26 -0600[diff] [blame]236const struct pad_conf_entry core_padconf_array_essential_bbai[] = {
237 /* Cape Bus i2c */
238 /* NOTE: For the i2cj_scl and i2ci_scl signals to work properly, the INPUTENABLE bit of the
239 * appropriate CTRL_CORE_PAD_x registers should be set to 0x1 because of retiming
240 * purposes.
241 */
242 {GPMC_A0, (M7 | PIN_INPUT_PULLUP)}, /* P9_19A: R6_GPIO7_3: gpmc_a0.i2c4_scl (Shared with F4_UART10_RTSN) */
243 {GPMC_A1, (M7 | PIN_INPUT_PULLUP)}, /* P9_20A: T9_GPIO7_4: gpmc_a1.i2c4_sda (Shared with D2_UART10_CTSN) */
244
245 /* Bluetooth UART */
246 {GPMC_A4, (M8 | PIN_INPUT)}, /* P6 UART6_RXD: gpmc_a4.uart6_rxd */
247 {GPMC_A5, (M8 | PIN_OUTPUT)}, /* R9 UART6_TXD: gpmc_a5.uart6_txd */
248 {GPMC_A6, (M8 | PIN_INPUT)}, /* R5 UART6_CTSN: gpmc_a6.uart6_ctsn */
249 {GPMC_A7, (M8 | PIN_OUTPUT)}, /* P5 UART6_RTSN: gpmc_a7.uart6_rtsn */
250
251 /* eMMC */
252 {GPMC_A19, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* K7: gpmc_a19.mmc2_dat4 */
253 {GPMC_A20, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* M7: gpmc_a20.mmc2_dat5 */
254 {GPMC_A21, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* J5: gpmc_a21.mmc2_dat6 */
255 {GPMC_A22, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* K6: gpmc_a22.mmc2_dat7 */
256 {GPMC_A23, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* J7: gpmc_a23.mmc2_clk */
257 {GPMC_A24, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* J4: gpmc_a24.mmc2_dat0 */
258 {GPMC_A25, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* J6: gpmc_a25.mmc2_dat1 */
259 {GPMC_A26, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* H4: gpmc_a26.mmc2_dat2 */
260 {GPMC_A27, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* H5: gpmc_a27.mmc2_dat3 */
261 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* H6: gpmc_cs1.mmc2_cmd */
262
263 {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* N1 RGMII_RST: gpmc_advn_ale.gpio2_23 */
264
265 {VIN1A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* AG8 INT_ADC: vin1a_clk0.gpio2_30 */
266 {VIN1A_DE0, (M10 | PIN_INPUT_PULLDOWN)}, /* P8_35B: AD9_EQEP1A_IN: vin1a_de0.eQEP1A_in */
267 {VIN1A_FLD0, (M10 | PIN_INPUT_PULLDOWN)}, /* P8_33B: AF9_EQEP1B_IN: vin1a_fld0.eQEP1B_in */
268 {VIN1A_VSYNC0, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_21A: AF8_TIMER13: vin1a_vsync0.gpio3_3 */
269
270 {VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* AH6 USR4: vin1a_d3.gpio3_7 */
271
272 {VIN1A_D6, (M10 | PIN_INPUT_PULLDOWN)}, /* P8_12: AG6: vin1a_d6.eQEP2A_in */
273 {VIN1A_D7, (M10 | PIN_INPUT_PULLDOWN)}, /* P8_11: AH4: vin1a_d7.eQEP2B_in */
274 {VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_15: AG4: vin1a_d8.gpio3_12 */
275 {VIN1A_D9, (M14 | PIN_INPUT)}, /* AG2 USB ID: vin1a_d9.gpio3_13 */
276 {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* AG3 USR3: vin1a_d10.gpio3_14 */
277 {VIN1A_D11, (M14 | PIN_INPUT_PULLDOWN)}, /* AG5 USR2: vin1a_d11.gpio3_15 */
278 {VIN1A_D13, (M14 | PIN_OUTPUT_PULLDOWN)}, /* AF6 USR0: vin1a_d13.gpio3_17 */
279 {VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)}, /* AF3 WL_REG_ON: vin1a_d14.gpio3_18 */
280 {VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)}, /* AF1 BT_HOST_WAKE: vin1a_d16.gpio3_20 */
281 {VIN1A_D17, (M14 | PIN_OUTPUT_PULLDOWN)}, /* AE3 BT_WAKE: vin1a_d17.gpio3_21 */
282 {VIN1A_D18, (M14 | PIN_OUTPUT_PULLUP)}, /* AE5 BT_REG_ON: vin1a_d18.gpio3_22 */
283 {VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)}, /* AE1 WL_HOST_WAKE: vin1a_d19.gpio3_23 */
284 {VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_26B: AE2: vin1a_d20.gpio3_24 */
285 {VIN1A_D23, (M14 | PIN_OUTPUT_PULLDOWN)}, /* AD3 VDD_ADC_SEL: vin1a_d23.gpio3_27 */
286
287 {VIN2A_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_15A: D1: vin2a_d2.gpio4_3 */
288
289 /* Cape Bus i2c (gpio shared) */
290 {VIN2A_D4, (M14 | PIN_INPUT)}, /* P9_20B: D2_UART10_CTSN: vin2a_d4. (Shared with T9_GPIO7_4) */
291 {VIN2A_D5, (M14 | PIN_INPUT)}, /* P9_19B: F4_UART10_RTSN: vin2a_d5. (Shared with R6_GPIO7_3) */
292
293 {VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_18: F5_GPIO4_9: vin2a_d8.gpio4_9 */
294 {VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_19: E6_EHRPWM2A: vin2a_d9.gpio4_10 */
295 {VIN2A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_13: D3_EHRPWM2B: vin2a_d10.gpio4_11 */
296 {VIN2A_D12, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_14: D5_GPIO4_13: vin2a_d12.gpio4_13 */
297 {VIN2A_D13, (M10 | PIN_INPUT_PULLDOWN)}, /* P9_42B: C2_GPIO4_14: vin2a_d13.eQEP3A_in */
298 {VIN2A_D14, (M10 | PIN_INPUT_PULLDOWN)}, /* P9_27A: C3_GPIO4_15: vin2a_d14.eQEP3B_in */
299 {VIN2A_D17, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_14: D6_EHRPWM3A: vin2a_d17.gpio4_25 */
300 {VIN2A_D18, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_16: C5_EHRPWM3B: vin2a_d18.gpio4_26 */
301 {VIN2A_D19, (M12 | PIN_INPUT | MANUAL_MODE)}, /* P8_15B: A3_GPIO4_27: vin2a_d19.pr1_pru1_gpi16 */
302 {VIN2A_D20, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_26: B3_GPIO4_28: vin2a_d20.gpio4_28 */
303 {VIN2A_D21, (M12 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* P8_16: B4_GPIO4_29: vin2a_d21.pr1_pru1_gpi18 */
304 {VOUT1_CLK, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_28A: D11_VOUT1_CLK: vout1_clk.gpio4_19 */
305 {VOUT1_DE, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_30A: B10_VOUT1_DE: vout1_de.gpio4_20 */
306 {VOUT1_HSYNC, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_29A: C11_VOUT1_HSYNC: vout1_hsync.gpio4_22 */
307 {VOUT1_VSYNC, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_27A: E11_VOUT1_VSYNC: vout1_vsync.gpio4_23 */
308 {VOUT1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_45A: F11_VOUT1_D0: vout1_d0.gpio8_0 */
309 {VOUT1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_46A: G10_VOUT1_D1: vout1_d1.gpio8_1 */
310 {VOUT1_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_43: F10_LCD_DATA2: vout1_d2.gpio8_2 */
311 {VOUT1_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_44: G11_LCD_DATA3: vout1_d3.gpio8_3 */
312 {VOUT1_D4, (M12 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* P8_41: E9_LCD_DATA4: vout1_d4.pr2_pru0_gpi1 */
313 {VOUT1_D5, (M12 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* P8_42: F9_LCD_DATA5: vout1_d5.pr2_pru0_gpi2 */
314 {VOUT1_D6, (M12 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* P8_39: F8_LCD_DATA6: vout1_d6.pr2_pru0_gpi3 */
315 {VOUT1_D7, (M12 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* P8_40: E7_LCD_DATA7: vout1_d7.pr2_pru0_gpi4 */
316 {VOUT1_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_37A: E8_VOUT1_D8: vout1_d8.gpio8_8 */
317 {VOUT1_D9, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_38A: D9_VOUT1_D9: vout1_d9.gpio8_9 */
318 {VOUT1_D10, (M14 | PIN_INPUT)}, /* P8_36A: D7_VOUT1_D10: vout1_d10.gpio8_10 */
319 {VOUT1_D11, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_34A: D8_VOUT1_D11: vout1_d11.gpio8_11 */
320 {VOUT1_D14, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_31A: C8_VOUT1_D14: vout1_d14.gpio8_14 */
321 {VOUT1_D15, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_32A: C7_VOUT1_D15: vout1_d15.gpio8_15 */
322 {VOUT1_D17, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_11B: B8_GPIO8_17: vout1_d17.gpio8_17 */
323 {VOUT1_D18, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_17: A7_GPIO8_18: vout1_d18.gpio8_18 */
324 {VOUT1_D19, (M12 | PIN_INPUT | MANUAL_MODE)}, /* P8_27B: A8_GPIO8_19: vout1_d19.pr2_pru0_gpi16 */
325 {VOUT1_D20, (M12 | PIN_INPUT | MANUAL_MODE)}, /* P8_28B: C9_GPIO8_20: vout1_d20.pr2_pru0_gpi17 */
326 {VOUT1_D21, (M12 | PIN_INPUT | MANUAL_MODE)}, /* P8_29B: A9_GPIO8_21: vout1_d21.pr2_pru0_gpi18 */
327 {VOUT1_D22, (M12 | PIN_INPUT | MANUAL_MODE)}, /* P8_30B: B9_GPIO8_22: vout1_d22.pr2_pru0_gpi19 */
328
329 /* Ethernet (and USB A overcurrent) */
330 {MDIO_MCLK, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* V1 MDIO_CLK: mdio_mclk.mdio_mclk */
331 {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* U4 MDIO_D: mdio_d.mdio_d */
332 {UART3_RXD, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* V2 GPIO5_18 (USB A overcurrent): uart3_rxd.gpio5_18 */
333 {UART3_TXD, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* Y1 MII0_INT: uart3_txd.gpio5_19 */
334 {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* W9 RGMII0_TXC: rgmii0_txc.rgmii0_txc */
335 {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* V9 RGMII0_TXCTL: rgmii0_txctl.rgmii0_txctl */
336 {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* V7 RGMII0_TXD3: rgmii0_txd3.rgmii0_txd3 */
337 {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* U7 RGMII0_TXD2: rgmii0_txd2.rgmii0_txd2 */
338 {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* V6 RGMII0_TXD1: rgmii0_txd1.rgmii0_txd1 */
339 {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* U6 RGMII0_TXD0: rgmii0_txd0.rgmii0_txd0 */
340 {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* U5 RGMII0_RXC: rgmii0_rxc.rgmii0_rxc */
341 {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* V5 RGMII0_RXCTL: rgmii0_rxctl.rgmii0_rxctl */
342 {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* V4 RGMII0_RXD3: rgmii0_rxd3.rgmii0_rxd3 */
343 {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* V3 RGMII0_RXD2: rgmii0_rxd2.rgmii0_rxd2 */
344 {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* Y2 RGMII0_RXD1: rgmii0_rxd1.rgmii0_rxd1 */
345 {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* W2 RGMII0_RXD0: rgmii0_rxd0.rgmii0_rxd0 */
346
347 {USB2_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* AC10 USB2_DRVVBUS: usb2_drvvbus.usb2_drvvbus */
348
349 {GPIO6_14, (M3 | PIN_INPUT)}, /* P9_26A: E21_UART10_RXD: gpio6_14.uart10_rxd */
350 {GPIO6_15, (M0 | PIN_INPUT_PULLDOWN)}, /* P9_24: F20_UART10_TXD: gpio6_15.gpio6_15 */
351 {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* F21 PMIC_INT: gpio6_16.gpio6_16 */
352 {XREF_CLK0, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_25: D18_GPIO6_17: xref_clk0.gpio6_17 */
353 {XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* P8_09: E17_TIMER14: xref_clk1.gpio6_18 */
354 {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_22A: B26_TIMER15: xref_clk2.gpio6_19 */
355 {XREF_CLK3, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_41A: C23_CLKOUT3: xref_clk3.gpio6_20 */
356 {MCASP1_ACLKR, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_12: B14_MCASP_ACLKR: mcasp1_aclkr.gpio5_0 */
357 {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* P9_18B: G12_GPIO5_2: mcasp1_axr0.i2c5_sda */
358 {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* P9_17B: F12_GPIO5_3: mcasp1_axr1.i2c5_scl */
359 {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* J11 USR1: mcasp1_axr3.gpio5_5 */
360 {MCASP1_AXR5, (M14 | PIN_OUTPUT_PULLUP)}, /* F13 eMMC_RSTn (missing on schematic): mcasp1_axr5.gpio5_7 */
361 {MCASP1_AXR8, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* P9_31A: B12_SPI3_SCLK: mcasp1_axr8.gpio5_10 */
362 {MCASP1_AXR9, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* P9_29A: A11_SPI3_D1: mcasp1_axr9.gpio5_11 */
363 {MCASP1_AXR10, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* P9_30: B13_SPI3_D0: mcasp1_axr10.gpio5_12 */
364 {MCASP1_AXR11, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* P9_28: A12_SPI3_CS0: mcasp1_axr11.gpio4_17 */
365 {MCASP1_AXR12, (M14 | PIN_INPUT | SLEWCONTROL)}, /* P9_42A: E14_GPIO4_18: mcasp1_axr12.gpio4_18 */
366 {MCASP1_AXR13, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* P8_10: A13_TIMER10: mcasp1_axr13.gpio6_4 */
367 {MCASP1_AXR14, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* P8_07: G14_TIMER11: mcasp1_axr14.gpio6_5 */
368 {MCASP1_AXR15, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* P8_08: F14_TIMER12: mcasp1_axr15.gpio6_6 */
369 {MCASP3_AXR0, (M4 | PIN_INPUT | SLEWCONTROL)}, /* P9_11A: B19_UART5_RXD: mcasp3_axr0.uart5_rxd */
370
371 /* microSD Socket */
372 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* W6: mmc1_clk.mmc1_clk */
373 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* Y6: mmc1_cmd.mmc1_cmd */
374 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* AA6: mmc1_dat0.mmc1_dat0 */
375 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* Y4: mmc1_dat1.mmc1_dat1 */
376 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* AA5: mmc1_dat2.mmc1_dat2 */
377 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* Y3: mmc1_dat3.mmc1_dat3 */
378 {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* W7: mmc1_sdcd.gpio6_27 */
379
380 {MMC3_CLK, (M14 | PIN_INPUT_PULLUP)}, /* P8_21: AD4_MMC3_CLK: mmc3_clk.gpio6_29 */
381 {MMC3_CMD, (M14 | PIN_INPUT_PULLUP)}, /* P8_20: AC4_MMC3_CMD: mmc3_cmd.gpio6_30 */
382 {MMC3_DAT0, (M14 | PIN_INPUT_PULLUP)}, /* P8_25: AC7_MMC3_DATA0: mmc3_dat0.gpio6_31 */
383 {MMC3_DAT1, (M14 | PIN_INPUT_PULLUP)}, /* P8_24: AC6_MMC3_DATA1: mmc3_dat1.gpio7_0 */
384 {MMC3_DAT2, (M14 | PIN_INPUT_PULLUP)}, /* P8_05: AC9_MMC3_DATA2: mmc3_dat2.gpio7_1 */
385 {MMC3_DAT3, (M14 | PIN_INPUT_PULLUP)}, /* P8_06: AC3_MMC3_DATA3: mmc3_dat3.gpio7_2 */
386 {MMC3_DAT4, (M14 | PIN_INPUT_PULLUP)}, /* P8_23: AC8_MMC3_DATA4: mmc3_dat4.gpio1_22 */
387 {MMC3_DAT5, (M14 | PIN_INPUT_PULLUP)}, /* P8_22: AD6_MMC3_DATA5: mmc3_dat5.gpio1_23 */
388 {MMC3_DAT6, (M14 | PIN_INPUT_PULLUP)}, /* P8_03: AB8_MMC3_DATA6: mmc3_dat6.gpio1_24 */
389 {MMC3_DAT7, (M14 | PIN_INPUT_PULLUP)}, /* P8_04: AB5_MMC3_DATA7: mmc3_dat7.gpio1_25 */
390 {SPI1_CS1, (M14 | PIN_INPUT_PULLDOWN)}, /* P9_23: A22_SPI2_CS1: spi1_cs1.gpio7_11 */
391 {SPI1_CS2, (M6 | PIN_INPUT | SLEWCONTROL)}, /* B21 HDMI_DDC_HPD: spi1_cs2.hdmi1_hpd */
392 {SPI2_SCLK, (M1 | PIN_INPUT)}, /* P9_22B: A26_UART3_RXD: spi2_sclk.uart3_rxd */
393 {SPI2_D0, (M14 | PIN_INPUT | SLEWCONTROL)}, /* P9_18A: G17_SPI2_D0: spi2_d0.gpio7_16 */
394 {SPI2_CS0, (M14 | PIN_INPUT | SLEWCONTROL)}, /* P9_17A: B24_SPI2_CS0: spi2_cs0.gpio7_17 */
395 {DCAN1_TX, (M2 | PIN_INPUT | SLEWCONTROL)}, /* G20 unused: dcan1_tx.uart8_rxd */
396 {DCAN1_RX, (M6 | PIN_INPUT | SLEWCONTROL)}, /* G19 unused: dcan1_rx.hdmi1_cec */
397
398 /* BeagleBone AI: Debug UART */
399 {UART1_RXD, (M0 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
400 {UART1_TXD, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
401
402 /* WiFi MMC */
403 {UART1_CTSN, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* uart1_ctsn.mmc4_clk */
404 {UART1_RTSN, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* uart1_rtsn.mmc4_cmd */
405 {UART2_RXD, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* uart2_rxd.mmc4_dat0 */
406 {UART2_TXD, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* uart2_txd.mmc4_dat1 */
407 {UART2_CTSN, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* uart2_ctsn.mmc4_dat2 */
408 {UART2_RTSN, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* uart2_rtsn.mmc4_dat3 */
409
410 /* On-board I2C */
411 {I2C1_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c1_sda.i2c1_sda */
412 {I2C1_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c1_scl.i2c1_scl */
413
414 /* HDMI I2C */
415 {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
416 {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
417
418 {ON_OFF, (M0 | PIN_OUTPUT)}, /* Y11: on_off.on_off */
419 {RTC_PORZ, (M0 | PIN_INPUT)}, /* AB17: rtc_porz.rtc_porz */
420 {TMS, (M0 | PIN_INPUT_PULLUP)}, /* F18: tms.tms */
421 {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* D23: tdi.tdi */
422 {TDO, (M0 | PIN_OUTPUT)}, /* F19: tdo.tdo */
423 {TCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* E20: tclk.tclk */
424 {TRSTN, (M0 | PIN_INPUT)}, /* D20: trstn.trstn */
425 {RTCK, (M0 | PIN_OUTPUT)}, /* E18: rtck.rtck */
426 {EMU0, (M0 | PIN_INPUT)}, /* G21: emu0.emu0 */
427 {EMU1, (M0 | PIN_INPUT)}, /* D24: emu1.emu1 */
428 {RESETN, (M0 | PIN_INPUT_PULLUP)}, /* E23: resetn.resetn */
429 {NMIN_DSP, (M0 | PIN_INPUT)}, /* D21: nmin_dsp.nmin_dsp */
430 {RSTOUTN, (M0 | PIN_OUTPUT)}, /* F23: rstoutn.rstoutn */
431};
432
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]433const struct pad_conf_entry core_padconf_array_delta_x15_sr1_1[] = {
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]434 {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */
435 {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_clk.vout1_clk */
436 {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_de.vout1_de */
437 {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_hsync.vout1_hsync */
438 {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_vsync.vout1_vsync */
439 {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d0.vout1_d0 */
440 {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d1.vout1_d1 */
441 {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d2.vout1_d2 */
442 {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d3.vout1_d3 */
443 {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d4.vout1_d4 */
444 {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d5.vout1_d5 */
445 {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d6.vout1_d6 */
446 {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d7.vout1_d7 */
447 {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d8.vout1_d8 */
448 {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d9.vout1_d9 */
449 {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d10.vout1_d10 */
450 {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d11.vout1_d11 */
451 {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d12.vout1_d12 */
452 {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d13.vout1_d13 */
453 {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d14.vout1_d14 */
454 {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d15.vout1_d15 */
455 {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d16.vout1_d16 */
456 {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d17.vout1_d17 */
457 {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d18.vout1_d18 */
458 {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d19.vout1_d19 */
459 {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d20.vout1_d20 */
460 {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d21.vout1_d21 */
461 {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d22.vout1_d22 */
462 {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d23.vout1_d23 */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]463};
464
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]465const struct pad_conf_entry core_padconf_array_delta_x15_sr2_0[] = {
466 {VIN1A_CLK0, (M14 | PIN_INPUT)}, /* vin1a_clk0.gpio2_30 */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]467 {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_clk.vout1_clk */
468 {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_de.vout1_de */
469 {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
470 {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */
471 {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */
472 {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */
473 {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */
474 {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */
475 {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */
476 {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */
477 {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */
478 {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */
479 {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */
480 {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */
481 {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */
482 {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */
483 {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */
484 {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */
485 {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */
486 {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */
487 {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */
488 {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */
489 {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */
490 {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */
491 {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */
492 {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */
493 {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */
494 {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]495};
496
Caleb Robey61143db2020-01-02 08:17:26 -0600[diff] [blame]497const struct iodelay_cfg_entry iodelay_cfg_array_bbai[] = {
498 {0x0190, 274, 0}, /* CFG_GPMC_A19_OEN */
499 {0x0194, 162, 0}, /* CFG_GPMC_A19_OUT */
500 {0x01A8, 401, 0}, /* CFG_GPMC_A20_OEN */
501 {0x01AC, 73, 0}, /* CFG_GPMC_A20_OUT */
502 {0x01B4, 465, 0}, /* CFG_GPMC_A21_OEN */
503 {0x01B8, 115, 0}, /* CFG_GPMC_A21_OUT */
504 {0x01C0, 633, 0}, /* CFG_GPMC_A22_OEN */
505 {0x01C4, 47, 0}, /* CFG_GPMC_A22_OUT */
506 {0x01D0, 935, 280}, /* CFG_GPMC_A23_OUT */
507 {0x01D8, 621, 0}, /* CFG_GPMC_A24_OEN */
508 {0x01DC, 0, 0}, /* CFG_GPMC_A24_OUT */
509 {0x01E4, 183, 0}, /* CFG_GPMC_A25_OEN */
510 {0x01E8, 0, 0}, /* CFG_GPMC_A25_OUT */
511 {0x01F0, 467, 0}, /* CFG_GPMC_A26_OEN */
512 {0x01F4, 0, 0}, /* CFG_GPMC_A26_OUT */
513 {0x01FC, 262, 0}, /* CFG_GPMC_A27_OEN */
514 {0x0200, 46, 0}, /* CFG_GPMC_A27_OUT */
515 {0x0364, 684, 0}, /* CFG_GPMC_CS1_OEN */
516 {0x0368, 76, 0}, /* CFG_GPMC_CS1_OUT */
517 {0x06F0, 260, 0}, /* CFG_RGMII0_RXC_IN */
518 {0x06FC, 0, 1412}, /* CFG_RGMII0_RXCTL_IN */
519 {0x0708, 123, 1047}, /* CFG_RGMII0_RXD0_IN */
520 {0x0714, 139, 1081}, /* CFG_RGMII0_RXD1_IN */
521 {0x0720, 195, 1100}, /* CFG_RGMII0_RXD2_IN */
522 {0x072C, 239, 1216}, /* CFG_RGMII0_RXD3_IN */
523 {0x0740, 89, 0}, /* CFG_RGMII0_TXC_OUT */
524 {0x074C, 15, 125}, /* CFG_RGMII0_TXCTL_OUT */
525 {0x0758, 339, 162}, /* CFG_RGMII0_TXD0_OUT */
526 {0x0764, 146, 94}, /* CFG_RGMII0_TXD1_OUT */
527 {0x0770, 0, 27}, /* CFG_RGMII0_TXD2_OUT */
528 {0x077C, 291, 205}, /* CFG_RGMII0_TXD3_OUT */
529 {0x0840, 0, 0}, /* CFG_UART1_CTSN_IN */
530 {0x0848, 0, 0}, /* CFG_UART1_CTSN_OUT */
531 {0x084C, 307, 0}, /* CFG_UART1_RTSN_IN */
532 {0x0850, 0, 0}, /* CFG_UART1_RTSN_OEN */
533 {0x0854, 0, 0}, /* CFG_UART1_RTSN_OUT */
534 {0x0870, 785, 0}, /* CFG_UART2_CTSN_IN */
535 {0x0874, 0, 0}, /* CFG_UART2_CTSN_OEN */
536 {0x0878, 0, 0}, /* CFG_UART2_CTSN_OUT */
537 {0x087C, 613, 0}, /* CFG_UART2_RTSN_IN */
538 {0x0880, 0, 0}, /* CFG_UART2_RTSN_OEN */
539 {0x0884, 0, 0}, /* CFG_UART2_RTSN_OUT */
540 {0x0888, 683, 0}, /* CFG_UART2_RXD_IN */
541 {0x088C, 0, 0}, /* CFG_UART2_RXD_OEN */
Wolfgang Denk62fb2b42021-09-27 17:42:39 +0200[diff] [blame]542 {0x0890, 0, 0}, /* CFG_UART2_RXD_OUT */
Caleb Robey61143db2020-01-02 08:17:26 -0600[diff] [blame]543 {0x0894, 835, 0}, /* CFG_UART2_TXD_IN */
544 {0x0898, 0, 0}, /* CFG_UART2_TXD_OEN */
545 {0x089C, 0, 0}, /* CFG_UART2_TXD_OUT */
546 {0x0ABC, 0, 1100}, /* CFG_VIN2A_D19_IN */
547 {0x0AE0, 0, 1300}, /* CFG_VIN2A_D21_IN */
548 {0x0B1C, 0, 1000}, /* CFG_VIN2A_D4_IN */
549 {0x0B28, 0, 1700}, /* CFG_VIN2A_D5_IN */
550 {0x0C18, 0, 500}, /* CFG_VOUT1_D19_IN */
551 {0x0C30, 0, 716}, /* CFG_VOUT1_D20_IN */
552 {0x0C3C, 0, 0}, /* CFG_VOUT1_D21_IN */
553 {0x0C48, 0, 404}, /* CFG_VOUT1_D22_IN */
554 {0x0C78, 0, 0}, /* CFG_VOUT1_D4_IN */
555 {0x0C84, 0, 365}, /* CFG_VOUT1_D5_IN */
Wolfgang Denk62fb2b42021-09-27 17:42:39 +0200[diff] [blame]556 {0x0C90, 0, 0}, /* CFG_VOUT1_D6_IN */
Caleb Robey61143db2020-01-02 08:17:26 -0600[diff] [blame]557 {0x0C9C, 0, 218}, /* CFG_VOUT1_D7_IN */
558};
559
Lokesh Vutla1e3425c2017-12-29 11:47:55 +0530[diff] [blame]560const struct pad_conf_entry core_padconf_array_essential_am574x_idk[] = {
561 {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */
562 {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */
563 {GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a2.vin4b_d2 */
564 {GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a3.vin4b_d3 */
565 {GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a4.vin4b_d4 */
566 {GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a5.vin4b_d5 */
567 {GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a6.vin4b_d6 */
568 {GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a7.vin4b_d7 */
569 {GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a8.vin4b_hsync1 */
570 {GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a9.vin4b_vsync1 */
571 {GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a10.vin4b_clk1 */
572 {GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a11.vin4b_de1 */
573 {GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a12.vin4b_fld1 */
574 {GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
575 {GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
576 {GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
577 {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
578 {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
579 {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
580 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
581 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
582 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
583 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
584 {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
585 {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
586 {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
587 {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
588 {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
589 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
590 {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
591 {VIN1A_D5, (M14 | PIN_OUTPUT)}, /* vin1a_d5.gpio3_9 */
592 {VIN1A_D6, (M14 | PIN_OUTPUT)}, /* vin1a_d6.gpio3_10 */
593 {VIN1A_D7, (M14 | PIN_OUTPUT)}, /* vin1a_d7.gpio3_11 */
594 {VIN1A_D8, (M14 | PIN_OUTPUT)}, /* vin1a_d8.gpio3_12 */
595 {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */
596 {VIN1A_D12, (M14 | PIN_INPUT)}, /* vin1a_d12.gpio3_16 */
597 {VIN1A_D13, (M14 | PIN_OUTPUT)}, /* vin1a_d13.gpio3_17 */
598 {VIN1A_D14, (M14 | PIN_OUTPUT)}, /* vin1a_d14.gpio3_18 */
599 {VIN1A_D15, (M14 | PIN_OUTPUT)}, /* vin1a_d15.gpio3_19 */
600 {VIN1A_D17, (M14 | PIN_OUTPUT)}, /* vin1a_d17.gpio3_21 */
601 {VIN1A_D18, (M14 | PIN_OUTPUT_PULLDOWN)}, /* vin1a_d18.gpio3_22 */
602 {VIN1A_D19, (M14 | PIN_OUTPUT_PULLUP)}, /* vin1a_d19.gpio3_23 */
603 {VIN1A_D22, (M14 | PIN_INPUT)}, /* vin1a_d22.gpio3_26 */
604 {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
605 {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */
606 {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
607 {VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */
608 {VIN2A_VSYNC0, (M14 | PIN_INPUT)}, /* vin2a_vsync0.gpio4_0 */
609 {VIN2A_D0, (M11 | PIN_INPUT)}, /* vin2a_d0.pr1_uart0_rxd */
610 {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */
611 {VIN2A_D2, (M10 | PIN_OUTPUT)}, /* vin2a_d2.eCAP1_in_PWM1_out */
612 {VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_edc_latch0_in */
613 {VIN2A_D4, (M11 | PIN_OUTPUT)}, /* vin2a_d4.pr1_edc_sync0_out */
614 {VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.pr1_pru1_gpo2 */
615 {VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */
616 {VIN2A_D11, (M11 | PIN_INPUT)}, /* vin2a_d11.pr1_mdio_data */
617 {VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
618 {VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
619 {VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
620 {VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
621 {VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
622 {VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
623 {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
624 {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
625 {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
626 {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
627 {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
628 {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
629 {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_clk.vout1_clk */
630 {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_de.vout1_de */
631 {VOUT1_FLD, (M14 | PIN_OUTPUT)}, /* vout1_fld.gpio4_21 */
632 {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
633 {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */
634 {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */
635 {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */
636 {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */
637 {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */
638 {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */
639 {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */
640 {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */
641 {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */
642 {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */
643 {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */
644 {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */
645 {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */
646 {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */
647 {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */
648 {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */
649 {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */
650 {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */
651 {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */
652 {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */
653 {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */
654 {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */
655 {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */
656 {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */
657 {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */
658 {MDIO_MCLK, (M0 | PIN_INPUT_SLEW)}, /* mdio_mclk.mdio_mclk */
659 {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */
660 {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
661 {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
662 {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
663 {RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
664 {RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
665 {RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
666 {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
667 {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
668 {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
669 {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
670 {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
671 {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
672 {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */
673 {USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */
674 {GPIO6_14, (M0 | PIN_OUTPUT)}, /* gpio6_14.gpio6_14 */
675 {GPIO6_15, (M0 | PIN_OUTPUT)}, /* gpio6_15.gpio6_15 */
676 {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
677 {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */
678 {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */
679 {XREF_CLK2, (M14 | PIN_OUTPUT)}, /* xref_clk2.gpio6_19 */
680 {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
681 {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
682 {MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.pr2_mdio_data */
683 {MCASP1_ACLKR, (M14 | PIN_INPUT)}, /* mcasp1_aclkr.gpio5_0 */
684 {MCASP1_FSR, (M14 | PIN_INPUT)}, /* mcasp1_fsr.gpio5_1 */
685 {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */
686 {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
687 {MCASP1_AXR2, (M14 | PIN_INPUT)}, /* mcasp1_axr2.gpio5_4 */
688 {MCASP1_AXR3, (M14 | PIN_INPUT)}, /* mcasp1_axr3.gpio5_5 */
689 {MCASP1_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp1_axr4.gpio5_6 */
690 {MCASP1_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp1_axr5.gpio5_7 */
691 {MCASP1_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp1_axr6.gpio5_8 */
692 {MCASP1_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp1_axr7.gpio5_9 */
693 {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr8.pr2_mii0_txen */
694 {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr9.pr2_mii0_txd3 */
695 {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr10.pr2_mii0_txd2 */
696 {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.pr2_mii0_txd1 */
697 {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr12.pr2_mii0_txd0 */
698 {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
699 {MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.pr2_mii0_rxdv */
700 {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
701 {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
702 {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
703 {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
704 {MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.pr2_mii0_rxlink */
705 {MCASP2_AXR4, (M14 | PIN_INPUT)}, /* mcasp2_axr4.gpio1_4 */
706 {MCASP2_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp2_axr5.gpio6_7 */
707 {MCASP2_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp2_axr6.gpio2_29 */
708 {MCASP2_AXR7, (M14 | PIN_INPUT)}, /* mcasp2_axr7.gpio1_5 */
709 {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */
710 {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */
711 {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */
712 {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */
713 {MCASP4_ACLKX, (M2 | PIN_INPUT)}, /* mcasp4_aclkx.spi3_sclk */
714 {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */
715 {MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */
716 {MCASP5_ACLKX, (M13 | PIN_OUTPUT | MANUAL_MODE)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */
717 {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_fsx.pr2_pru1_gpi2 */
718 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
719 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
720 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
721 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
722 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
723 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
724 {MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */
725 {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */
726 {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */
727 {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
728 {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
729 {MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */
730 {MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
731 {MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */
732 {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */
733 {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */
734 {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */
735 {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */
736 {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */
737 {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */
738 {SPI1_SCLK, (M14 | PIN_OUTPUT)}, /* spi1_sclk.gpio7_7 */
739 {SPI1_D1, (M14 | PIN_OUTPUT)}, /* spi1_d1.gpio7_8 */
740 {SPI1_D0, (M14 | PIN_OUTPUT)}, /* spi1_d0.gpio7_9 */
741 {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
742 {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
743 {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */
Tomi Valkeinen939a8da2018-06-08 12:51:19 +0300[diff] [blame]744 {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
Lokesh Vutla1e3425c2017-12-29 11:47:55 +0530[diff] [blame]745 {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */
746 {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d1.spi2_d1 */
747 {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d0.spi2_d0 */
748 {SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */
749 {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
750 {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */
751 {UART1_RXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */
752 {UART1_TXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_txd.gpio7_23 */
753 {UART2_RXD, (M4 | PIN_INPUT)}, /* uart2_rxd.uart2_rxd */
754 {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */
755 {UART2_CTSN, (M2 | PIN_INPUT)}, /* uart2_ctsn.uart3_rxd */
756 {UART2_RTSN, (M1 | PIN_OUTPUT)}, /* uart2_rtsn.uart3_txd */
757 {I2C1_SDA, (M0 | PIN_INPUT)}, /* i2c1_sda.i2c1_sda */
758 {I2C1_SCL, (M0 | PIN_INPUT)}, /* i2c1_scl.i2c1_scl */
759 {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
760 {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
761 {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */
762 {WAKEUP1, (M0 | PIN_INPUT)}, /* Wakeup1.Wakeup1 */
763 {WAKEUP2, (M0 | PIN_INPUT)}, /* Wakeup2.Wakeup2 */
764 {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */
765 {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */
766 {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */
767 {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
768 {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */
769 {TDO, (M0 | PIN_OUTPUT_PULLUP)}, /* tdo.tdo */
770 {TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */
771 {TRSTN, (M0 | PIN_INPUT_PULLDOWN)}, /* trstn.trstn */
772 {RTCK, (M0 | PIN_OUTPUT_PULLUP)}, /* rtck.rtck */
773 {EMU0, (M0 | PIN_INPUT_PULLUP)}, /* emu0.emu0 */
774 {EMU1, (M0 | PIN_INPUT_PULLUP)}, /* emu1.emu1 */
775 {RESETN, (M0 | PIN_INPUT)}, /* resetn.resetn */
776 {NMIN_DSP, (M0 | PIN_INPUT)}, /* nmin_dsp.nmin_dsp */
777 {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */
778};
779
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]780const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = {
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]781 {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */
782 {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */
783 {GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a2.vin4b_d2 */
784 {GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a3.vin4b_d3 */
785 {GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a4.vin4b_d4 */
786 {GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a5.vin4b_d5 */
787 {GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a6.vin4b_d6 */
788 {GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a7.vin4b_d7 */
789 {GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a8.vin4b_hsync1 */
790 {GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a9.vin4b_vsync1 */
791 {GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a10.vin4b_clk1 */
792 {GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a11.vin4b_de1 */
793 {GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a12.vin4b_fld1 */
794 {GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
795 {GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
796 {GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
797 {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
798 {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
799 {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]800 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
801 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
802 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
803 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]804 {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]805 {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
806 {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
807 {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
808 {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
809 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]810 {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
811 {VIN1A_D5, (M14 | PIN_OUTPUT)}, /* vin1a_d5.gpio3_9 */
812 {VIN1A_D6, (M14 | PIN_OUTPUT)}, /* vin1a_d6.gpio3_10 */
813 {VIN1A_D7, (M14 | PIN_OUTPUT)}, /* vin1a_d7.gpio3_11 */
814 {VIN1A_D8, (M14 | PIN_OUTPUT)}, /* vin1a_d8.gpio3_12 */
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]815 {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]816 {VIN1A_D12, (M14 | PIN_INPUT)}, /* vin1a_d12.gpio3_16 */
817 {VIN1A_D13, (M14 | PIN_OUTPUT)}, /* vin1a_d13.gpio3_17 */
818 {VIN1A_D14, (M14 | PIN_OUTPUT)}, /* vin1a_d14.gpio3_18 */
819 {VIN1A_D15, (M14 | PIN_OUTPUT)}, /* vin1a_d15.gpio3_19 */
820 {VIN1A_D17, (M14 | PIN_OUTPUT)}, /* vin1a_d17.gpio3_21 */
821 {VIN1A_D18, (M14 | PIN_OUTPUT_PULLDOWN)}, /* vin1a_d18.gpio3_22 */
822 {VIN1A_D19, (M14 | PIN_OUTPUT_PULLUP)}, /* vin1a_d19.gpio3_23 */
823 {VIN1A_D22, (M14 | PIN_INPUT)}, /* vin1a_d22.gpio3_26 */
824 {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
825 {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */
826 {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]827 {VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]828 {VIN2A_VSYNC0, (M14 | PIN_INPUT)}, /* vin2a_vsync0.gpio4_0 */
829 {VIN2A_D0, (M11 | PIN_INPUT)}, /* vin2a_d0.pr1_uart0_rxd */
830 {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */
831 {VIN2A_D2, (M10 | PIN_OUTPUT)}, /* vin2a_d2.eCAP1_in_PWM1_out */
832 {VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_edc_latch0_in */
833 {VIN2A_D4, (M11 | PIN_OUTPUT)}, /* vin2a_d4.pr1_edc_sync0_out */
834 {VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.pr1_pru1_gpo2 */
835 {VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */
836 {VIN2A_D11, (M11 | PIN_INPUT)}, /* vin2a_d11.pr1_mdio_data */
837 {VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
838 {VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
839 {VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
840 {VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
841 {VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
842 {VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]843 {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]844 {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]845 {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
846 {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
847 {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
848 {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]849 {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_clk.vout1_clk */
850 {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_de.vout1_de */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]851 {VOUT1_FLD, (M14 | PIN_OUTPUT)}, /* vout1_fld.gpio4_21 */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]852 {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
853 {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */
854 {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */
855 {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */
856 {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */
857 {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */
858 {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */
859 {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */
860 {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */
861 {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */
862 {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */
863 {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */
864 {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */
865 {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */
866 {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */
867 {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */
868 {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */
869 {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */
870 {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */
871 {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */
872 {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */
873 {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */
874 {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */
875 {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */
876 {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */
877 {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */
878 {MDIO_MCLK, (M0 | PIN_INPUT_SLEW)}, /* mdio_mclk.mdio_mclk */
879 {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]880 {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
881 {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
882 {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
883 {RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
884 {RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
885 {RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]886 {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
887 {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
888 {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
889 {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
890 {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
891 {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]892 {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */
893 {USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]894 {GPIO6_14, (M0 | PIN_OUTPUT)}, /* gpio6_14.gpio6_14 */
895 {GPIO6_15, (M0 | PIN_OUTPUT)}, /* gpio6_15.gpio6_15 */
896 {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]897 {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */
898 {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]899 {XREF_CLK2, (M14 | PIN_OUTPUT)}, /* xref_clk2.gpio6_19 */
900 {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
901 {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]902 {MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.pr2_mdio_data */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]903 {MCASP1_ACLKR, (M14 | PIN_INPUT)}, /* mcasp1_aclkr.gpio5_0 */
904 {MCASP1_FSR, (M14 | PIN_INPUT)}, /* mcasp1_fsr.gpio5_1 */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]905 {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */
906 {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]907 {MCASP1_AXR2, (M14 | PIN_INPUT)}, /* mcasp1_axr2.gpio5_4 */
908 {MCASP1_AXR3, (M14 | PIN_INPUT)}, /* mcasp1_axr3.gpio5_5 */
909 {MCASP1_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp1_axr4.gpio5_6 */
910 {MCASP1_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp1_axr5.gpio5_7 */
911 {MCASP1_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp1_axr6.gpio5_8 */
912 {MCASP1_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp1_axr7.gpio5_9 */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]913 {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr8.pr2_mii0_txen */
914 {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr9.pr2_mii0_txd3 */
915 {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr10.pr2_mii0_txd2 */
916 {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.pr2_mii0_txd1 */
917 {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr12.pr2_mii0_txd0 */
918 {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
919 {MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.pr2_mii0_rxdv */
920 {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]921 {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]922 {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
923 {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
924 {MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.pr2_mii0_rxlink */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]925 {MCASP2_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp2_axr4.gpio1_4 */
926 {MCASP2_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp2_axr5.gpio6_7 */
927 {MCASP2_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp2_axr6.gpio2_29 */
928 {MCASP2_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp2_axr7.gpio1_5 */
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]929 {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]930 {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */
931 {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */
932 {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]933 {MCASP4_ACLKX, (M2 | PIN_INPUT)}, /* mcasp4_aclkx.spi3_sclk */
934 {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]935 {MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]936 {MCASP5_ACLKX, (M13 | PIN_OUTPUT | MANUAL_MODE)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */
937 {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_fsx.pr2_pru1_gpi2 */
938 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]939 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
940 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
941 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
942 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
943 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
944 {MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */
945 {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]946 {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]947 {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
948 {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
949 {MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */
950 {MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
951 {MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]952 {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */
953 {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */
954 {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */
955 {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */
956 {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */
957 {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]958 {SPI1_SCLK, (M14 | PIN_OUTPUT)}, /* spi1_sclk.gpio7_7 */
959 {SPI1_D1, (M14 | PIN_OUTPUT)}, /* spi1_d1.gpio7_8 */
960 {SPI1_D0, (M14 | PIN_OUTPUT)}, /* spi1_d0.gpio7_9 */
961 {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
962 {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]963 {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */
Tomi Valkeinen939a8da2018-06-08 12:51:19 +0300[diff] [blame]964 {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]965 {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */
966 {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d1.spi2_d1 */
967 {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d0.spi2_d0 */
968 {SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]969 {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
970 {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]971 {UART1_RXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */
972 {UART1_TXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_txd.gpio7_23 */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]973 {UART2_RXD, (M4 | PIN_INPUT)}, /* uart2_rxd.uart2_rxd */
974 {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */
975 {UART2_CTSN, (M2 | PIN_INPUT)}, /* uart2_ctsn.uart3_rxd */
976 {UART2_RTSN, (M1 | PIN_OUTPUT)}, /* uart2_rtsn.uart3_txd */
977 {I2C1_SDA, (M0 | PIN_INPUT)}, /* i2c1_sda.i2c1_sda */
978 {I2C1_SCL, (M0 | PIN_INPUT)}, /* i2c1_scl.i2c1_scl */
979 {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
980 {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
981 {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */
982 {WAKEUP1, (M0 | PIN_INPUT)}, /* Wakeup1.Wakeup1 */
983 {WAKEUP2, (M0 | PIN_INPUT)}, /* Wakeup2.Wakeup2 */
984 {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */
985 {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */
986 {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]987 {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]988 {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]989 {TDO, (M0 | PIN_OUTPUT_PULLUP)}, /* tdo.tdo */
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]990 {TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */
991 {TRSTN, (M0 | PIN_INPUT_PULLDOWN)}, /* trstn.trstn */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]992 {RTCK, (M0 | PIN_OUTPUT_PULLUP)}, /* rtck.rtck */
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]993 {EMU0, (M0 | PIN_INPUT_PULLUP)}, /* emu0.emu0 */
994 {EMU1, (M0 | PIN_INPUT_PULLUP)}, /* emu1.emu1 */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]995 {RESETN, (M0 | PIN_INPUT)}, /* resetn.resetn */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]996 {NMIN_DSP, (M0 | PIN_INPUT)}, /* nmin_dsp.nmin_dsp */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]997 {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]998};
999
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530[diff] [blame]1000const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = {
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1001 {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin1b_d0 */
1002 {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin1b_d1 */
1003 {GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a2.vin1b_d2 */
1004 {GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a3.vin1b_d3 */
1005 {GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a4.vin1b_d4 */
1006 {GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a5.vin1b_d5 */
1007 {GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a6.vin1b_d6 */
1008 {GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a7.vin1b_d7 */
1009 {GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a8.vin1b_hsync1 */
1010 {GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a9.vin1b_vsync1 */
1011 {GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a10.vin1b_clk1 */
1012 {GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a11.vin1b_de1 */
1013 {GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a12.vin1b_fld1 */
1014 {GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
1015 {GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
1016 {GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
1017 {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
1018 {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
1019 {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530[diff] [blame]1020 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
1021 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
1022 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
1023 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
1024 {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
1025 {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
1026 {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
1027 {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
1028 {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
1029 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1030 {GPMC_CS0, (M14 | PIN_OUTPUT)}, /* gpmc_cs0.gpio2_19 */
1031 {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
1032 {GPMC_CS3, (M14 | PIN_OUTPUT)}, /* gpmc_cs3.gpio2_21 */
1033 {GPMC_CLK, (M14 | PIN_INPUT)}, /* gpmc_clk.gpio2_22 */
1034 {GPMC_ADVN_ALE, (M14 | PIN_OUTPUT)}, /* gpmc_advn_ale.gpio2_23 */
1035 {GPMC_OEN_REN, (M14 | PIN_OUTPUT)}, /* gpmc_oen_ren.gpio2_24 */
1036 {GPMC_WEN, (M14 | PIN_OUTPUT)}, /* gpmc_wen.gpio2_25 */
1037 {GPMC_BEN0, (M14 | PIN_OUTPUT)}, /* gpmc_ben0.gpio2_26 */
1038 {GPMC_BEN1, (M14 | PIN_OUTPUT)}, /* gpmc_ben1.gpio2_27 */
1039 {GPMC_WAIT0, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* gpmc_wait0.gpio2_28 */
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530[diff] [blame]1040 {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
1041 {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */
1042 {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
1043 {VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1044 {VIN2A_VSYNC0, (M14 | PIN_OUTPUT)}, /* vin2a_vsync0.gpio4_0 */
1045 {VIN2A_D0, (M11 | PIN_INPUT)}, /* vin2a_d0.pr1_uart0_rxd */
1046 {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */
1047 {VIN2A_D2, (M10 | PIN_OUTPUT)}, /* vin2a_d2.eCAP1_in_PWM1_out */
1048 {VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */
1049 {VIN2A_D11, (M11 | PIN_INPUT)}, /* vin2a_d11.pr1_mdio_data */
1050 {VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
1051 {VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
1052 {VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
1053 {VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
1054 {VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
1055 {VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530[diff] [blame]1056 {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1057 {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530[diff] [blame]1058 {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
1059 {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
1060 {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
1061 {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1062 {VOUT1_FLD, (M14 | PIN_OUTPUT)}, /* vout1_fld.gpio4_21 */
1063 {MDIO_MCLK, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
1064 {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */
1065 {UART3_RXD, (M14 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* uart3_rxd.gpio5_18 */
1066 {UART3_TXD, (M14 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* uart3_txd.gpio5_19 */
1067 {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
1068 {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
1069 {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
1070 {RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
1071 {RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
1072 {RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530[diff] [blame]1073 {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1074 {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
1075 {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
1076 {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
1077 {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
1078 {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
1079 {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */
1080 {USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */
1081 {GPIO6_14, (M0 | PIN_OUTPUT)}, /* gpio6_14.gpio6_14 */
1082 {GPIO6_15, (M0 | PIN_OUTPUT)}, /* gpio6_15.gpio6_15 */
1083 {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
1084 {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */
1085 {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */
1086 {XREF_CLK2, (M14 | PIN_OUTPUT)}, /* xref_clk2.gpio6_19 */
1087 {XREF_CLK3, (M7 | PIN_INPUT)}, /* xref_clk3.hdq0 */
1088 {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
1089 {MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.pr2_mdio_data */
1090 {MCASP1_ACLKR, (M14 | PIN_INPUT)}, /* mcasp1_aclkr.gpio5_0 */
1091 {MCASP1_FSR, (M14 | PIN_INPUT)}, /* mcasp1_fsr.gpio5_1 */
1092 {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */
1093 {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
1094 {MCASP1_AXR2, (M14 | PIN_INPUT)}, /* mcasp1_axr2.gpio5_4 */
1095 {MCASP1_AXR3, (M14 | PIN_INPUT)}, /* mcasp1_axr3.gpio5_5 */
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530[diff] [blame]1096 {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1097 {MCASP1_AXR5, (M14 | PIN_INPUT)}, /* mcasp1_axr5.gpio5_7 */
1098 {MCASP1_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp1_axr6.gpio5_8 */
1099 {MCASP1_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp1_axr7.gpio5_9 */
1100 {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr8.pr2_mii0_txen */
1101 {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr9.pr2_mii0_txd3 */
1102 {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr10.pr2_mii0_txd2 */
1103 {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.pr2_mii0_txd1 */
1104 {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr12.pr2_mii0_txd0 */
1105 {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
1106 {MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.pr2_mii0_rxdv */
1107 {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
1108 {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
1109 {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
1110 {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
1111 {MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.pr2_mii0_rxlink */
1112 {MCASP2_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp2_axr4.gpio1_4 */
1113 {MCASP2_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp2_axr5.gpio6_7 */
1114 {MCASP2_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp2_axr6.gpio2_29 */
1115 {MCASP2_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp2_axr7.gpio1_5 */
1116 {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */
1117 {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */
1118 {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */
1119 {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */
1120 {MCASP4_ACLKX, (M2 | PIN_OUTPUT)}, /* mcasp4_aclkx.spi3_sclk */
1121 {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */
1122 {MCASP4_AXR1, (M2 | PIN_OUTPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */
1123 {MCASP5_AXR0, (M4 | PIN_INPUT)}, /* mcasp5_axr0.uart3_rxd */
1124 {MCASP5_AXR1, (M4 | PIN_OUTPUT)}, /* mcasp5_axr1.uart3_txd */
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530[diff] [blame]1125 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
1126 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
1127 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
1128 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
1129 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
1130 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1131 {MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */
1132 {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */
1133 {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */
1134 {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
1135 {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
1136 {MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */
1137 {MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
1138 {MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */
1139 {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530[diff] [blame]1140 {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1141 {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */
1142 {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */
1143 {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */
1144 {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */
1145 {SPI1_SCLK, (M14 | PIN_OUTPUT)}, /* spi1_sclk.gpio7_7 */
1146 {SPI1_D1, (M14 | PIN_OUTPUT)}, /* spi1_d1.gpio7_8 */
1147 {SPI1_D0, (M14 | PIN_OUTPUT)}, /* spi1_d0.gpio7_9 */
1148 {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
1149 {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
1150 {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */
1151 {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
1152 {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */
1153 {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d1.spi2_d1 */
1154 {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d0.spi2_d0 */
1155 {SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530[diff] [blame]1156 {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
1157 {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1158 {UART1_RXD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */
1159 {UART1_CTSN, (M14 | PIN_OUTPUT)}, /* uart1_ctsn.gpio7_24 */
1160 {UART1_RTSN, (M14 | PIN_OUTPUT)}, /* uart1_rtsn.gpio7_25 */
1161 {I2C1_SDA, (M0 | PIN_INPUT)}, /* i2c1_sda.i2c1_sda */
1162 {I2C1_SCL, (M0 | PIN_INPUT)}, /* i2c1_scl.i2c1_scl */
1163 {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
1164 {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
1165 {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */
1166 {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */
1167 {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */
1168 {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530[diff] [blame]1169 {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
1170 {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1171 {TDO, (M0 | PIN_OUTPUT_PULLUP)}, /* tdo.tdo */
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530[diff] [blame]1172 {TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1173 {TRSTN, (M0 | PIN_INPUT)}, /* trstn.trstn */
1174 {RTCK, (M0 | PIN_OUTPUT_PULLUP)}, /* rtck.rtck */
1175 {EMU0, (M0 | PIN_INPUT)}, /* emu0.emu0 */
1176 {EMU1, (M0 | PIN_INPUT)}, /* emu1.emu1 */
1177 {RESETN, (M0 | PIN_INPUT)}, /* resetn.resetn */
1178 {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530[diff] [blame]1179};
1180
Roger Quadros26130592017-03-13 15:04:28 +0200[diff] [blame]1181const struct pad_conf_entry core_padconf_array_icss1eth_am571x_idk[] = {
1182 /* PR1 MII0 */
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1183 {VOUT1_D8, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d8.pr1_mii_mt0_clk */
1184 {VOUT1_D9, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d9.pr1_mii0_txd3 */
1185 {VOUT1_D10, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d10.pr1_mii0_txd2 */
1186 {VOUT1_D11, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d11.pr1_mii0_txen */
1187 {VOUT1_D12, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d12.pr1_mii0_txd1 */
1188 {VOUT1_D13, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d13.pr1_mii0_txd0 */
1189 {VOUT1_D14, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d14.pr1_mii_mr0_clk */
Roger Quadros26130592017-03-13 15:04:28 +0200[diff] [blame]1190 {VOUT1_D15, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.pr1_mii0_rxdv */
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1191 {VOUT1_D16, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.pr1_mii0_rxd3 */
1192 {VOUT1_D17, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.pr1_mii0_rxd2 */
1193 {VOUT1_D18, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.pr1_mii0_rxd1 */
1194 {VOUT1_D19, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.pr1_mii0_rxd0 */
Roger Quadros26130592017-03-13 15:04:28 +0200[diff] [blame]1195 {VOUT1_D20, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d20.pr1_mii0_rxer */
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1196 {VOUT1_D21, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.pr1_mii0_rxlink */
1197 {VOUT1_D22, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.pr1_mii0_col */
1198 {VOUT1_D23, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.pr1_mii0_crs */
Roger Quadros26130592017-03-13 15:04:28 +0200[diff] [blame]1199
1200 /* PR1 MII1 */
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1201 {VIN2A_D3, (M12 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_mii1_col */
1202 {VIN2A_D4, (M13 | PIN_OUTPUT_PULLUP)}, /* vin2a_d4.pr1_mii1_txd1 */
1203 {VIN2A_D5, (M13 | PIN_OUTPUT_PULLUP)}, /* vin2a_d5.pr1_mii1_txd0 */
1204 {VIN2A_D6, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_d6.pr1_mii_mt1_clk */
1205 {VIN2A_D7, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_d7.pr1_mii1_txen */
1206 {VIN2A_D8, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_d8.pr1_mii1_txd3 */
1207 {VIN2A_D9, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_d9.pr1_mii1_txd2 */
Roger Quadros26130592017-03-13 15:04:28 +0200[diff] [blame]1208 {VOUT1_VSYNC, (M12 | PIN_INPUT_PULLUP)}, /* vout1_vsync.pr1_mii1_rxer */
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1209 {VOUT1_D0, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d0.pr1_mii1_rxlink */
1210 {VOUT1_D1, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.pr1_mii1_crs */
1211 {VOUT1_D2, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d2.pr1_mii_mr1_clk */
Roger Quadros26130592017-03-13 15:04:28 +0200[diff] [blame]1212 {VOUT1_D3, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.pr1_mii1_rxdv */
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1213 {VOUT1_D4, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.pr1_mii1_rxd3 */
1214 {VOUT1_D5, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.pr1_mii1_rxd2 */
1215 {VOUT1_D6, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.pr1_mii1_rxd1 */
1216 {VOUT1_D7, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.pr1_mii1_rxd0 */
Roger Quadros26130592017-03-13 15:04:28 +0200[diff] [blame]1217};
1218
1219const struct pad_conf_entry core_padconf_array_vout_am571x_idk[] = {
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1220 {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_clk.vout1_clk */
1221 {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_de.vout1_de */
1222 {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_hsync.vout1_hsync */
1223 {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_vsync.vout1_vsync */
1224 {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d0.vout1_d0 */
1225 {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d1.vout1_d1 */
1226 {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d2.vout1_d2 */
1227 {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d3.vout1_d3 */
1228 {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d4.vout1_d4 */
1229 {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d5.vout1_d5 */
1230 {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d6.vout1_d6 */
1231 {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d7.vout1_d7 */
1232 {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d8.vout1_d8 */
1233 {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d9.vout1_d9 */
1234 {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d10.vout1_d10 */
1235 {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d11.vout1_d11 */
1236 {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d12.vout1_d12 */
1237 {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d13.vout1_d13 */
1238 {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d14.vout1_d14 */
1239 {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d15.vout1_d15 */
1240 {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d16.vout1_d16 */
1241 {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d17.vout1_d17 */
1242 {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d18.vout1_d18 */
1243 {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d19.vout1_d19 */
1244 {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d20.vout1_d20 */
1245 {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d21.vout1_d21 */
1246 {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d22.vout1_d22 */
1247 {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d23.vout1_d23 */
1248
1249 {MCASP5_ACLKX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_aclkx.pr2_pru1_gpi1 */
1250 {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_fsx.pr2_pru1_gpi2 */
1251 {UART2_RXD, (M0 | PIN_INPUT)}, /* uart2_rxd.uart2_rxd */
1252 {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */
1253 {VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.pr1_pru1_gpo2 */
Roger Quadros26130592017-03-13 15:04:28 +0200[diff] [blame]1254};
1255
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]1256const struct pad_conf_entry early_padconf[] = {
1257 {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */
1258 {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
1259 {I2C1_SDA, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SDA */
1260 {I2C1_SCL, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SCL */
Caleb Robey61143db2020-01-02 08:17:26 -0600[diff] [blame]1261
1262 /* BeagleBone AI: Debug UART */
1263 {UART1_RXD, (M0 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
1264 {UART1_TXD, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]1265};
1266
Caleb Robey0dfcc932020-01-02 08:17:25 -0600[diff] [blame]1267#ifdef CONFIG_SUPPORT_EMMC_BOOT
1268const struct pad_conf_entry emmc_padconf[] = {
1269 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* K7: gpmc_a19.mmc2_dat4 */
1270 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* M7: gpmc_a20.mmc2_dat5 */
1271 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* J5: gpmc_a21.mmc2_dat6 */
1272 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* K6: gpmc_a22.mmc2_dat7 */
1273 {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* J7: gpmc_a23.mmc2_clk */
1274 {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* J4: gpmc_a24.mmc2_dat0 */
1275 {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* J6: gpmc_a25.mmc2_dat1 */
1276 {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* H4: gpmc_a26.mmc2_dat2 */
1277 {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* H5: gpmc_a27.mmc2_dat3 */
1278 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* H6: gpmc_cs1.mmc2_cmd */
1279 {MCASP1_AXR5, (M14 | PIN_OUTPUT_PULLUP)}, /* F13: eMMC_RSTn (missing on schematic): mcasp1_axr5.gpio5_7 */
1280};
1281#endif
1282
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]1283#ifdef CONFIG_IODELAY_RECALIBRATION
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]1284const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr1_1[] = {
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]1285 {0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */
1286 {0x0120, 2648, 0}, /* CFG_GPMC_A10_IN */
1287 {0x012C, 2918, 0}, /* CFG_GPMC_A11_IN */
1288 {0x0198, 2917, 0}, /* CFG_GPMC_A1_IN */
1289 {0x0204, 3156, 178}, /* CFG_GPMC_A2_IN */
1290 {0x0210, 3109, 246}, /* CFG_GPMC_A3_IN */
1291 {0x021C, 3142, 100}, /* CFG_GPMC_A4_IN */
1292 {0x0228, 3084, 33}, /* CFG_GPMC_A5_IN */
1293 {0x0234, 2778, 0}, /* CFG_GPMC_A6_IN */
1294 {0x0240, 3110, 0}, /* CFG_GPMC_A7_IN */
1295 {0x024C, 2874, 0}, /* CFG_GPMC_A8_IN */
1296 {0x0258, 3072, 0}, /* CFG_GPMC_A9_IN */
1297 {0x0264, 2466, 0}, /* CFG_GPMC_AD0_IN */
1298 {0x0270, 2523, 0}, /* CFG_GPMC_AD10_IN */
1299 {0x027C, 2453, 0}, /* CFG_GPMC_AD11_IN */
1300 {0x0288, 2285, 0}, /* CFG_GPMC_AD12_IN */
1301 {0x0294, 2206, 0}, /* CFG_GPMC_AD13_IN */
1302 {0x02A0, 1898, 0}, /* CFG_GPMC_AD14_IN */
1303 {0x02AC, 2473, 0}, /* CFG_GPMC_AD15_IN */
1304 {0x02B8, 2307, 0}, /* CFG_GPMC_AD1_IN */
1305 {0x02C4, 2691, 0}, /* CFG_GPMC_AD2_IN */
1306 {0x02D0, 2384, 0}, /* CFG_GPMC_AD3_IN */
1307 {0x02DC, 2462, 0}, /* CFG_GPMC_AD4_IN */
1308 {0x02E8, 2335, 0}, /* CFG_GPMC_AD5_IN */
1309 {0x02F4, 2370, 0}, /* CFG_GPMC_AD6_IN */
1310 {0x0300, 2389, 0}, /* CFG_GPMC_AD7_IN */
1311 {0x030C, 2672, 0}, /* CFG_GPMC_AD8_IN */
1312 {0x0318, 2334, 0}, /* CFG_GPMC_AD9_IN */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]1313 {0x0378, 0, 0}, /* CFG_GPMC_CS3_IN */
1314 {0x0678, 406, 0}, /* CFG_MMC3_CLK_IN */
1315 {0x0680, 659, 0}, /* CFG_MMC3_CLK_OUT */
1316 {0x0684, 0, 0}, /* CFG_MMC3_CMD_IN */
1317 {0x0688, 0, 0}, /* CFG_MMC3_CMD_OEN */
1318 {0x068C, 0, 0}, /* CFG_MMC3_CMD_OUT */
1319 {0x0690, 130, 0}, /* CFG_MMC3_DAT0_IN */
1320 {0x0694, 0, 0}, /* CFG_MMC3_DAT0_OEN */
1321 {0x0698, 0, 0}, /* CFG_MMC3_DAT0_OUT */
1322 {0x069C, 169, 0}, /* CFG_MMC3_DAT1_IN */
1323 {0x06A0, 0, 0}, /* CFG_MMC3_DAT1_OEN */
1324 {0x06A4, 0, 0}, /* CFG_MMC3_DAT1_OUT */
1325 {0x06A8, 0, 0}, /* CFG_MMC3_DAT2_IN */
1326 {0x06AC, 0, 0}, /* CFG_MMC3_DAT2_OEN */
1327 {0x06B0, 0, 0}, /* CFG_MMC3_DAT2_OUT */
1328 {0x06B4, 457, 0}, /* CFG_MMC3_DAT3_IN */
1329 {0x06B8, 0, 0}, /* CFG_MMC3_DAT3_OEN */
1330 {0x06BC, 0, 0}, /* CFG_MMC3_DAT3_OUT */
1331 {0x06C0, 702, 0}, /* CFG_MMC3_DAT4_IN */
1332 {0x06C4, 0, 0}, /* CFG_MMC3_DAT4_OEN */
1333 {0x06C8, 0, 0}, /* CFG_MMC3_DAT4_OUT */
1334 {0x06CC, 738, 0}, /* CFG_MMC3_DAT5_IN */
1335 {0x06D0, 0, 0}, /* CFG_MMC3_DAT5_OEN */
1336 {0x06D4, 0, 0}, /* CFG_MMC3_DAT5_OUT */
1337 {0x06D8, 856, 0}, /* CFG_MMC3_DAT6_IN */
1338 {0x06DC, 0, 0}, /* CFG_MMC3_DAT6_OEN */
1339 {0x06E0, 0, 0}, /* CFG_MMC3_DAT6_OUT */
1340 {0x06E4, 610, 0}, /* CFG_MMC3_DAT7_IN */
1341 {0x06E8, 0, 0}, /* CFG_MMC3_DAT7_OEN */
1342 {0x06EC, 0, 0}, /* CFG_MMC3_DAT7_OUT */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]1343 {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
1344 {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
1345 {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
1346 {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */
1347 {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */
1348 {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */
1349 {0x0740, 531, 120}, /* CFG_RGMII0_TXC_OUT */
Nishanth Menon951e5322016-11-25 11:14:21 +0530[diff] [blame]1350 {0x074C, 201, 60}, /* CFG_RGMII0_TXCTL_OUT */
1351 {0x0758, 229, 120}, /* CFG_RGMII0_TXD0_OUT */
1352 {0x0764, 141, 0}, /* CFG_RGMII0_TXD1_OUT */
1353 {0x0770, 495, 120}, /* CFG_RGMII0_TXD2_OUT */
1354 {0x077C, 660, 120}, /* CFG_RGMII0_TXD3_OUT */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]1355 {0x0A70, 1551, 115}, /* CFG_VIN2A_D12_OUT */
1356 {0x0A7C, 816, 0}, /* CFG_VIN2A_D13_OUT */
1357 {0x0A88, 876, 0}, /* CFG_VIN2A_D14_OUT */
1358 {0x0A94, 312, 0}, /* CFG_VIN2A_D15_OUT */
1359 {0x0AA0, 58, 0}, /* CFG_VIN2A_D16_OUT */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]1360 {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]1361 {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */
1362 {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */
1363 {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
1364 {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
1365 {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
1366 {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
Felipe Balbi4750eb62014-11-10 14:02:44 -0600[diff] [blame]1367};
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]1368
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]1369const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr2_0[] = {
1370 {0x0114, 2519, 702}, /* CFG_GPMC_A0_IN */
1371 {0x0120, 2435, 411}, /* CFG_GPMC_A10_IN */
1372 {0x012C, 2379, 755}, /* CFG_GPMC_A11_IN */
1373 {0x0198, 2384, 778}, /* CFG_GPMC_A1_IN */
1374 {0x0204, 2499, 1127}, /* CFG_GPMC_A2_IN */
1375 {0x0210, 2455, 1181}, /* CFG_GPMC_A3_IN */
1376 {0x021C, 2486, 1039}, /* CFG_GPMC_A4_IN */
1377 {0x0228, 2456, 938}, /* CFG_GPMC_A5_IN */
1378 {0x0234, 2463, 573}, /* CFG_GPMC_A6_IN */
1379 {0x0240, 2608, 783}, /* CFG_GPMC_A7_IN */
1380 {0x024C, 2430, 656}, /* CFG_GPMC_A8_IN */
1381 {0x0258, 2465, 850}, /* CFG_GPMC_A9_IN */
1382 {0x0264, 2316, 301}, /* CFG_GPMC_AD0_IN */
1383 {0x0270, 2324, 406}, /* CFG_GPMC_AD10_IN */
1384 {0x027C, 2278, 352}, /* CFG_GPMC_AD11_IN */
1385 {0x0288, 2297, 160}, /* CFG_GPMC_AD12_IN */
1386 {0x0294, 2278, 108}, /* CFG_GPMC_AD13_IN */
1387 {0x02A0, 2035, 0}, /* CFG_GPMC_AD14_IN */
1388 {0x02AC, 2279, 378}, /* CFG_GPMC_AD15_IN */
1389 {0x02B8, 2440, 70}, /* CFG_GPMC_AD1_IN */
1390 {0x02C4, 2404, 446}, /* CFG_GPMC_AD2_IN */
1391 {0x02D0, 2343, 212}, /* CFG_GPMC_AD3_IN */
1392 {0x02DC, 2355, 322}, /* CFG_GPMC_AD4_IN */
1393 {0x02E8, 2337, 192}, /* CFG_GPMC_AD5_IN */
1394 {0x02F4, 2270, 314}, /* CFG_GPMC_AD6_IN */
1395 {0x0300, 2339, 259}, /* CFG_GPMC_AD7_IN */
1396 {0x030C, 2308, 577}, /* CFG_GPMC_AD8_IN */
1397 {0x0318, 2334, 166}, /* CFG_GPMC_AD9_IN */
1398 {0x0378, 0, 0}, /* CFG_GPMC_CS3_IN */
1399 {0x0678, 0, 386}, /* CFG_MMC3_CLK_IN */
1400 {0x0680, 605, 0}, /* CFG_MMC3_CLK_OUT */
1401 {0x0684, 0, 0}, /* CFG_MMC3_CMD_IN */
1402 {0x0688, 0, 0}, /* CFG_MMC3_CMD_OEN */
1403 {0x068C, 0, 0}, /* CFG_MMC3_CMD_OUT */
1404 {0x0690, 171, 0}, /* CFG_MMC3_DAT0_IN */
1405 {0x0694, 0, 0}, /* CFG_MMC3_DAT0_OEN */
1406 {0x0698, 0, 0}, /* CFG_MMC3_DAT0_OUT */
1407 {0x069C, 221, 0}, /* CFG_MMC3_DAT1_IN */
1408 {0x06A0, 0, 0}, /* CFG_MMC3_DAT1_OEN */
1409 {0x06A4, 0, 0}, /* CFG_MMC3_DAT1_OUT */
1410 {0x06A8, 0, 0}, /* CFG_MMC3_DAT2_IN */
1411 {0x06AC, 0, 0}, /* CFG_MMC3_DAT2_OEN */
1412 {0x06B0, 0, 0}, /* CFG_MMC3_DAT2_OUT */
1413 {0x06B4, 474, 0}, /* CFG_MMC3_DAT3_IN */
1414 {0x06B8, 0, 0}, /* CFG_MMC3_DAT3_OEN */
1415 {0x06BC, 0, 0}, /* CFG_MMC3_DAT3_OUT */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]1416 {0x06C0, 792, 0}, /* CFG_MMC3_DAT4_IN */
1417 {0x06C4, 0, 0}, /* CFG_MMC3_DAT4_OEN */
1418 {0x06C8, 0, 0}, /* CFG_MMC3_DAT4_OUT */
1419 {0x06CC, 782, 0}, /* CFG_MMC3_DAT5_IN */
1420 {0x06D0, 0, 0}, /* CFG_MMC3_DAT5_OEN */
1421 {0x06D4, 0, 0}, /* CFG_MMC3_DAT5_OUT */
1422 {0x06D8, 942, 0}, /* CFG_MMC3_DAT6_IN */
1423 {0x06DC, 0, 0}, /* CFG_MMC3_DAT6_OEN */
1424 {0x06E0, 0, 0}, /* CFG_MMC3_DAT6_OUT */
1425 {0x06E4, 636, 0}, /* CFG_MMC3_DAT7_IN */
1426 {0x06E8, 0, 0}, /* CFG_MMC3_DAT7_OEN */
1427 {0x06EC, 0, 0}, /* CFG_MMC3_DAT7_OUT */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]1428 {0x06F0, 260, 0}, /* CFG_RGMII0_RXC_IN */
1429 {0x06FC, 0, 1412}, /* CFG_RGMII0_RXCTL_IN */
1430 {0x0708, 123, 1047}, /* CFG_RGMII0_RXD0_IN */
1431 {0x0714, 139, 1081}, /* CFG_RGMII0_RXD1_IN */
1432 {0x0720, 195, 1100}, /* CFG_RGMII0_RXD2_IN */
1433 {0x072C, 239, 1216}, /* CFG_RGMII0_RXD3_IN */
1434 {0x0740, 89, 0}, /* CFG_RGMII0_TXC_OUT */
1435 {0x074C, 15, 125}, /* CFG_RGMII0_TXCTL_OUT */
1436 {0x0758, 339, 162}, /* CFG_RGMII0_TXD0_OUT */
1437 {0x0764, 146, 94}, /* CFG_RGMII0_TXD1_OUT */
1438 {0x0770, 0, 27}, /* CFG_RGMII0_TXD2_OUT */
1439 {0x077C, 291, 205}, /* CFG_RGMII0_TXD3_OUT */
1440 {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
1441 {0x0A7C, 219, 101}, /* CFG_VIN2A_D13_OUT */
1442 {0x0A88, 92, 58}, /* CFG_VIN2A_D14_OUT */
1443 {0x0A94, 135, 100}, /* CFG_VIN2A_D15_OUT */
1444 {0x0AA0, 154, 101}, /* CFG_VIN2A_D16_OUT */
1445 {0x0AAC, 78, 27}, /* CFG_VIN2A_D17_OUT */
1446 {0x0AB0, 411, 0}, /* CFG_VIN2A_D18_IN */
1447 {0x0ABC, 0, 382}, /* CFG_VIN2A_D19_IN */
1448 {0x0AD4, 320, 750}, /* CFG_VIN2A_D20_IN */
1449 {0x0AE0, 192, 836}, /* CFG_VIN2A_D21_IN */
1450 {0x0AEC, 294, 669}, /* CFG_VIN2A_D22_IN */
1451 {0x0AF8, 50, 700}, /* CFG_VIN2A_D23_IN */
Lokesh Vutla1ffdc002017-06-05 14:48:17 +0530[diff] [blame]1452 {0x0B9C, 0, 706}, /* CFG_VOUT1_CLK_OUT */
1453 {0x0BA8, 2313, 0}, /* CFG_VOUT1_D0_OUT */
1454 {0x0BB4, 2199, 0}, /* CFG_VOUT1_D10_OUT */
1455 {0x0BC0, 2266, 0}, /* CFG_VOUT1_D11_OUT */
1456 {0x0BCC, 3159, 0}, /* CFG_VOUT1_D12_OUT */
1457 {0x0BD8, 2100, 0}, /* CFG_VOUT1_D13_OUT */
1458 {0x0BE4, 2229, 0}, /* CFG_VOUT1_D14_OUT */
1459 {0x0BF0, 2202, 0}, /* CFG_VOUT1_D15_OUT */
1460 {0x0BFC, 2084, 0}, /* CFG_VOUT1_D16_OUT */
1461 {0x0C08, 2195, 0}, /* CFG_VOUT1_D17_OUT */
1462 {0x0C14, 2342, 0}, /* CFG_VOUT1_D18_OUT */
1463 {0x0C20, 2463, 0}, /* CFG_VOUT1_D19_OUT */
1464 {0x0C2C, 2439, 0}, /* CFG_VOUT1_D1_OUT */
1465 {0x0C38, 2304, 0}, /* CFG_VOUT1_D20_OUT */
1466 {0x0C44, 2103, 0}, /* CFG_VOUT1_D21_OUT */
1467 {0x0C50, 2145, 0}, /* CFG_VOUT1_D22_OUT */
1468 {0x0C5C, 1932, 0}, /* CFG_VOUT1_D23_OUT */
1469 {0x0C68, 2200, 0}, /* CFG_VOUT1_D2_OUT */
1470 {0x0C74, 2355, 0}, /* CFG_VOUT1_D3_OUT */
1471 {0x0C80, 3215, 0}, /* CFG_VOUT1_D4_OUT */
1472 {0x0C8C, 2314, 0}, /* CFG_VOUT1_D5_OUT */
1473 {0x0C98, 2238, 0}, /* CFG_VOUT1_D6_OUT */
1474 {0x0CA4, 2381, 0}, /* CFG_VOUT1_D7_OUT */
1475 {0x0CB0, 2138, 0}, /* CFG_VOUT1_D8_OUT */
1476 {0x0CBC, 2383, 0}, /* CFG_VOUT1_D9_OUT */
1477 {0x0CC8, 1984, 0}, /* CFG_VOUT1_DE_OUT */
1478 {0x0CE0, 1947, 0}, /* CFG_VOUT1_HSYNC_OUT */
1479 {0x0CEC, 2739, 0}, /* CFG_VOUT1_VSYNC_OUT */
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530[diff] [blame]1480};
1481
Lokesh Vutla1e3425c2017-12-29 11:47:55 +0530[diff] [blame]1482const struct iodelay_cfg_entry iodelay_cfg_array_am574x_idk[] = {
1483 {0x0114, 2199, 621}, /* CFG_GPMC_A0_IN */
1484 {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */
1485 {0x012C, 2133, 859}, /* CFG_GPMC_A11_IN */
1486 {0x0138, 2258, 562}, /* CFG_GPMC_A12_IN */
1487 {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
1488 {0x0150, 2149, 1052}, /* CFG_GPMC_A14_IN */
1489 {0x015C, 2121, 997}, /* CFG_GPMC_A15_IN */
1490 {0x0168, 2159, 1134}, /* CFG_GPMC_A16_IN */
1491 {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
1492 {0x0174, 2135, 1085}, /* CFG_GPMC_A17_IN */
1493 {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
1494 {0x0198, 1989, 612}, /* CFG_GPMC_A1_IN */
1495 {0x0204, 2218, 912}, /* CFG_GPMC_A2_IN */
1496 {0x0210, 2168, 963}, /* CFG_GPMC_A3_IN */
1497 {0x021C, 2196, 813}, /* CFG_GPMC_A4_IN */
1498 {0x0228, 2082, 782}, /* CFG_GPMC_A5_IN */
1499 {0x0234, 2098, 407}, /* CFG_GPMC_A6_IN */
1500 {0x0240, 2343, 585}, /* CFG_GPMC_A7_IN */
1501 {0x024C, 2030, 685}, /* CFG_GPMC_A8_IN */
1502 {0x0258, 2116, 832}, /* CFG_GPMC_A9_IN */
1503 {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
1504 {0x0590, 1000, 3900}, /* CFG_MCASP5_ACLKX_OUT */
1505 {0x05AC, 1000, 3800}, /* CFG_MCASP5_FSX_IN */
1506 {0x06F0, 451, 0}, /* CFG_RGMII0_RXC_IN */
1507 {0x06FC, 127, 1571}, /* CFG_RGMII0_RXCTL_IN */
1508 {0x0708, 165, 1178}, /* CFG_RGMII0_RXD0_IN */
1509 {0x0714, 136, 1302}, /* CFG_RGMII0_RXD1_IN */
1510 {0x0720, 0, 1520}, /* CFG_RGMII0_RXD2_IN */
1511 {0x072C, 28, 1690}, /* CFG_RGMII0_RXD3_IN */
1512 {0x0740, 121, 0}, /* CFG_RGMII0_TXC_OUT */
1513 {0x074C, 60, 0}, /* CFG_RGMII0_TXCTL_OUT */
1514 {0x0758, 153, 0}, /* CFG_RGMII0_TXD0_OUT */
1515 {0x0764, 35, 0}, /* CFG_RGMII0_TXD1_OUT */
1516 {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */
1517 {0x077C, 172, 0}, /* CFG_RGMII0_TXD3_OUT */
1518 {0x0A70, 147, 0}, /* CFG_VIN2A_D12_OUT */
1519 {0x0A7C, 110, 0}, /* CFG_VIN2A_D13_OUT */
1520 {0x0A88, 18, 0}, /* CFG_VIN2A_D14_OUT */
1521 {0x0A94, 82, 0}, /* CFG_VIN2A_D15_OUT */
1522 {0x0AA0, 33, 0}, /* CFG_VIN2A_D16_OUT */
1523 {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
1524 {0x0AB0, 417, 0}, /* CFG_VIN2A_D18_IN */
1525 {0x0ABC, 156, 843}, /* CFG_VIN2A_D19_IN */
1526 {0x0AD4, 223, 1413}, /* CFG_VIN2A_D20_IN */
1527 {0x0AE0, 169, 1415}, /* CFG_VIN2A_D21_IN */
1528 {0x0AEC, 43, 1150}, /* CFG_VIN2A_D22_IN */
1529 {0x0AF8, 0, 1210}, /* CFG_VIN2A_D23_IN */
1530 {0x0B30, 0, 200}, /* CFG_VIN2A_D5_OUT */
1531 {0x0B9C, 1281, 497}, /* CFG_VOUT1_CLK_OUT */
1532 {0x0BA8, 379, 0}, /* CFG_VOUT1_D0_OUT */
1533 {0x0BB4, 441, 0}, /* CFG_VOUT1_D10_OUT */
1534 {0x0BC0, 461, 0}, /* CFG_VOUT1_D11_OUT */
1535 {0x0BCC, 1189, 0}, /* CFG_VOUT1_D12_OUT */
1536 {0x0BD8, 312, 0}, /* CFG_VOUT1_D13_OUT */
1537 {0x0BE4, 298, 0}, /* CFG_VOUT1_D14_OUT */
1538 {0x0BF0, 284, 0}, /* CFG_VOUT1_D15_OUT */
1539 {0x0BFC, 152, 0}, /* CFG_VOUT1_D16_OUT */
1540 {0x0C08, 216, 0}, /* CFG_VOUT1_D17_OUT */
1541 {0x0C14, 408, 0}, /* CFG_VOUT1_D18_OUT */
1542 {0x0C20, 519, 0}, /* CFG_VOUT1_D19_OUT */
1543 {0x0C2C, 475, 0}, /* CFG_VOUT1_D1_OUT */
1544 {0x0C38, 316, 0}, /* CFG_VOUT1_D20_OUT */
1545 {0x0C44, 59, 0}, /* CFG_VOUT1_D21_OUT */
1546 {0x0C50, 221, 0}, /* CFG_VOUT1_D22_OUT */
1547 {0x0C5C, 96, 0}, /* CFG_VOUT1_D23_OUT */
1548 {0x0C68, 264, 0}, /* CFG_VOUT1_D2_OUT */
1549 {0x0C74, 421, 0}, /* CFG_VOUT1_D3_OUT */
1550 {0x0C80, 1257, 0}, /* CFG_VOUT1_D4_OUT */
1551 {0x0C8C, 432, 0}, /* CFG_VOUT1_D5_OUT */
1552 {0x0C98, 436, 0}, /* CFG_VOUT1_D6_OUT */
1553 {0x0CA4, 440, 0}, /* CFG_VOUT1_D7_OUT */
1554 {0x0CB0, 81, 100}, /* CFG_VOUT1_D8_OUT */
1555 {0x0CBC, 471, 0}, /* CFG_VOUT1_D9_OUT */
1556 {0x0CC8, 0, 0}, /* CFG_VOUT1_DE_OUT */
1557 {0x0CE0, 0, 0}, /* CFG_VOUT1_HSYNC_OUT */
1558 {0x0CEC, 815, 0}, /* CFG_VOUT1_VSYNC_OUT */
1559};
1560
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]1561const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = {
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]1562 {0x0114, 1861, 901}, /* CFG_GPMC_A0_IN */
1563 {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */
1564 {0x012C, 1783, 1178}, /* CFG_GPMC_A11_IN */
1565 {0x0138, 1903, 853}, /* CFG_GPMC_A12_IN */
1566 {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
1567 {0x0150, 2575, 966}, /* CFG_GPMC_A14_IN */
1568 {0x015C, 2503, 889}, /* CFG_GPMC_A15_IN */
1569 {0x0168, 2528, 1007}, /* CFG_GPMC_A16_IN */
1570 {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
1571 {0x0174, 2533, 980}, /* CFG_GPMC_A17_IN */
1572 {0x0188, 590, 0}, /* CFG_GPMC_A18_OUT */
1573 {0x0198, 1652, 891}, /* CFG_GPMC_A1_IN */
1574 {0x0204, 1888, 1212}, /* CFG_GPMC_A2_IN */
1575 {0x0210, 1839, 1274}, /* CFG_GPMC_A3_IN */
1576 {0x021C, 1868, 1113}, /* CFG_GPMC_A4_IN */
1577 {0x0228, 1757, 1079}, /* CFG_GPMC_A5_IN */
1578 {0x0234, 1800, 670}, /* CFG_GPMC_A6_IN */
1579 {0x0240, 1967, 898}, /* CFG_GPMC_A7_IN */
1580 {0x024C, 1731, 959}, /* CFG_GPMC_A8_IN */
1581 {0x0258, 1766, 1150}, /* CFG_GPMC_A9_IN */
1582 {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
1583 {0x0590, 1000, 4200}, /* CFG_MCASP5_ACLKX_OUT */
1584 {0x05AC, 800, 3800}, /* CFG_MCASP5_FSX_IN */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]1585 {0x06F0, 260, 0}, /* CFG_RGMII0_RXC_IN */
1586 {0x06FC, 0, 1412}, /* CFG_RGMII0_RXCTL_IN */
1587 {0x0708, 123, 1047}, /* CFG_RGMII0_RXD0_IN */
1588 {0x0714, 139, 1081}, /* CFG_RGMII0_RXD1_IN */
1589 {0x0720, 195, 1100}, /* CFG_RGMII0_RXD2_IN */
1590 {0x072C, 239, 1216}, /* CFG_RGMII0_RXD3_IN */
1591 {0x0740, 89, 0}, /* CFG_RGMII0_TXC_OUT */
1592 {0x074C, 15, 125}, /* CFG_RGMII0_TXCTL_OUT */
1593 {0x0758, 339, 162}, /* CFG_RGMII0_TXD0_OUT */
1594 {0x0764, 146, 94}, /* CFG_RGMII0_TXD1_OUT */
1595 {0x0770, 0, 27}, /* CFG_RGMII0_TXD2_OUT */
1596 {0x077C, 291, 205}, /* CFG_RGMII0_TXD3_OUT */
1597 {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
1598 {0x0A7C, 219, 101}, /* CFG_VIN2A_D13_OUT */
1599 {0x0A88, 92, 58}, /* CFG_VIN2A_D14_OUT */
1600 {0x0A94, 135, 100}, /* CFG_VIN2A_D15_OUT */
1601 {0x0AA0, 154, 101}, /* CFG_VIN2A_D16_OUT */
1602 {0x0AAC, 78, 27}, /* CFG_VIN2A_D17_OUT */
1603 {0x0AB0, 411, 0}, /* CFG_VIN2A_D18_IN */
1604 {0x0ABC, 0, 382}, /* CFG_VIN2A_D19_IN */
1605 {0x0AD4, 320, 750}, /* CFG_VIN2A_D20_IN */
1606 {0x0AE0, 192, 836}, /* CFG_VIN2A_D21_IN */
1607 {0x0AEC, 294, 669}, /* CFG_VIN2A_D22_IN */
1608 {0x0AF8, 50, 700}, /* CFG_VIN2A_D23_IN */
Lokesh Vutla691b8822016-11-25 11:14:23 +0530[diff] [blame]1609 {0x0B30, 0, 0}, /* CFG_VIN2A_D5_OUT */
Lokesh Vutla3a3de612017-06-05 14:48:15 +0530[diff] [blame]1610 {0x0B9C, 1126, 751}, /* CFG_VOUT1_CLK_OUT */
1611 {0x0BA8, 395, 0}, /* CFG_VOUT1_D0_OUT */
1612 {0x0BB4, 282, 0}, /* CFG_VOUT1_D10_OUT */
1613 {0x0BC0, 348, 0}, /* CFG_VOUT1_D11_OUT */
1614 {0x0BCC, 1240, 0}, /* CFG_VOUT1_D12_OUT */
1615 {0x0BD8, 182, 0}, /* CFG_VOUT1_D13_OUT */
1616 {0x0BE4, 311, 0}, /* CFG_VOUT1_D14_OUT */
1617 {0x0BF0, 285, 0}, /* CFG_VOUT1_D15_OUT */
1618 {0x0BFC, 166, 0}, /* CFG_VOUT1_D16_OUT */
1619 {0x0C08, 278, 0}, /* CFG_VOUT1_D17_OUT */
1620 {0x0C14, 425, 0}, /* CFG_VOUT1_D18_OUT */
1621 {0x0C20, 516, 0}, /* CFG_VOUT1_D19_OUT */
1622 {0x0C2C, 521, 0}, /* CFG_VOUT1_D1_OUT */
1623 {0x0C38, 386, 0}, /* CFG_VOUT1_D20_OUT */
1624 {0x0C44, 111, 0}, /* CFG_VOUT1_D21_OUT */
1625 {0x0C50, 227, 0}, /* CFG_VOUT1_D22_OUT */
1626 {0x0C5C, 0, 0}, /* CFG_VOUT1_D23_OUT */
1627 {0x0C68, 282, 0}, /* CFG_VOUT1_D2_OUT */
1628 {0x0C74, 438, 0}, /* CFG_VOUT1_D3_OUT */
1629 {0x0C80, 1298, 0}, /* CFG_VOUT1_D4_OUT */
1630 {0x0C8C, 397, 0}, /* CFG_VOUT1_D5_OUT */
1631 {0x0C98, 321, 0}, /* CFG_VOUT1_D6_OUT */
1632 {0x0CA4, 155, 309}, /* CFG_VOUT1_D7_OUT */
1633 {0x0CB0, 212, 0}, /* CFG_VOUT1_D8_OUT */
1634 {0x0CBC, 466, 0}, /* CFG_VOUT1_D9_OUT */
1635 {0x0CC8, 0, 0}, /* CFG_VOUT1_DE_OUT */
1636 {0x0CE0, 0, 0}, /* CFG_VOUT1_HSYNC_OUT */
1637 {0x0CEC, 139, 701}, /* CFG_VOUT1_VSYNC_OUT */
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500[diff] [blame]1638};
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530[diff] [blame]1639
1640const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk[] = {
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1641 {0x0114, 1873, 702}, /* CFG_GPMC_A0_IN */
1642 {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */
1643 {0x012C, 1851, 1011}, /* CFG_GPMC_A11_IN */
1644 {0x0138, 2009, 601}, /* CFG_GPMC_A12_IN */
1645 {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
1646 {0x0150, 2247, 1186}, /* CFG_GPMC_A14_IN */
1647 {0x015C, 2176, 1197}, /* CFG_GPMC_A15_IN */
1648 {0x0168, 2229, 1268}, /* CFG_GPMC_A16_IN */
1649 {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
1650 {0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */
1651 {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
1652 {0x0198, 1629, 772}, /* CFG_GPMC_A1_IN */
1653 {0x0204, 1734, 898}, /* CFG_GPMC_A2_IN */
1654 {0x0210, 1757, 1076}, /* CFG_GPMC_A3_IN */
1655 {0x021C, 1794, 893}, /* CFG_GPMC_A4_IN */
1656 {0x0228, 1726, 853}, /* CFG_GPMC_A5_IN */
1657 {0x0234, 1792, 612}, /* CFG_GPMC_A6_IN */
1658 {0x0240, 2117, 610}, /* CFG_GPMC_A7_IN */
1659 {0x024C, 1758, 653}, /* CFG_GPMC_A8_IN */
1660 {0x0258, 1705, 899}, /* CFG_GPMC_A9_IN */
1661 {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
1662 {0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */
1663 {0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */
1664 {0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */
1665 {0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */
1666 {0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */
1667 {0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */
1668 {0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */
1669 {0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */
1670 {0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */
1671 {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
1672 {0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */
1673 {0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */
1674 {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
1675 {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */
1676 {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */
1677 {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
1678 {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */
1679 {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */
1680 {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */
1681 {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */
1682 {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */
1683 {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */
1684 {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */
1685 {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530[diff] [blame]1686};
1687
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530[diff] [blame]1688const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk_4port[] = {
1689 {0x0588, 2100, 1959}, /* CFG_MCASP5_ACLKX_IN */
1690 {0x05AC, 2100, 1780}, /* CFG_MCASP5_FSX_IN */
1691 {0x0B30, 0, 400}, /* CFG_VIN2A_D5_OUT */
1692};
Lokesh Vutla8313d5e2015-06-04 16:42:42 +0530[diff] [blame]1693#endif
Felipe Balbi4750eb62014-11-10 14:02:44 -0600[diff] [blame]1694#endif /* _MUX_DATA_BEAGLE_X15_H_ */