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git01.mediatek.com / filogic / uboot / ea7387e170f240bbc8ec2db1e12b5492ede9b853 / . / drivers / phy / cadence / phy-cadence-torrent.c
blob: d4e8ece4935a28b7a730e2a719273e9becc73d96 [file] [log] [blame]
Aswath Govindrajufb2bdb62021-07-21 21:28:37 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Cadence Torrent SD0801 PHY driver.
4 *
5 * Based on the linux driver provided by Cadence
6 *
7 * Copyright (c) 2018 Cadence Design Systems
8 *
9 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
10 *
11 */
12
Aswath Govindrajufb2bdb62021-07-21 21:28:37 +0530[diff] [blame]13#include <clk.h>
14#include <generic-phy.h>
15#include <reset.h>
16#include <dm/device.h>
17#include <dm/device_compat.h>
18#include <dm/device-internal.h>
19#include <dm/lists.h>
20#include <dm/read.h>
21#include <dm/uclass.h>
22#include <linux/io.h>
23#include <dt-bindings/phy/phy.h>
24#include <regmap.h>
25#include <linux/delay.h>
26#include <linux/string.h>
27
28#define REF_CLK_19_2MHz 19200000
29#define REF_CLK_25MHz 25000000
30
31#define MAX_NUM_LANES 4
32#define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps*/
33
34#define NUM_SSC_MODE 3
35#define NUM_PHY_TYPE 6
36
37#define POLL_TIMEOUT_US 5000
38#define PLL_LOCK_TIMEOUT 100000
39
40#define TORRENT_COMMON_CDB_OFFSET 0x0
41
42#define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
43 ((0x4000 << (block_offset)) + \
44 (((ln) << 9) << (reg_offset)))
45#define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
46 ((0x8000 << (block_offset)) + \
47 (((ln) << 9) << (reg_offset)))
48
49#define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \
50 (0xC000 << (block_offset))
51
52#define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \
53 (0xE000 << (block_offset))
54
55/*
56 * register offsets from SD0801 PHY register block base (i.e MHDP
57 * register base + 0x500000)
58 */
59#define CMN_SSM_BANDGAP_TMR 0x0021U
60#define CMN_SSM_BIAS_TMR 0x0022U
61#define CMN_PLLSM0_PLLPRE_TMR 0x002AU
62#define CMN_PLLSM0_PLLLOCK_TMR 0x002CU
63#define CMN_PLLSM1_PLLPRE_TMR 0x0032U
64#define CMN_PLLSM1_PLLLOCK_TMR 0x0034U
65#define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U
66#define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U
67#define CMN_BGCAL_INIT_TMR 0x0064U
68#define CMN_BGCAL_ITER_TMR 0x0065U
69#define CMN_IBCAL_INIT_TMR 0x0074U
70#define CMN_PLL0_VCOCAL_TCTRL 0x0082U
71#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U
72#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U
73#define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U
74#define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U
75#define CMN_PLL0_INTDIV_M0 0x0090U
76#define CMN_PLL0_FRACDIVL_M0 0x0091U
77#define CMN_PLL0_FRACDIVH_M0 0x0092U
78#define CMN_PLL0_HIGH_THR_M0 0x0093U
79#define CMN_PLL0_DSM_DIAG_M0 0x0094U
80#define CMN_PLL0_SS_CTRL1_M0 0x0098U
81#define CMN_PLL0_SS_CTRL2_M0 0x0099U
82#define CMN_PLL0_SS_CTRL3_M0 0x009AU
83#define CMN_PLL0_SS_CTRL4_M0 0x009BU
84#define CMN_PLL0_LOCK_REFCNT_START 0x009CU
85#define CMN_PLL0_LOCK_PLLCNT_START 0x009EU
86#define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU
87#define CMN_PLL0_INTDIV_M1 0x00A0U
88#define CMN_PLL0_FRACDIVH_M1 0x00A2U
89#define CMN_PLL0_HIGH_THR_M1 0x00A3U
90#define CMN_PLL0_DSM_DIAG_M1 0x00A4U
91#define CMN_PLL0_SS_CTRL1_M1 0x00A8U
92#define CMN_PLL0_SS_CTRL2_M1 0x00A9U
93#define CMN_PLL0_SS_CTRL3_M1 0x00AAU
94#define CMN_PLL0_SS_CTRL4_M1 0x00ABU
95#define CMN_PLL1_VCOCAL_TCTRL 0x00C2U
96#define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U
97#define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U
98#define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U
99#define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U
100#define CMN_PLL1_INTDIV_M0 0x00D0U
101#define CMN_PLL1_FRACDIVL_M0 0x00D1U
102#define CMN_PLL1_FRACDIVH_M0 0x00D2U
103#define CMN_PLL1_HIGH_THR_M0 0x00D3U
104#define CMN_PLL1_DSM_DIAG_M0 0x00D4U
105#define CMN_PLL1_DSM_FBH_OVRD_M0 0x00D5U
106#define CMN_PLL1_DSM_FBL_OVRD_M0 0x00D6U
107#define CMN_PLL1_SS_CTRL1_M0 0x00D8U
108#define CMN_PLL1_SS_CTRL2_M0 0x00D9U
109#define CMN_PLL1_SS_CTRL3_M0 0x00DAU
110#define CMN_PLL1_SS_CTRL4_M0 0x00DBU
111#define CMN_PLL1_LOCK_REFCNT_START 0x00DCU
112#define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU
113#define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU
114#define CMN_TXPUCAL_TUNE 0x0103U
115#define CMN_TXPUCAL_INIT_TMR 0x0104U
116#define CMN_TXPUCAL_ITER_TMR 0x0105U
117#define CMN_CMN_TXPDCAL_OVRD 0x0109U
118#define CMN_TXPDCAL_TUNE 0x010BU
119#define CMN_TXPDCAL_INIT_TMR 0x010CU
120#define CMN_TXPDCAL_ITER_TMR 0x010DU
121#define CMN_RXCAL_INIT_TMR 0x0114U
122#define CMN_RXCAL_ITER_TMR 0x0115U
123#define CMN_SD_CAL_INIT_TMR 0x0124U
124#define CMN_SD_CAL_ITER_TMR 0x0125U
125#define CMN_SD_CAL_REFTIM_START 0x0126U
126#define CMN_SD_CAL_PLLCNT_START 0x0128U
127#define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U
128#define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U
129#define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U
130#define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U
131#define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U
132#define CMN_PDIAG_PLL0_CTRL_M1 0x01B0U
133#define CMN_PDIAG_PLL0_CLK_SEL_M1 0x01B1U
134#define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U
135#define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U
136#define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01B6U
137#define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U
138#define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U
139#define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U
140#define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U
141#define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U
142#define CMN_DIAG_BIAS_OVRD1 0x01E1U
143
144/* PMA TX Lane registers */
145#define TX_TXCC_CTRL 0x0040U
146#define TX_TXCC_CPOST_MULT_00 0x004CU
147#define TX_TXCC_CPOST_MULT_01 0x004DU
148#define TX_TXCC_MGNFS_MULT_000 0x0050U
149#define TX_TXCC_MGNFS_MULT_100 0x0054U
150#define DRV_DIAG_TX_DRV 0x00C6U
151#define XCVR_DIAG_PLLDRC_CTRL 0x00E5U
152#define XCVR_DIAG_HSCLK_SEL 0x00E6U
153#define XCVR_DIAG_HSCLK_DIV 0x00E7U
154#define XCVR_DIAG_RXCLK_CTRL 0x00E9U
155#define XCVR_DIAG_BIDI_CTRL 0x00EAU
156#define XCVR_DIAG_PSC_OVRD 0x00EBU
157#define TX_PSC_A0 0x0100U
158#define TX_PSC_A1 0x0101U
159#define TX_PSC_A2 0x0102U
160#define TX_PSC_A3 0x0103U
161#define TX_RCVDET_ST_TMR 0x0123U
162#define TX_DIAG_ACYA 0x01E7U
163#define TX_DIAG_ACYA_HBDC_MASK 0x0001U
164
165/* PMA RX Lane registers */
166#define RX_PSC_A0 0x0000U
167#define RX_PSC_A1 0x0001U
168#define RX_PSC_A2 0x0002U
169#define RX_PSC_A3 0x0003U
170#define RX_PSC_CAL 0x0006U
171#define RX_CDRLF_CNFG 0x0080U
172#define RX_CDRLF_CNFG3 0x0082U
173#define RX_SIGDET_HL_FILT_TMR 0x0090U
174#define RX_REE_GCSM1_CTRL 0x0108U
175#define RX_REE_GCSM1_EQENM_PH1 0x0109U
176#define RX_REE_GCSM1_EQENM_PH2 0x010AU
177#define RX_REE_GCSM2_CTRL 0x0110U
178#define RX_REE_PERGCSM_CTRL 0x0118U
179#define RX_REE_ATTEN_THR 0x0149U
180#define RX_REE_TAP1_CLIP 0x0171U
181#define RX_REE_TAP2TON_CLIP 0x0172U
182#define RX_REE_SMGM_CTRL1 0x0177U
183#define RX_REE_SMGM_CTRL2 0x0178U
184#define RX_DIAG_DFE_CTRL 0x01E0U
185#define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U
186#define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U
187#define RX_DIAG_NQST_CTRL 0x01E5U
188#define RX_DIAG_SIGDET_TUNE 0x01E8U
189#define RX_DIAG_PI_RATE 0x01F4U
190#define RX_DIAG_PI_CAP 0x01F5U
191#define RX_DIAG_ACYA 0x01FFU
192
193/* PHY PCS common registers */
194#define PHY_PLL_CFG 0x000EU
195#define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U
196#define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U
197#define PHY_PIPE_USB3_GEN2_POST_CFG1 0x0023U
198
199/* PHY PMA common registers */
200#define PHY_PMA_CMN_CTRL1 0x0000U
201#define PHY_PMA_CMN_CTRL2 0x0001U
202#define PHY_PMA_PLL_RAW_CTRL 0x0003U
203
204static const struct reg_field phy_pll_cfg = REG_FIELD(PHY_PLL_CFG, 0, 1);
205static const struct reg_field phy_pma_cmn_ctrl_1 =
206 REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0);
207static const struct reg_field phy_pma_cmn_ctrl_2 =
208 REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7);
209static const struct reg_field phy_pma_pll_raw_ctrl =
210 REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1);
211
212#define reset_control_assert reset_assert
213#define reset_control_deassert reset_deassert
214#define reset_control reset_ctl
215#define reset_control_put reset_free
216
217enum cdns_torrent_phy_type {
218 TYPE_NONE,
219 TYPE_DP,
220 TYPE_PCIE,
221 TYPE_SGMII,
222 TYPE_QSGMII,
223 TYPE_USB,
224};
225
226enum cdns_torrent_ssc_mode {
227 NO_SSC,
228 EXTERNAL_SSC,
229 INTERNAL_SSC
230};
231
232struct cdns_torrent_inst {
233 struct phy *phy;
234 u32 mlane;
235 enum cdns_torrent_phy_type phy_type;
236 u32 num_lanes;
237 struct reset_ctl_bulk *lnk_rst;
238 enum cdns_torrent_ssc_mode ssc_mode;
239};
240
241struct cdns_torrent_phy {
242 void __iomem *sd_base; /* SD0801 register base */
243 size_t size;
244 struct reset_control *phy_rst;
245 struct udevice *dev;
246 struct cdns_torrent_inst phys[MAX_NUM_LANES];
247 int nsubnodes;
248 const struct cdns_torrent_data *init_data;
249 struct regmap *regmap;
250 struct regmap *regmap_common_cdb;
251 struct regmap *regmap_phy_pcs_common_cdb;
252 struct regmap *regmap_phy_pma_common_cdb;
253 struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];
254 struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
255 struct regmap_field *phy_pll_cfg;
256 struct regmap_field *phy_pma_cmn_ctrl_1;
257 struct regmap_field *phy_pma_cmn_ctrl_2;
258 struct regmap_field *phy_pma_pll_raw_ctrl;
259};
260
261struct cdns_reg_pairs {
262 u32 val;
263 u32 off;
264};
265
266struct cdns_torrent_vals {
267 struct cdns_reg_pairs *reg_pairs;
268 u32 num_regs;
269};
270
271struct cdns_torrent_data {
272 u8 block_offset_shift;
273 u8 reg_offset_shift;
274 struct cdns_torrent_vals *link_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
275 [NUM_SSC_MODE];
276 struct cdns_torrent_vals *xcvr_diag_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
277 [NUM_SSC_MODE];
278 struct cdns_torrent_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
279 [NUM_SSC_MODE];
280 struct cdns_torrent_vals *cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
281 [NUM_SSC_MODE];
282 struct cdns_torrent_vals *tx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
283 [NUM_SSC_MODE];
284 struct cdns_torrent_vals *rx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
285 [NUM_SSC_MODE];
286};
287
288static inline struct cdns_torrent_inst *phy_get_drvdata(struct phy *phy)
289{
290 struct cdns_torrent_phy *sp = dev_get_priv(phy->dev);
291 int index;
292
293 if (phy->id >= MAX_NUM_LANES)
294 return NULL;
295
296 for (index = 0; index < sp->nsubnodes; index++) {
297 if (phy->id == sp->phys[index].mlane)
298 return &sp->phys[index];
299 }
300
301 return NULL;
302}
303
304static struct regmap *cdns_regmap_init(struct udevice *dev, void __iomem *base,
305 u32 block_offset,
306 u8 reg_offset_shift)
307{
308 struct cdns_torrent_phy *sp = dev_get_priv(dev);
309 struct regmap_config config;
310
311 config.r_start = (ulong)(base + block_offset);
312 config.r_size = sp->size - block_offset;
313 config.reg_offset_shift = reg_offset_shift;
314 config.width = REGMAP_SIZE_16;
315
316 return devm_regmap_init(dev, NULL, NULL, &config);
317}
318
319static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy)
320{
321 struct udevice *dev = cdns_phy->dev;
322 struct regmap_field *field;
323 struct regmap *regmap;
324
325 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
326 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg);
327 if (IS_ERR(field)) {
328 dev_err(dev, "PHY_PLL_CFG reg field init failed\n");
329 return PTR_ERR(field);
330 }
331 cdns_phy->phy_pll_cfg = field;
332
333 regmap = cdns_phy->regmap_phy_pma_common_cdb;
334 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1);
335 if (IS_ERR(field)) {
336 dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n");
337 return PTR_ERR(field);
338 }
339 cdns_phy->phy_pma_cmn_ctrl_1 = field;
340
341 regmap = cdns_phy->regmap_phy_pma_common_cdb;
342 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2);
343 if (IS_ERR(field)) {
344 dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n");
345 return PTR_ERR(field);
346 }
347 cdns_phy->phy_pma_cmn_ctrl_2 = field;
348
349 regmap = cdns_phy->regmap_phy_pma_common_cdb;
350 field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl);
351 if (IS_ERR(field)) {
352 dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n");
353 return PTR_ERR(field);
354 }
355 cdns_phy->phy_pma_pll_raw_ctrl = field;
356
357 return 0;
358}
359
360static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy)
361{
362 void __iomem *sd_base = cdns_phy->sd_base;
363 u8 block_offset_shift, reg_offset_shift;
364 struct udevice *dev = cdns_phy->dev;
365 struct regmap *regmap;
366 u32 block_offset;
367 int i;
368
369 block_offset_shift = cdns_phy->init_data->block_offset_shift;
370 reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
371
372 for (i = 0; i < MAX_NUM_LANES; i++) {
373 block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift,
374 reg_offset_shift);
375
376 regmap = cdns_regmap_init(dev, sd_base, block_offset,
377 reg_offset_shift);
378 if (IS_ERR(regmap)) {
379 dev_err(dev, "Failed to init tx lane CDB regmap\n");
380 return PTR_ERR(regmap);
381 }
382 cdns_phy->regmap_tx_lane_cdb[i] = regmap;
383 block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift,
384 reg_offset_shift);
385 regmap = cdns_regmap_init(dev, sd_base, block_offset,
386 reg_offset_shift);
387 if (IS_ERR(regmap)) {
388 dev_err(dev, "Failed to init rx lane CDB regmap");
389 return PTR_ERR(regmap);
390 }
391 cdns_phy->regmap_rx_lane_cdb[i] = regmap;
392 }
393
394 block_offset = TORRENT_COMMON_CDB_OFFSET;
395 regmap = cdns_regmap_init(dev, sd_base, block_offset,
396 reg_offset_shift);
397 if (IS_ERR(regmap)) {
398 dev_err(dev, "Failed to init common CDB regmap\n");
399 return PTR_ERR(regmap);
400 }
401 cdns_phy->regmap_common_cdb = regmap;
402
403 block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift);
404 regmap = cdns_regmap_init(dev, sd_base, block_offset,
405 reg_offset_shift);
406 if (IS_ERR(regmap)) {
407 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
408 return PTR_ERR(regmap);
409 }
410 cdns_phy->regmap_phy_pcs_common_cdb = regmap;
411
412 block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift);
413 regmap = cdns_regmap_init(dev, sd_base, block_offset,
414 reg_offset_shift);
415 if (IS_ERR(regmap)) {
416 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
417 return PTR_ERR(regmap);
418 }
419 cdns_phy->regmap_phy_pma_common_cdb = regmap;
420
421 return 0;
422}
423
424static int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
425{
426 const struct cdns_torrent_data *init_data = cdns_phy->init_data;
427 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
428 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
429 enum cdns_torrent_phy_type phy_t1, phy_t2, tmp_phy_type;
430 struct cdns_torrent_vals *pcs_cmn_vals;
431 int i, j, node, mlane, num_lanes, ret;
432 struct cdns_reg_pairs *reg_pairs;
433 enum cdns_torrent_ssc_mode ssc;
434 struct regmap *regmap;
435 u32 num_regs;
436
437 /* Maximum 2 links (subnodes) are supported */
438 if (cdns_phy->nsubnodes != 2)
439 return -EINVAL;
440
441 phy_t1 = cdns_phy->phys[0].phy_type;
442 phy_t2 = cdns_phy->phys[1].phy_type;
443
444 /*
445 * First configure the PHY for first link with phy_t1. Geth the array
446 * values are [phy_t1][phy_t2][ssc].
447 */
448 for (node = 0; node < cdns_phy->nsubnodes; node++) {
449 if (node == 1) {
450 /*
451 * If fist link with phy_t1 is configured, then
452 * configure the PHY for second link with phy_t2.
453 * Get the array values as [phy_t2][phy_t1][ssc]
454 */
455 tmp_phy_type = phy_t1;
456 phy_t1 = phy_t2;
457 phy_t2 = tmp_phy_type;
458 }
459
460 mlane = cdns_phy->phys[node].mlane;
461 ssc = cdns_phy->phys[node].ssc_mode;
462 num_lanes = cdns_phy->phys[node].num_lanes;
463
464 /**
465 * PHY configuration specific registers:
466 * link_cmn_vals depend on combination of PHY types being
467 * configured and are common for both PHY types, so array
468 * values should be same for [phy_t1][phy_t2][ssc] and
469 * [phy_t2][phy_t1][ssc].
470 * xcvr_diag_vals also depend on combination of PHY types
471 * being configured, but these can be different for particular
472 * PHY type and are per lane.
473 */
474 link_cmn_vals = init_data->link_cmn_vals[phy_t1][phy_t2][ssc];
475 if (link_cmn_vals) {
476 reg_pairs = link_cmn_vals->reg_pairs;
477 num_regs = link_cmn_vals->num_regs;
478 regmap = cdns_phy->regmap_common_cdb;
479
480 /**
481 * First array value in link_cmn_vals must be of
482 * PHY_PLL_CFG register
483 */
484 regmap_field_write(cdns_phy->phy_pll_cfg,
485 reg_pairs[0].val);
486
487 for (i = 1; i < num_regs; i++)
488 regmap_write(regmap, reg_pairs[i].off,
489 reg_pairs[i].val);
490 }
491
492 xcvr_diag_vals = init_data->xcvr_diag_vals[phy_t1][phy_t2][ssc];
493 if (xcvr_diag_vals) {
494 reg_pairs = xcvr_diag_vals->reg_pairs;
495 num_regs = xcvr_diag_vals->num_regs;
496 for (i = 0; i < num_lanes; i++) {
497 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
498 for (j = 0; j < num_regs; j++)
499 regmap_write(regmap, reg_pairs[j].off,
500 reg_pairs[j].val);
501 }
502 }
503
504 /* PHY PCS common registers configurations */
505 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc];
506 if (pcs_cmn_vals) {
507 reg_pairs = pcs_cmn_vals->reg_pairs;
508 num_regs = pcs_cmn_vals->num_regs;
509 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
510 for (i = 0; i < num_regs; i++)
511 regmap_write(regmap, reg_pairs[i].off,
512 reg_pairs[i].val);
513 }
514
515 /* PMA common registers configurations */
516 cmn_vals = init_data->cmn_vals[phy_t1][phy_t2][ssc];
517 if (cmn_vals) {
518 reg_pairs = cmn_vals->reg_pairs;
519 num_regs = cmn_vals->num_regs;
520 regmap = cdns_phy->regmap_common_cdb;
521 for (i = 0; i < num_regs; i++)
522 regmap_write(regmap, reg_pairs[i].off,
523 reg_pairs[i].val);
524 }
525
526 /* PMA TX lane registers configurations */
527 tx_ln_vals = init_data->tx_ln_vals[phy_t1][phy_t2][ssc];
528 if (tx_ln_vals) {
529 reg_pairs = tx_ln_vals->reg_pairs;
530 num_regs = tx_ln_vals->num_regs;
531 for (i = 0; i < num_lanes; i++) {
532 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
533 for (j = 0; j < num_regs; j++)
534 regmap_write(regmap, reg_pairs[j].off,
535 reg_pairs[j].val);
536 }
537 }
538
539 /* PMA RX lane registers configurations */
540 rx_ln_vals = init_data->rx_ln_vals[phy_t1][phy_t2][ssc];
541 if (rx_ln_vals) {
542 reg_pairs = rx_ln_vals->reg_pairs;
543 num_regs = rx_ln_vals->num_regs;
544 for (i = 0; i < num_lanes; i++) {
545 regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane];
546 for (j = 0; j < num_regs; j++)
547 regmap_write(regmap, reg_pairs[j].off,
548 reg_pairs[j].val);
549 }
550 }
551
552 reset_deassert_bulk(cdns_phy->phys[node].lnk_rst);
553 }
554
555 /* Take the PHY out of reset */
556 ret = reset_control_deassert(cdns_phy->phy_rst);
557 if (ret)
558 return ret;
559
560 return 0;
561}
562
563static int cdns_torrent_phy_probe(struct udevice *dev)
564{
565 struct cdns_torrent_phy *cdns_phy = dev_get_priv(dev);
566 int ret, subnodes = 0, node = 0, i;
567 struct cdns_torrent_data *data;
568 u32 total_num_lanes = 0;
569 struct clk *clk;
570 ofnode child;
571 u32 phy_type;
572
573 cdns_phy->dev = dev;
574
575 /* Get init data for this phy */
576 data = (struct cdns_torrent_data *)dev_get_driver_data(dev);
577 cdns_phy->init_data = data;
578
579 cdns_phy->phy_rst = devm_reset_control_get_by_index(dev, 0);
580 if (IS_ERR(cdns_phy->phy_rst)) {
581 dev_err(dev, "failed to get reset\n");
582 return PTR_ERR(cdns_phy->phy_rst);
583 }
584
585 clk = devm_clk_get(dev, "refclk");
586 if (IS_ERR(clk)) {
587 dev_err(dev, "phy ref clock not found\n");
588 return PTR_ERR(clk);
589 }
590
591 ret = clk_prepare_enable(clk);
592 if (ret) {
593 dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
594 return ret;
595 }
596
597 cdns_phy->sd_base = devfdt_remap_addr_index(dev, 0);
598 if (IS_ERR(cdns_phy->sd_base))
599 return PTR_ERR(cdns_phy->sd_base);
600 devfdt_get_addr_size_index(dev, 0, (fdt_size_t *)&cdns_phy->size);
601
602 dev_for_each_subnode(child, dev)
603 subnodes++;
604 if (subnodes == 0) {
605 dev_err(dev, "No available link subnodes found\n");
606 return -EINVAL;
607 }
608 ret = cdns_torrent_regmap_init(cdns_phy);
609 if (ret)
610 return ret;
611
612 ret = cdns_torrent_regfield_init(cdns_phy);
613 if (ret)
614 return ret;
615
616 /* Going through all the available subnodes or children*/
617 ofnode_for_each_subnode(child, dev_ofnode(dev)) {
Aswath Govindraju35a51e02021-10-20 20:58:57 +0530[diff] [blame]618 /* PHY subnode name must be a 'phy' */
619 if (!ofnode_name_eq(child, "phy"))
Aswath Govindrajufb2bdb62021-07-21 21:28:37 +0530[diff] [blame]620 continue;
621 cdns_phy->phys[node].lnk_rst =
622 devm_reset_bulk_get_by_node(dev, child);
623 if (IS_ERR(cdns_phy->phys[node].lnk_rst)) {
624 dev_err(dev, "%s: failed to get reset\n",
625 ofnode_get_name(child));
626 ret = PTR_ERR(cdns_phy->phys[node].lnk_rst);
627 goto put_lnk_rst;
628 }
629
630 if (ofnode_read_u32(child, "reg",
631 &cdns_phy->phys[node].mlane)) {
632 dev_err(dev, "%s: No \"reg \" - property.\n",
633 ofnode_get_name(child));
634 ret = -EINVAL;
635 goto put_child;
636 }
637
638 if (ofnode_read_u32(child, "cdns,phy-type", &phy_type)) {
639 dev_err(dev, "%s: No \"cdns,phy-type \" - property.\n",
640 ofnode_get_name(child));
641 ret = -EINVAL;
642 goto put_child;
643 }
644
645 switch (phy_type) {
646 case PHY_TYPE_PCIE:
647 cdns_phy->phys[node].phy_type = TYPE_PCIE;
648 break;
649 case PHY_TYPE_DP:
650 cdns_phy->phys[node].phy_type = TYPE_DP;
651 break;
652 case PHY_TYPE_SGMII:
653 cdns_phy->phys[node].phy_type = TYPE_SGMII;
654 break;
655 case PHY_TYPE_QSGMII:
656 cdns_phy->phys[node].phy_type = TYPE_QSGMII;
657 break;
658 case PHY_TYPE_USB3:
659 cdns_phy->phys[node].phy_type = TYPE_USB;
660 break;
661 default:
662 dev_err(dev, "Unsupported protocol\n");
663 ret = -EINVAL;
664 goto put_child;
665 }
666
667 if (ofnode_read_u32(child, "cdns,num-lanes",
668 &cdns_phy->phys[node].num_lanes)) {
669 dev_err(dev, "%s: No \"cdns,num-lanes \" - property.\n",
670 ofnode_get_name(child));
671 ret = -EINVAL;
672 goto put_child;
673 }
674
675 total_num_lanes += cdns_phy->phys[node].num_lanes;
676
677 /* Get SSC mode */
678 ofnode_read_u32(child, "cdns,ssc-mode",
679 &cdns_phy->phys[node].ssc_mode);
680 node++;
681 }
682
683 cdns_phy->nsubnodes = node;
684
685 if (total_num_lanes > MAX_NUM_LANES) {
686 dev_err(dev, "Invalid lane configuration\n");
687 goto put_lnk_rst;
688 }
689
690 if (cdns_phy->nsubnodes > 1) {
691 ret = cdns_torrent_phy_configure_multilink(cdns_phy);
692 if (ret)
693 goto put_lnk_rst;
694 }
695
696 reset_control_deassert(cdns_phy->phy_rst);
697 return 0;
698
699put_child:
700 node++;
701put_lnk_rst:
702 for (i = 0; i < node; i++)
703 reset_release_bulk(cdns_phy->phys[i].lnk_rst);
704 return ret;
705}
706
707static int cdns_torrent_phy_on(struct phy *gphy)
708{
709 struct cdns_torrent_inst *inst = phy_get_drvdata(gphy);
710 struct cdns_torrent_phy *cdns_phy = dev_get_priv(gphy->dev);
711 u32 read_val;
712 int ret;
713
714 if (cdns_phy->nsubnodes == 1) {
715 /* Take the PHY lane group out of reset */
716 reset_deassert_bulk(inst->lnk_rst);
717
718 /* Take the PHY out of reset */
719 ret = reset_control_deassert(cdns_phy->phy_rst);
720 if (ret)
721 return ret;
722 }
723
724 /*
725 * Wait for cmn_ready assertion
726 * PHY_PMA_CMN_CTRL1[0] == 1
727 */
728 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,
729 read_val, read_val, 1000,
730 PLL_LOCK_TIMEOUT);
731 if (ret) {
732 dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");
733 return ret;
734 }
735 mdelay(10);
736
737 return 0;
738}
739
740static int cdns_torrent_phy_init(struct phy *phy)
741{
742 struct cdns_torrent_phy *cdns_phy = dev_get_priv(phy->dev);
743 const struct cdns_torrent_data *init_data = cdns_phy->init_data;
744 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
745 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
746 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
747 enum cdns_torrent_phy_type phy_type = inst->phy_type;
748 enum cdns_torrent_ssc_mode ssc = inst->ssc_mode;
749 struct cdns_torrent_vals *pcs_cmn_vals;
750 struct cdns_reg_pairs *reg_pairs;
751 struct regmap *regmap;
752 u32 num_regs;
753 int i, j;
754
755 if (cdns_phy->nsubnodes > 1)
756 return 0;
757
758 /**
759 * Spread spectrum generation is not required or supported
760 * for SGMII/QSGMII
761 */
762 if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII)
763 ssc = NO_SSC;
764
765 /* PHY configuration specific registers for single link */
766 link_cmn_vals = init_data->link_cmn_vals[phy_type][TYPE_NONE][ssc];
767 if (link_cmn_vals) {
768 reg_pairs = link_cmn_vals->reg_pairs;
769 num_regs = link_cmn_vals->num_regs;
770 regmap = cdns_phy->regmap_common_cdb;
771
772 /**
773 * First array value in link_cmn_vals must be of
774 * PHY_PLL_CFG register
775 */
776 regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val);
777
778 for (i = 1; i < num_regs; i++)
779 regmap_write(regmap, reg_pairs[i].off,
780 reg_pairs[i].val);
781 }
782
783 xcvr_diag_vals = init_data->xcvr_diag_vals[phy_type][TYPE_NONE][ssc];
784 if (xcvr_diag_vals) {
785 reg_pairs = xcvr_diag_vals->reg_pairs;
786 num_regs = xcvr_diag_vals->num_regs;
787 for (i = 0; i < inst->num_lanes; i++) {
788 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
789 for (j = 0; j < num_regs; j++)
790 regmap_write(regmap, reg_pairs[j].off,
791 reg_pairs[j].val);
792 }
793 }
794
795 /* PHY PCS common registers configurations */
796 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
797 if (pcs_cmn_vals) {
798 reg_pairs = pcs_cmn_vals->reg_pairs;
799 num_regs = pcs_cmn_vals->num_regs;
800 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
801 for (i = 0; i < num_regs; i++)
802 regmap_write(regmap, reg_pairs[i].off,
803 reg_pairs[i].val);
804 }
805
806 /* PMA common registers configurations */
807 cmn_vals = init_data->cmn_vals[phy_type][TYPE_NONE][ssc];
808 if (cmn_vals) {
809 reg_pairs = cmn_vals->reg_pairs;
810 num_regs = cmn_vals->num_regs;
811 regmap = cdns_phy->regmap_common_cdb;
812 for (i = 0; i < num_regs; i++)
813 regmap_write(regmap, reg_pairs[i].off,
814 reg_pairs[i].val);
815 }
816
817 /* PMA TX lane registers configurations */
818 tx_ln_vals = init_data->tx_ln_vals[phy_type][TYPE_NONE][ssc];
819 if (tx_ln_vals) {
820 reg_pairs = tx_ln_vals->reg_pairs;
821 num_regs = tx_ln_vals->num_regs;
822 for (i = 0; i < inst->num_lanes; i++) {
823 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
824 for (j = 0; j < num_regs; j++)
825 regmap_write(regmap, reg_pairs[j].off,
826 reg_pairs[j].val);
827 }
828 }
829
830 /* PMA RX lane registers configurations */
831 rx_ln_vals = init_data->rx_ln_vals[phy_type][TYPE_NONE][ssc];
832 if (rx_ln_vals) {
833 reg_pairs = rx_ln_vals->reg_pairs;
834 num_regs = rx_ln_vals->num_regs;
835 for (i = 0; i < inst->num_lanes; i++) {
836 regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane];
837 for (j = 0; j < num_regs; j++)
838 regmap_write(regmap, reg_pairs[j].off,
839 reg_pairs[j].val);
840 }
841 }
842
843 return 0;
844}
845
846static int cdns_torrent_phy_off(struct phy *gphy)
847{
848 struct cdns_torrent_inst *inst = phy_get_drvdata(gphy);
849 struct cdns_torrent_phy *cdns_phy = dev_get_priv(gphy->dev);
850 int ret;
851
852 if (cdns_phy->nsubnodes != 1)
853 return 0;
854
855 ret = reset_control_assert(cdns_phy->phy_rst);
856 if (ret)
857 return ret;
858
859 return reset_assert_bulk(inst->lnk_rst);
860}
861
862static int cdns_torrent_phy_remove(struct udevice *dev)
863{
864 struct cdns_torrent_phy *cdns_phy = dev_get_priv(dev);
865 int i;
866
867 reset_control_assert(cdns_phy->phy_rst);
868 for (i = 0; i < cdns_phy->nsubnodes; i++)
869 reset_release_bulk(cdns_phy->phys[i].lnk_rst);
870
871 return 0;
872}
873
874/* USB and SGMII/QSGMII link configuration */
875static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = {
876 {0x0002, PHY_PLL_CFG},
877 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0},
878 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
879};
880
881static struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = {
882 {0x0000, XCVR_DIAG_HSCLK_SEL},
883 {0x0001, XCVR_DIAG_HSCLK_DIV},
884 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
885};
886
887static struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = {
888 {0x0011, XCVR_DIAG_HSCLK_SEL},
889 {0x0003, XCVR_DIAG_HSCLK_DIV},
890 {0x009B, XCVR_DIAG_PLLDRC_CTRL}
891};
892
893static struct cdns_torrent_vals usb_sgmii_link_cmn_vals = {
894 .reg_pairs = usb_sgmii_link_cmn_regs,
895 .num_regs = ARRAY_SIZE(usb_sgmii_link_cmn_regs),
896};
897
898static struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = {
899 .reg_pairs = usb_sgmii_xcvr_diag_ln_regs,
900 .num_regs = ARRAY_SIZE(usb_sgmii_xcvr_diag_ln_regs),
901};
902
903static struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = {
904 .reg_pairs = sgmii_usb_xcvr_diag_ln_regs,
905 .num_regs = ARRAY_SIZE(sgmii_usb_xcvr_diag_ln_regs),
906};
907
908/* PCIe and USB Unique SSC link configuration */
909static struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = {
910 {0x0003, PHY_PLL_CFG},
911 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
912 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
913 {0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0}
914};
915
916static struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = {
917 {0x0000, XCVR_DIAG_HSCLK_SEL},
918 {0x0001, XCVR_DIAG_HSCLK_DIV},
919 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
920};
921
922static struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = {
923 {0x0011, XCVR_DIAG_HSCLK_SEL},
924 {0x0001, XCVR_DIAG_HSCLK_DIV},
925 {0x00C9, XCVR_DIAG_PLLDRC_CTRL}
926};
927
928static struct cdns_torrent_vals pcie_usb_link_cmn_vals = {
929 .reg_pairs = pcie_usb_link_cmn_regs,
930 .num_regs = ARRAY_SIZE(pcie_usb_link_cmn_regs),
931};
932
933static struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = {
934 .reg_pairs = pcie_usb_xcvr_diag_ln_regs,
935 .num_regs = ARRAY_SIZE(pcie_usb_xcvr_diag_ln_regs),
936};
937
938static struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = {
939 .reg_pairs = usb_pcie_xcvr_diag_ln_regs,
940 .num_regs = ARRAY_SIZE(usb_pcie_xcvr_diag_ln_regs),
941};
942
943/* USB 100 MHz Ref clk, internal SSC */
944static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = {
945 {0x0004, CMN_PLL0_DSM_DIAG_M0},
946 {0x0004, CMN_PLL0_DSM_DIAG_M1},
947 {0x0004, CMN_PLL1_DSM_DIAG_M0},
948 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
949 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
950 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
951 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
952 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
953 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
954 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
955 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
956 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
957 {0x0064, CMN_PLL0_INTDIV_M0},
958 {0x0050, CMN_PLL0_INTDIV_M1},
959 {0x0064, CMN_PLL1_INTDIV_M0},
960 {0x0002, CMN_PLL0_FRACDIVH_M0},
961 {0x0002, CMN_PLL0_FRACDIVH_M1},
962 {0x0002, CMN_PLL1_FRACDIVH_M0},
963 {0x0044, CMN_PLL0_HIGH_THR_M0},
964 {0x0036, CMN_PLL0_HIGH_THR_M1},
965 {0x0044, CMN_PLL1_HIGH_THR_M0},
966 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
967 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
968 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
969 {0x0001, CMN_PLL0_SS_CTRL1_M0},
970 {0x0001, CMN_PLL0_SS_CTRL1_M1},
971 {0x0001, CMN_PLL1_SS_CTRL1_M0},
972 {0x011B, CMN_PLL0_SS_CTRL2_M0},
973 {0x011B, CMN_PLL0_SS_CTRL2_M1},
974 {0x011B, CMN_PLL1_SS_CTRL2_M0},
975 {0x006E, CMN_PLL0_SS_CTRL3_M0},
976 {0x0058, CMN_PLL0_SS_CTRL3_M1},
977 {0x006E, CMN_PLL1_SS_CTRL3_M0},
978 {0x000E, CMN_PLL0_SS_CTRL4_M0},
979 {0x0012, CMN_PLL0_SS_CTRL4_M1},
980 {0x000E, CMN_PLL1_SS_CTRL4_M0},
981 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
982 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
983 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
984 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
985 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
986 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
987 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
988 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
989 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
990 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
991 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
992 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},
993 {0x007F, CMN_TXPUCAL_TUNE},
994 {0x007F, CMN_TXPDCAL_TUNE}
995};
996
997static struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = {
998 .reg_pairs = usb_100_int_ssc_cmn_regs,
999 .num_regs = ARRAY_SIZE(usb_100_int_ssc_cmn_regs),
1000};
1001
1002/* Single USB link configuration */
1003static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = {
1004 {0x0000, PHY_PLL_CFG},
1005 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}
1006};
1007
1008static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = {
1009 {0x0000, XCVR_DIAG_HSCLK_SEL},
1010 {0x0001, XCVR_DIAG_HSCLK_DIV},
1011 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
1012};
1013
1014static struct cdns_torrent_vals sl_usb_link_cmn_vals = {
1015 .reg_pairs = sl_usb_link_cmn_regs,
1016 .num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs),
1017};
1018
1019static struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = {
1020 .reg_pairs = sl_usb_xcvr_diag_ln_regs,
1021 .num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs),
1022};
1023
1024/* USB PHY PCS common configuration */
1025static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = {
1026 {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0},
1027 {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0},
1028 {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1}
1029};
1030
1031static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = {
1032 .reg_pairs = usb_phy_pcs_cmn_regs,
1033 .num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs),
1034};
1035
1036/* USB 100 MHz Ref clk, no SSC */
1037static struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = {
1038 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
1039 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
1040 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
1041 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
1042 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
1043 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
1044 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
1045};
1046
1047static struct cdns_torrent_vals sl_usb_100_no_ssc_cmn_vals = {
1048 .reg_pairs = sl_usb_100_no_ssc_cmn_regs,
1049 .num_regs = ARRAY_SIZE(sl_usb_100_no_ssc_cmn_regs),
1050};
1051
1052static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = {
1053 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
1054 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},
1055 {0x007F, CMN_TXPUCAL_TUNE},
1056 {0x007F, CMN_TXPDCAL_TUNE}
1057};
1058
1059static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = {
1060 {0x02FF, TX_PSC_A0},
1061 {0x06AF, TX_PSC_A1},
1062 {0x06AE, TX_PSC_A2},
1063 {0x06AE, TX_PSC_A3},
1064 {0x2A82, TX_TXCC_CTRL},
1065 {0x0014, TX_TXCC_CPOST_MULT_01},
1066 {0x0003, XCVR_DIAG_PSC_OVRD}
1067};
1068
1069static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = {
1070 {0x0D1D, RX_PSC_A0},
1071 {0x0D1D, RX_PSC_A1},
1072 {0x0D00, RX_PSC_A2},
1073 {0x0500, RX_PSC_A3},
1074 {0x0013, RX_SIGDET_HL_FILT_TMR},
1075 {0x0000, RX_REE_GCSM1_CTRL},
1076 {0x0C02, RX_REE_ATTEN_THR},
1077 {0x0330, RX_REE_SMGM_CTRL1},
1078 {0x0300, RX_REE_SMGM_CTRL2},
1079 {0x0019, RX_REE_TAP1_CLIP},
1080 {0x0019, RX_REE_TAP2TON_CLIP},
1081 {0x1004, RX_DIAG_SIGDET_TUNE},
1082 {0x00F9, RX_DIAG_NQST_CTRL},
1083 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
1084 {0x0002, RX_DIAG_DFE_AMP_TUNE_3},
1085 {0x0000, RX_DIAG_PI_CAP},
1086 {0x0031, RX_DIAG_PI_RATE},
1087 {0x0001, RX_DIAG_ACYA},
1088 {0x018C, RX_CDRLF_CNFG},
1089 {0x0003, RX_CDRLF_CNFG3}
1090};
1091
1092static struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = {
1093 .reg_pairs = usb_100_no_ssc_cmn_regs,
1094 .num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs),
1095};
1096
1097static struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = {
1098 .reg_pairs = usb_100_no_ssc_tx_ln_regs,
1099 .num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs),
1100};
1101
1102static struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = {
1103 .reg_pairs = usb_100_no_ssc_rx_ln_regs,
1104 .num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs),
1105};
1106
1107/* Single link USB, 100 MHz Ref clk, internal SSC */
1108static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = {
1109 {0x0004, CMN_PLL0_DSM_DIAG_M0},
1110 {0x0004, CMN_PLL1_DSM_DIAG_M0},
1111 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
1112 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
1113 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
1114 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
1115 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
1116 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
1117 {0x0064, CMN_PLL0_INTDIV_M0},
1118 {0x0064, CMN_PLL1_INTDIV_M0},
1119 {0x0002, CMN_PLL0_FRACDIVH_M0},
1120 {0x0002, CMN_PLL1_FRACDIVH_M0},
1121 {0x0044, CMN_PLL0_HIGH_THR_M0},
1122 {0x0044, CMN_PLL1_HIGH_THR_M0},
1123 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
1124 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
1125 {0x0001, CMN_PLL0_SS_CTRL1_M0},
1126 {0x0001, CMN_PLL1_SS_CTRL1_M0},
1127 {0x011B, CMN_PLL0_SS_CTRL2_M0},
1128 {0x011B, CMN_PLL1_SS_CTRL2_M0},
1129 {0x006E, CMN_PLL0_SS_CTRL3_M0},
1130 {0x006E, CMN_PLL1_SS_CTRL3_M0},
1131 {0x000E, CMN_PLL0_SS_CTRL4_M0},
1132 {0x000E, CMN_PLL1_SS_CTRL4_M0},
1133 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
1134 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
1135 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
1136 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
1137 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
1138 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
1139 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
1140 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
1141 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
1142 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
1143 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
1144 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
1145 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
1146 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
1147};
1148
1149static struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = {
1150 .reg_pairs = sl_usb_100_int_ssc_cmn_regs,
1151 .num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs),
1152};
1153
1154/* PCIe and SGMII/QSGMII Unique SSC link configuration */
1155static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = {
1156 {0x0003, PHY_PLL_CFG},
1157 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
1158 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
1159 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
1160};
1161
1162static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = {
1163 {0x0000, XCVR_DIAG_HSCLK_SEL},
1164 {0x0001, XCVR_DIAG_HSCLK_DIV},
1165 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
1166};
1167
1168static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = {
1169 {0x0011, XCVR_DIAG_HSCLK_SEL},
1170 {0x0003, XCVR_DIAG_HSCLK_DIV},
1171 {0x009B, XCVR_DIAG_PLLDRC_CTRL}
1172};
1173
1174static struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = {
1175 .reg_pairs = pcie_sgmii_link_cmn_regs,
1176 .num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs),
1177};
1178
1179static struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = {
1180 .reg_pairs = pcie_sgmii_xcvr_diag_ln_regs,
1181 .num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs),
1182};
1183
1184static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = {
1185 .reg_pairs = sgmii_pcie_xcvr_diag_ln_regs,
1186 .num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs),
1187};
1188
1189/* SGMII 100 MHz Ref clk, no SSC */
1190static struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = {
1191 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
1192 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
1193 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
1194 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
1195 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
1196};
1197
1198static struct cdns_torrent_vals sl_sgmii_100_no_ssc_cmn_vals = {
1199 .reg_pairs = sl_sgmii_100_no_ssc_cmn_regs,
1200 .num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_cmn_regs),
1201};
1202
1203static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = {
1204 {0x007F, CMN_TXPUCAL_TUNE},
1205 {0x007F, CMN_TXPDCAL_TUNE}
1206};
1207
1208static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = {
1209 {0x00F3, TX_PSC_A0},
1210 {0x04A2, TX_PSC_A2},
1211 {0x04A2, TX_PSC_A3},
1212 {0x0000, TX_TXCC_CPOST_MULT_00},
1213 {0x00B3, DRV_DIAG_TX_DRV}
1214};
1215
1216static struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = {
1217 {0x00F3, TX_PSC_A0},
1218 {0x04A2, TX_PSC_A2},
1219 {0x04A2, TX_PSC_A3},
1220 {0x0000, TX_TXCC_CPOST_MULT_00},
1221 {0x00B3, DRV_DIAG_TX_DRV},
1222 {0x4000, XCVR_DIAG_RXCLK_CTRL},
1223};
1224
1225static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = {
1226 {0x091D, RX_PSC_A0},
1227 {0x0900, RX_PSC_A2},
1228 {0x0100, RX_PSC_A3},
1229 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
1230 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
1231 {0x0000, RX_DIAG_DFE_CTRL},
1232 {0x0019, RX_REE_TAP1_CLIP},
1233 {0x0019, RX_REE_TAP2TON_CLIP},
1234 {0x0098, RX_DIAG_NQST_CTRL},
1235 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
1236 {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
1237 {0x0000, RX_DIAG_PI_CAP},
1238 {0x0010, RX_DIAG_PI_RATE},
1239 {0x0001, RX_DIAG_ACYA},
1240 {0x018C, RX_CDRLF_CNFG},
1241};
1242
1243static struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = {
1244 .reg_pairs = sgmii_100_no_ssc_cmn_regs,
1245 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs),
1246};
1247
1248static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = {
1249 .reg_pairs = sgmii_100_no_ssc_tx_ln_regs,
1250 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs),
1251};
1252
1253static struct cdns_torrent_vals ti_sgmii_100_no_ssc_tx_ln_vals = {
1254 .reg_pairs = ti_sgmii_100_no_ssc_tx_ln_regs,
1255 .num_regs = ARRAY_SIZE(ti_sgmii_100_no_ssc_tx_ln_regs),
1256};
1257
1258static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = {
1259 .reg_pairs = sgmii_100_no_ssc_rx_ln_regs,
1260 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs),
1261};
1262
1263/* SGMII 100 MHz Ref clk, internal SSC */
1264static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = {
1265 {0x0004, CMN_PLL0_DSM_DIAG_M0},
1266 {0x0004, CMN_PLL0_DSM_DIAG_M1},
1267 {0x0004, CMN_PLL1_DSM_DIAG_M0},
1268 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
1269 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
1270 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
1271 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
1272 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
1273 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
1274 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
1275 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
1276 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
1277 {0x0064, CMN_PLL0_INTDIV_M0},
1278 {0x0050, CMN_PLL0_INTDIV_M1},
1279 {0x0064, CMN_PLL1_INTDIV_M0},
1280 {0x0002, CMN_PLL0_FRACDIVH_M0},
1281 {0x0002, CMN_PLL0_FRACDIVH_M1},
1282 {0x0002, CMN_PLL1_FRACDIVH_M0},
1283 {0x0044, CMN_PLL0_HIGH_THR_M0},
1284 {0x0036, CMN_PLL0_HIGH_THR_M1},
1285 {0x0044, CMN_PLL1_HIGH_THR_M0},
1286 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
1287 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
1288 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
1289 {0x0001, CMN_PLL0_SS_CTRL1_M0},
1290 {0x0001, CMN_PLL0_SS_CTRL1_M1},
1291 {0x0001, CMN_PLL1_SS_CTRL1_M0},
1292 {0x011B, CMN_PLL0_SS_CTRL2_M0},
1293 {0x011B, CMN_PLL0_SS_CTRL2_M1},
1294 {0x011B, CMN_PLL1_SS_CTRL2_M0},
1295 {0x006E, CMN_PLL0_SS_CTRL3_M0},
1296 {0x0058, CMN_PLL0_SS_CTRL3_M1},
1297 {0x006E, CMN_PLL1_SS_CTRL3_M0},
1298 {0x000E, CMN_PLL0_SS_CTRL4_M0},
1299 {0x0012, CMN_PLL0_SS_CTRL4_M1},
1300 {0x000E, CMN_PLL1_SS_CTRL4_M0},
1301 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
1302 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
1303 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
1304 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
1305 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
1306 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
1307 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
1308 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
1309 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
1310 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
1311 {0x007F, CMN_TXPUCAL_TUNE},
1312 {0x007F, CMN_TXPDCAL_TUNE}
1313};
1314
1315static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = {
1316 .reg_pairs = sgmii_100_int_ssc_cmn_regs,
1317 .num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs),
1318};
1319
1320/* QSGMII 100 MHz Ref clk, no SSC */
1321static struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = {
1322 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
1323 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
1324 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
1325 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
1326 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
1327};
1328
1329static struct cdns_torrent_vals sl_qsgmii_100_no_ssc_cmn_vals = {
1330 .reg_pairs = sl_qsgmii_100_no_ssc_cmn_regs,
1331 .num_regs = ARRAY_SIZE(sl_qsgmii_100_no_ssc_cmn_regs),
1332};
1333
1334static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = {
1335 {0x007F, CMN_TXPUCAL_TUNE},
1336 {0x007F, CMN_TXPDCAL_TUNE}
1337};
1338
1339static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = {
1340 {0x00F3, TX_PSC_A0},
1341 {0x04A2, TX_PSC_A2},
1342 {0x04A2, TX_PSC_A3},
1343 {0x0000, TX_TXCC_CPOST_MULT_00},
1344 {0x0011, TX_TXCC_MGNFS_MULT_100},
1345 {0x0003, DRV_DIAG_TX_DRV}
1346};
1347
1348static struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = {
1349 {0x00F3, TX_PSC_A0},
1350 {0x04A2, TX_PSC_A2},
1351 {0x04A2, TX_PSC_A3},
1352 {0x0000, TX_TXCC_CPOST_MULT_00},
1353 {0x0011, TX_TXCC_MGNFS_MULT_100},
1354 {0x0003, DRV_DIAG_TX_DRV},
1355 {0x4000, XCVR_DIAG_RXCLK_CTRL},
1356};
1357
1358static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = {
1359 {0x091D, RX_PSC_A0},
1360 {0x0900, RX_PSC_A2},
1361 {0x0100, RX_PSC_A3},
1362 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
1363 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
1364 {0x0000, RX_DIAG_DFE_CTRL},
1365 {0x0019, RX_REE_TAP1_CLIP},
1366 {0x0019, RX_REE_TAP2TON_CLIP},
1367 {0x0098, RX_DIAG_NQST_CTRL},
1368 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
1369 {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
1370 {0x0000, RX_DIAG_PI_CAP},
1371 {0x0010, RX_DIAG_PI_RATE},
1372 {0x0001, RX_DIAG_ACYA},
1373 {0x018C, RX_CDRLF_CNFG},
1374};
1375
1376static struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = {
1377 .reg_pairs = qsgmii_100_no_ssc_cmn_regs,
1378 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs),
1379};
1380
1381static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = {
1382 .reg_pairs = qsgmii_100_no_ssc_tx_ln_regs,
1383 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs),
1384};
1385
1386static struct cdns_torrent_vals ti_qsgmii_100_no_ssc_tx_ln_vals = {
1387 .reg_pairs = ti_qsgmii_100_no_ssc_tx_ln_regs,
1388 .num_regs = ARRAY_SIZE(ti_qsgmii_100_no_ssc_tx_ln_regs),
1389};
1390
1391static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = {
1392 .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs,
1393 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs),
1394};
1395
1396/* QSGMII 100 MHz Ref clk, internal SSC */
1397static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = {
1398 {0x0004, CMN_PLL0_DSM_DIAG_M0},
1399 {0x0004, CMN_PLL0_DSM_DIAG_M1},
1400 {0x0004, CMN_PLL1_DSM_DIAG_M0},
1401 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
1402 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
1403 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
1404 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
1405 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
1406 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
1407 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
1408 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
1409 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
1410 {0x0064, CMN_PLL0_INTDIV_M0},
1411 {0x0050, CMN_PLL0_INTDIV_M1},
1412 {0x0064, CMN_PLL1_INTDIV_M0},
1413 {0x0002, CMN_PLL0_FRACDIVH_M0},
1414 {0x0002, CMN_PLL0_FRACDIVH_M1},
1415 {0x0002, CMN_PLL1_FRACDIVH_M0},
1416 {0x0044, CMN_PLL0_HIGH_THR_M0},
1417 {0x0036, CMN_PLL0_HIGH_THR_M1},
1418 {0x0044, CMN_PLL1_HIGH_THR_M0},
1419 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
1420 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
1421 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
1422 {0x0001, CMN_PLL0_SS_CTRL1_M0},
1423 {0x0001, CMN_PLL0_SS_CTRL1_M1},
1424 {0x0001, CMN_PLL1_SS_CTRL1_M0},
1425 {0x011B, CMN_PLL0_SS_CTRL2_M0},
1426 {0x011B, CMN_PLL0_SS_CTRL2_M1},
1427 {0x011B, CMN_PLL1_SS_CTRL2_M0},
1428 {0x006E, CMN_PLL0_SS_CTRL3_M0},
1429 {0x0058, CMN_PLL0_SS_CTRL3_M1},
1430 {0x006E, CMN_PLL1_SS_CTRL3_M0},
1431 {0x000E, CMN_PLL0_SS_CTRL4_M0},
1432 {0x0012, CMN_PLL0_SS_CTRL4_M1},
1433 {0x000E, CMN_PLL1_SS_CTRL4_M0},
1434 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
1435 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
1436 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
1437 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
1438 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
1439 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
1440 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
1441 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
1442 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
1443 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
1444 {0x007F, CMN_TXPUCAL_TUNE},
1445 {0x007F, CMN_TXPDCAL_TUNE}
1446};
1447
1448static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = {
1449 .reg_pairs = qsgmii_100_int_ssc_cmn_regs,
1450 .num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs),
1451};
1452
1453/* Single SGMII/QSGMII link configuration */
1454static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = {
1455 {0x0000, PHY_PLL_CFG},
1456 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
1457};
1458
1459static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = {
1460 {0x0000, XCVR_DIAG_HSCLK_SEL},
1461 {0x0003, XCVR_DIAG_HSCLK_DIV},
1462 {0x0013, XCVR_DIAG_PLLDRC_CTRL}
1463};
1464
1465static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = {
1466 .reg_pairs = sl_sgmii_link_cmn_regs,
1467 .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs),
1468};
1469
1470static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
1471 .reg_pairs = sl_sgmii_xcvr_diag_ln_regs,
1472 .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
1473};
1474
1475/* Multi link PCIe, 100 MHz Ref clk, internal SSC */
1476static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
1477 {0x0004, CMN_PLL0_DSM_DIAG_M0},
1478 {0x0004, CMN_PLL0_DSM_DIAG_M1},
1479 {0x0004, CMN_PLL1_DSM_DIAG_M0},
1480 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
1481 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
1482 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
1483 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
1484 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
1485 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
1486 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
1487 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
1488 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
1489 {0x0064, CMN_PLL0_INTDIV_M0},
1490 {0x0050, CMN_PLL0_INTDIV_M1},
1491 {0x0064, CMN_PLL1_INTDIV_M0},
1492 {0x0002, CMN_PLL0_FRACDIVH_M0},
1493 {0x0002, CMN_PLL0_FRACDIVH_M1},
1494 {0x0002, CMN_PLL1_FRACDIVH_M0},
1495 {0x0044, CMN_PLL0_HIGH_THR_M0},
1496 {0x0036, CMN_PLL0_HIGH_THR_M1},
1497 {0x0044, CMN_PLL1_HIGH_THR_M0},
1498 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
1499 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
1500 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
1501 {0x0001, CMN_PLL0_SS_CTRL1_M0},
1502 {0x0001, CMN_PLL0_SS_CTRL1_M1},
1503 {0x0001, CMN_PLL1_SS_CTRL1_M0},
1504 {0x011B, CMN_PLL0_SS_CTRL2_M0},
1505 {0x011B, CMN_PLL0_SS_CTRL2_M1},
1506 {0x011B, CMN_PLL1_SS_CTRL2_M0},
1507 {0x006E, CMN_PLL0_SS_CTRL3_M0},
1508 {0x0058, CMN_PLL0_SS_CTRL3_M1},
1509 {0x006E, CMN_PLL1_SS_CTRL3_M0},
1510 {0x000E, CMN_PLL0_SS_CTRL4_M0},
1511 {0x0012, CMN_PLL0_SS_CTRL4_M1},
1512 {0x000E, CMN_PLL1_SS_CTRL4_M0},
1513 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
1514 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
1515 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
1516 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
1517 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
1518 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
1519 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
1520 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
1521 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
1522 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
1523};
1524
1525static struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = {
1526 .reg_pairs = pcie_100_int_ssc_cmn_regs,
1527 .num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs),
1528};
1529
1530/* Single link PCIe, 100 MHz Ref clk, internal SSC */
1531static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = {
1532 {0x0004, CMN_PLL0_DSM_DIAG_M0},
1533 {0x0004, CMN_PLL0_DSM_DIAG_M1},
1534 {0x0004, CMN_PLL1_DSM_DIAG_M0},
1535 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
1536 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
1537 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
1538 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
1539 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
1540 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
1541 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
1542 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
1543 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
1544 {0x0064, CMN_PLL0_INTDIV_M0},
1545 {0x0050, CMN_PLL0_INTDIV_M1},
1546 {0x0050, CMN_PLL1_INTDIV_M0},
1547 {0x0002, CMN_PLL0_FRACDIVH_M0},
1548 {0x0002, CMN_PLL0_FRACDIVH_M1},
1549 {0x0002, CMN_PLL1_FRACDIVH_M0},
1550 {0x0044, CMN_PLL0_HIGH_THR_M0},
1551 {0x0036, CMN_PLL0_HIGH_THR_M1},
1552 {0x0036, CMN_PLL1_HIGH_THR_M0},
1553 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
1554 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
1555 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
1556 {0x0001, CMN_PLL0_SS_CTRL1_M0},
1557 {0x0001, CMN_PLL0_SS_CTRL1_M1},
1558 {0x0001, CMN_PLL1_SS_CTRL1_M0},
1559 {0x011B, CMN_PLL0_SS_CTRL2_M0},
1560 {0x011B, CMN_PLL0_SS_CTRL2_M1},
1561 {0x011B, CMN_PLL1_SS_CTRL2_M0},
1562 {0x006E, CMN_PLL0_SS_CTRL3_M0},
1563 {0x0058, CMN_PLL0_SS_CTRL3_M1},
1564 {0x0058, CMN_PLL1_SS_CTRL3_M0},
1565 {0x000E, CMN_PLL0_SS_CTRL4_M0},
1566 {0x0012, CMN_PLL0_SS_CTRL4_M1},
1567 {0x0012, CMN_PLL1_SS_CTRL4_M0},
1568 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
1569 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
1570 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
1571 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
1572 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
1573 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
1574 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
1575 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
1576 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
1577 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
1578};
1579
1580static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = {
1581 .reg_pairs = sl_pcie_100_int_ssc_cmn_regs,
1582 .num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs),
1583};
1584
1585/* PCIe, 100 MHz Ref clk, no SSC & external SSC */
1586static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = {
1587 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
1588 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
1589 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}
1590};
1591
1592static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = {
1593 {0x0019, RX_REE_TAP1_CLIP},
1594 {0x0019, RX_REE_TAP2TON_CLIP},
1595 {0x0001, RX_DIAG_ACYA}
1596};
1597
1598static struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = {
1599 .reg_pairs = pcie_100_ext_no_ssc_cmn_regs,
1600 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs),
1601};
1602
1603static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = {
1604 .reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs,
1605 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs),
1606};
1607
1608static const struct cdns_torrent_data cdns_map_torrent = {
1609 .block_offset_shift = 0x2,
1610 .reg_offset_shift = 0x2,
1611 .link_cmn_vals = {
1612 [TYPE_PCIE] = {
1613 [TYPE_NONE] = {
1614 [NO_SSC] = NULL,
1615 [EXTERNAL_SSC] = NULL,
1616 [INTERNAL_SSC] = NULL,
1617 },
1618 [TYPE_SGMII] = {
1619 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
1620 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
1621 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
1622 },
1623 [TYPE_QSGMII] = {
1624 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
1625 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
1626 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
1627 },
1628 [TYPE_USB] = {
1629 [NO_SSC] = &pcie_usb_link_cmn_vals,
1630 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
1631 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
1632 },
1633 },
1634 [TYPE_SGMII] = {
1635 [TYPE_NONE] = {
1636 [NO_SSC] = &sl_sgmii_link_cmn_vals,
1637 },
1638 [TYPE_PCIE] = {
1639 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
1640 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
1641 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
1642 },
1643 [TYPE_USB] = {
1644 [NO_SSC] = &usb_sgmii_link_cmn_vals,
1645 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
1646 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
1647 },
1648 },
1649 [TYPE_QSGMII] = {
1650 [TYPE_NONE] = {
1651 [NO_SSC] = &sl_sgmii_link_cmn_vals,
1652 },
1653 [TYPE_PCIE] = {
1654 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
1655 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
1656 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
1657 },
1658 [TYPE_USB] = {
1659 [NO_SSC] = &usb_sgmii_link_cmn_vals,
1660 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
1661 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
1662 },
1663 },
1664 [TYPE_USB] = {
1665 [TYPE_NONE] = {
1666 [NO_SSC] = &sl_usb_link_cmn_vals,
1667 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
1668 [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
1669 },
1670 [TYPE_PCIE] = {
1671 [NO_SSC] = &pcie_usb_link_cmn_vals,
1672 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
1673 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
1674 },
1675 [TYPE_SGMII] = {
1676 [NO_SSC] = &usb_sgmii_link_cmn_vals,
1677 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
1678 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
1679 },
1680 [TYPE_QSGMII] = {
1681 [NO_SSC] = &usb_sgmii_link_cmn_vals,
1682 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
1683 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
1684 },
1685 },
1686 },
1687 .xcvr_diag_vals = {
1688 [TYPE_PCIE] = {
1689 [TYPE_NONE] = {
1690 [NO_SSC] = NULL,
1691 [EXTERNAL_SSC] = NULL,
1692 [INTERNAL_SSC] = NULL,
1693 },
1694 [TYPE_SGMII] = {
1695 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
1696 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
1697 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
1698 },
1699 [TYPE_QSGMII] = {
1700 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
1701 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
1702 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
1703 },
1704 [TYPE_USB] = {
1705 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
1706 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
1707 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
1708 },
1709 },
1710 [TYPE_SGMII] = {
1711 [TYPE_NONE] = {
1712 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
1713 },
1714 [TYPE_PCIE] = {
1715 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
1716 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
1717 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
1718 },
1719 [TYPE_USB] = {
1720 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
1721 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
1722 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
1723 },
1724 },
1725 [TYPE_QSGMII] = {
1726 [TYPE_NONE] = {
1727 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
1728 },
1729 [TYPE_PCIE] = {
1730 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
1731 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
1732 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
1733 },
1734 [TYPE_USB] = {
1735 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
1736 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
1737 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
1738 },
1739 },
1740 [TYPE_USB] = {
1741 [TYPE_NONE] = {
1742 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
1743 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
1744 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
1745 },
1746 [TYPE_PCIE] = {
1747 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
1748 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
1749 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
1750 },
1751 [TYPE_SGMII] = {
1752 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
1753 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
1754 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
1755 },
1756 [TYPE_QSGMII] = {
1757 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
1758 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
1759 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
1760 },
1761 },
1762 },
1763 .pcs_cmn_vals = {
1764 [TYPE_USB] = {
1765 [TYPE_NONE] = {
1766 [NO_SSC] = &usb_phy_pcs_cmn_vals,
1767 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
1768 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
1769 },
1770 [TYPE_PCIE] = {
1771 [NO_SSC] = &usb_phy_pcs_cmn_vals,
1772 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
1773 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
1774 },
1775 [TYPE_SGMII] = {
1776 [NO_SSC] = &usb_phy_pcs_cmn_vals,
1777 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
1778 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
1779 },
1780 [TYPE_QSGMII] = {
1781 [NO_SSC] = &usb_phy_pcs_cmn_vals,
1782 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
1783 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
1784 },
1785 },
1786 },
1787 .cmn_vals = {
1788 [TYPE_PCIE] = {
1789 [TYPE_NONE] = {
1790 [NO_SSC] = NULL,
1791 [EXTERNAL_SSC] = NULL,
1792 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
1793 },
1794 [TYPE_SGMII] = {
1795 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
1796 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
1797 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
1798 },
1799 [TYPE_QSGMII] = {
1800 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
1801 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
1802 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
1803 },
1804 [TYPE_USB] = {
1805 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
1806 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
1807 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
1808 },
1809 },
1810 [TYPE_SGMII] = {
1811 [TYPE_NONE] = {
1812 [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
1813 },
1814 [TYPE_PCIE] = {
1815 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
1816 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
1817 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
1818 },
1819 [TYPE_USB] = {
1820 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
1821 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
1822 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
1823 },
1824 },
1825 [TYPE_QSGMII] = {
1826 [TYPE_NONE] = {
1827 [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
1828 },
1829 [TYPE_PCIE] = {
1830 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
1831 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
1832 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
1833 },
1834 [TYPE_USB] = {
1835 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
1836 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
1837 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
1838 },
1839 },
1840 [TYPE_USB] = {
1841 [TYPE_NONE] = {
1842 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
1843 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
1844 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
1845 },
1846 [TYPE_PCIE] = {
1847 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
1848 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
1849 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
1850 },
1851 [TYPE_SGMII] = {
1852 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
1853 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
1854 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
1855 },
1856 [TYPE_QSGMII] = {
1857 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
1858 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
1859 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
1860 },
1861 },
1862 },
1863 .tx_ln_vals = {
1864 [TYPE_PCIE] = {
1865 [TYPE_NONE] = {
1866 [NO_SSC] = NULL,
1867 [EXTERNAL_SSC] = NULL,
1868 [INTERNAL_SSC] = NULL,
1869 },
1870 [TYPE_SGMII] = {
1871 [NO_SSC] = NULL,
1872 [EXTERNAL_SSC] = NULL,
1873 [INTERNAL_SSC] = NULL,
1874 },
1875 [TYPE_QSGMII] = {
1876 [NO_SSC] = NULL,
1877 [EXTERNAL_SSC] = NULL,
1878 [INTERNAL_SSC] = NULL,
1879 },
1880 [TYPE_USB] = {
1881 [NO_SSC] = NULL,
1882 [EXTERNAL_SSC] = NULL,
1883 [INTERNAL_SSC] = NULL,
1884 },
1885 },
1886 [TYPE_SGMII] = {
1887 [TYPE_NONE] = {
1888 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
1889 },
1890 [TYPE_PCIE] = {
1891 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
1892 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
1893 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
1894 },
1895 [TYPE_USB] = {
1896 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
1897 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
1898 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
1899 },
1900 },
1901 [TYPE_QSGMII] = {
1902 [TYPE_NONE] = {
1903 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
1904 },
1905 [TYPE_PCIE] = {
1906 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
1907 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
1908 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
1909 },
1910 [TYPE_USB] = {
1911 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
1912 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
1913 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
1914 },
1915 },
1916 [TYPE_USB] = {
1917 [TYPE_NONE] = {
1918 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
1919 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
1920 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
1921 },
1922 [TYPE_PCIE] = {
1923 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
1924 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
1925 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
1926 },
1927 [TYPE_SGMII] = {
1928 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
1929 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
1930 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
1931 },
1932 [TYPE_QSGMII] = {
1933 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
1934 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
1935 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
1936 },
1937 },
1938 },
1939 .rx_ln_vals = {
1940 [TYPE_PCIE] = {
1941 [TYPE_NONE] = {
1942 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1943 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1944 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1945 },
1946 [TYPE_SGMII] = {
1947 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1948 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1949 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1950 },
1951 [TYPE_QSGMII] = {
1952 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1953 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1954 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1955 },
1956 [TYPE_USB] = {
1957 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1958 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1959 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1960 },
1961 },
1962 [TYPE_SGMII] = {
1963 [TYPE_NONE] = {
1964 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
1965 },
1966 [TYPE_PCIE] = {
1967 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
1968 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
1969 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
1970 },
1971 [TYPE_USB] = {
1972 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
1973 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
1974 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
1975 },
1976 },
1977 [TYPE_QSGMII] = {
1978 [TYPE_NONE] = {
1979 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
1980 },
1981 [TYPE_PCIE] = {
1982 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
1983 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
1984 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
1985 },
1986 [TYPE_USB] = {
1987 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
1988 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
1989 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
1990 },
1991 },
1992 [TYPE_USB] = {
1993 [TYPE_NONE] = {
1994 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
1995 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
1996 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
1997 },
1998 [TYPE_PCIE] = {
1999 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
2000 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2001 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2002 },
2003 [TYPE_SGMII] = {
2004 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
2005 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2006 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2007 },
2008 [TYPE_QSGMII] = {
2009 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
2010 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2011 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2012 },
2013 },
2014 },
2015};
2016
2017static const struct cdns_torrent_data ti_j721e_map_torrent = {
2018 .block_offset_shift = 0x0,
2019 .reg_offset_shift = 0x1,
2020 .link_cmn_vals = {
2021 [TYPE_PCIE] = {
2022 [TYPE_NONE] = {
2023 [NO_SSC] = NULL,
2024 [EXTERNAL_SSC] = NULL,
2025 [INTERNAL_SSC] = NULL,
2026 },
2027 [TYPE_SGMII] = {
2028 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
2029 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
2030 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
2031 },
2032 [TYPE_QSGMII] = {
2033 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
2034 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
2035 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
2036 },
2037 [TYPE_USB] = {
2038 [NO_SSC] = &pcie_usb_link_cmn_vals,
2039 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
2040 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
2041 },
2042 },
2043 [TYPE_SGMII] = {
2044 [TYPE_NONE] = {
2045 [NO_SSC] = &sl_sgmii_link_cmn_vals,
2046 },
2047 [TYPE_PCIE] = {
2048 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
2049 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
2050 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
2051 },
2052 [TYPE_USB] = {
2053 [NO_SSC] = &usb_sgmii_link_cmn_vals,
2054 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
2055 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
2056 },
2057 },
2058 [TYPE_QSGMII] = {
2059 [TYPE_NONE] = {
2060 [NO_SSC] = &sl_sgmii_link_cmn_vals,
2061 },
2062 [TYPE_PCIE] = {
2063 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
2064 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
2065 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
2066 },
2067 [TYPE_USB] = {
2068 [NO_SSC] = &usb_sgmii_link_cmn_vals,
2069 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
2070 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
2071 },
2072 },
2073 [TYPE_USB] = {
2074 [TYPE_NONE] = {
2075 [NO_SSC] = &sl_usb_link_cmn_vals,
2076 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
2077 [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
2078 },
2079 [TYPE_PCIE] = {
2080 [NO_SSC] = &pcie_usb_link_cmn_vals,
2081 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
2082 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
2083 },
2084 [TYPE_SGMII] = {
2085 [NO_SSC] = &usb_sgmii_link_cmn_vals,
2086 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
2087 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
2088 },
2089 [TYPE_QSGMII] = {
2090 [NO_SSC] = &usb_sgmii_link_cmn_vals,
2091 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
2092 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
2093 },
2094 },
2095 },
2096 .xcvr_diag_vals = {
2097 [TYPE_PCIE] = {
2098 [TYPE_NONE] = {
2099 [NO_SSC] = NULL,
2100 [EXTERNAL_SSC] = NULL,
2101 [INTERNAL_SSC] = NULL,
2102 },
2103 [TYPE_SGMII] = {
2104 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
2105 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
2106 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
2107 },
2108 [TYPE_QSGMII] = {
2109 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
2110 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
2111 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
2112 },
2113 [TYPE_USB] = {
2114 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
2115 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
2116 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
2117 },
2118 },
2119 [TYPE_SGMII] = {
2120 [TYPE_NONE] = {
2121 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
2122 },
2123 [TYPE_PCIE] = {
2124 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
2125 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
2126 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
2127 },
2128 [TYPE_USB] = {
2129 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
2130 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
2131 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
2132 },
2133 },
2134 [TYPE_QSGMII] = {
2135 [TYPE_NONE] = {
2136 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
2137 },
2138 [TYPE_PCIE] = {
2139 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
2140 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
2141 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
2142 },
2143 [TYPE_USB] = {
2144 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
2145 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
2146 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
2147 },
2148 },
2149 [TYPE_USB] = {
2150 [TYPE_NONE] = {
2151 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
2152 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
2153 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
2154 },
2155 [TYPE_PCIE] = {
2156 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
2157 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
2158 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
2159 },
2160 [TYPE_SGMII] = {
2161 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
2162 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
2163 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
2164 },
2165 [TYPE_QSGMII] = {
2166 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
2167 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
2168 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
2169 },
2170 },
2171 },
2172 .pcs_cmn_vals = {
2173 [TYPE_USB] = {
2174 [TYPE_NONE] = {
2175 [NO_SSC] = &usb_phy_pcs_cmn_vals,
2176 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
2177 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
2178 },
2179 [TYPE_PCIE] = {
2180 [NO_SSC] = &usb_phy_pcs_cmn_vals,
2181 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
2182 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
2183 },
2184 [TYPE_SGMII] = {
2185 [NO_SSC] = &usb_phy_pcs_cmn_vals,
2186 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
2187 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
2188 },
2189 [TYPE_QSGMII] = {
2190 [NO_SSC] = &usb_phy_pcs_cmn_vals,
2191 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
2192 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
2193 },
2194 },
2195 },
2196 .cmn_vals = {
2197 [TYPE_PCIE] = {
2198 [TYPE_NONE] = {
2199 [NO_SSC] = NULL,
2200 [EXTERNAL_SSC] = NULL,
2201 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
2202 },
2203 [TYPE_SGMII] = {
2204 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
2205 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
2206 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
2207 },
2208 [TYPE_QSGMII] = {
2209 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
2210 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
2211 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
2212 },
2213 [TYPE_USB] = {
2214 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
2215 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
2216 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
2217 },
2218 },
2219 [TYPE_SGMII] = {
2220 [TYPE_NONE] = {
2221 [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
2222 },
2223 [TYPE_PCIE] = {
2224 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
2225 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
2226 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
2227 },
2228 [TYPE_USB] = {
2229 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
2230 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
2231 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
2232 },
2233 },
2234 [TYPE_QSGMII] = {
2235 [TYPE_NONE] = {
2236 [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
2237 },
2238 [TYPE_PCIE] = {
2239 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
2240 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
2241 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
2242 },
2243 [TYPE_USB] = {
2244 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
2245 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
2246 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
2247 },
2248 },
2249 [TYPE_USB] = {
2250 [TYPE_NONE] = {
2251 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
2252 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
2253 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
2254 },
2255 [TYPE_PCIE] = {
2256 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
2257 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
2258 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
2259 },
2260 [TYPE_SGMII] = {
2261 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
2262 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
2263 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
2264 },
2265 [TYPE_QSGMII] = {
2266 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
2267 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
2268 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
2269 },
2270 },
2271 },
2272 .tx_ln_vals = {
2273 [TYPE_PCIE] = {
2274 [TYPE_NONE] = {
2275 [NO_SSC] = NULL,
2276 [EXTERNAL_SSC] = NULL,
2277 [INTERNAL_SSC] = NULL,
2278 },
2279 [TYPE_SGMII] = {
2280 [NO_SSC] = NULL,
2281 [EXTERNAL_SSC] = NULL,
2282 [INTERNAL_SSC] = NULL,
2283 },
2284 [TYPE_QSGMII] = {
2285 [NO_SSC] = NULL,
2286 [EXTERNAL_SSC] = NULL,
2287 [INTERNAL_SSC] = NULL,
2288 },
2289 [TYPE_USB] = {
2290 [NO_SSC] = NULL,
2291 [EXTERNAL_SSC] = NULL,
2292 [INTERNAL_SSC] = NULL,
2293 },
2294 },
2295 [TYPE_SGMII] = {
2296 [TYPE_NONE] = {
2297 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
2298 },
2299 [TYPE_PCIE] = {
2300 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
2301 [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
2302 [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
2303 },
2304 [TYPE_USB] = {
2305 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
2306 [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
2307 [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
2308 },
2309 },
2310 [TYPE_QSGMII] = {
2311 [TYPE_NONE] = {
2312 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
2313 },
2314 [TYPE_PCIE] = {
2315 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
2316 [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
2317 [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
2318 },
2319 [TYPE_USB] = {
2320 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
2321 [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
2322 [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
2323 },
2324 },
2325 [TYPE_USB] = {
2326 [TYPE_NONE] = {
2327 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
2328 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
2329 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
2330 },
2331 [TYPE_PCIE] = {
2332 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
2333 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
2334 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
2335 },
2336 [TYPE_SGMII] = {
2337 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
2338 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
2339 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
2340 },
2341 [TYPE_QSGMII] = {
2342 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
2343 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
2344 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
2345 },
2346 },
2347 },
2348 .rx_ln_vals = {
2349 [TYPE_PCIE] = {
2350 [TYPE_NONE] = {
2351 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2352 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2353 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2354 },
2355 [TYPE_SGMII] = {
2356 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2357 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2358 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2359 },
2360 [TYPE_QSGMII] = {
2361 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2362 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2363 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2364 },
2365 [TYPE_USB] = {
2366 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2367 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2368 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2369 },
2370 },
2371 [TYPE_SGMII] = {
2372 [TYPE_NONE] = {
2373 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
2374 },
2375 [TYPE_PCIE] = {
2376 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
2377 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
2378 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
2379 },
2380 [TYPE_USB] = {
2381 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
2382 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
2383 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
2384 },
2385 },
2386 [TYPE_QSGMII] = {
2387 [TYPE_NONE] = {
2388 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
2389 },
2390 [TYPE_PCIE] = {
2391 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
2392 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
2393 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
2394 },
2395 [TYPE_USB] = {
2396 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
2397 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
2398 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
2399 },
2400 },
2401 [TYPE_USB] = {
2402 [TYPE_NONE] = {
2403 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
2404 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2405 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2406 },
2407 [TYPE_PCIE] = {
2408 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
2409 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2410 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2411 },
2412 [TYPE_SGMII] = {
2413 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
2414 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2415 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2416 },
2417 [TYPE_QSGMII] = {
2418 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
2419 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2420 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2421 },
2422 },
2423 },
2424};
2425
2426static int cdns_torrent_phy_reset(struct phy *gphy)
2427{
2428 struct cdns_torrent_phy *sp = dev_get_priv(gphy->dev);
2429
2430 reset_control_assert(sp->phy_rst);
2431 reset_control_deassert(sp->phy_rst);
2432 return 0;
2433}
2434
2435static const struct udevice_id cdns_torrent_id_table[] = {
2436 {
2437 .compatible = "cdns,torrent-phy",
2438 .data = (ulong)&cdns_map_torrent,
2439 },
2440 {
2441 .compatible = "ti,j721e-serdes-10g",
2442 .data = (ulong)&ti_j721e_map_torrent,
2443 },
2444 {}
2445};
2446
2447static const struct phy_ops cdns_torrent_phy_ops = {
2448 .init = cdns_torrent_phy_init,
2449 .power_on = cdns_torrent_phy_on,
2450 .power_off = cdns_torrent_phy_off,
2451 .reset = cdns_torrent_phy_reset,
2452};
2453
2454U_BOOT_DRIVER(torrent_phy_provider) = {
2455 .name = "cdns,torrent",
2456 .id = UCLASS_PHY,
2457 .of_match = cdns_torrent_id_table,
2458 .probe = cdns_torrent_phy_probe,
2459 .remove = cdns_torrent_phy_remove,
2460 .ops = &cdns_torrent_phy_ops,
2461 .priv_auto = sizeof(struct cdns_torrent_phy),
2462};