blob: d39b87b2e245fce46ac417f800f0f730878dd0bb [file] [log] [blame]
Peng Fan5e80d5a2018-10-18 14:28:30 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2018 NXP
4 * Peng Fan <peng.fan@nxp.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -070011#include <malloc.h>
Peng Fan2e0644a2023-04-28 12:08:09 +080012#include <firmware/imx/sci/sci.h>
Peng Fan5e80d5a2018-10-18 14:28:30 +020013#include <asm/arch/clock.h>
14#include <dt-bindings/clock/imx8qxp-clock.h>
15#include <dt-bindings/soc/imx_rsrc.h>
16#include <misc.h>
17
Peng Fan6a8e5f92019-03-05 02:32:33 +000018#include "clk-imx8.h"
Peng Fan5e80d5a2018-10-18 14:28:30 +020019
Peng Fan6a8e5f92019-03-05 02:32:33 +000020__weak ulong imx8_clk_get_rate(struct clk *clk)
Peng Fan5e80d5a2018-10-18 14:28:30 +020021{
Peng Fan6a8e5f92019-03-05 02:32:33 +000022 return 0;
Peng Fan5e80d5a2018-10-18 14:28:30 +020023}
24
Peng Fan6a8e5f92019-03-05 02:32:33 +000025__weak ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
Peng Fan5e80d5a2018-10-18 14:28:30 +020026{
Peng Fan6a8e5f92019-03-05 02:32:33 +000027 return 0;
Peng Fan5e80d5a2018-10-18 14:28:30 +020028}
29
Peng Fan6a8e5f92019-03-05 02:32:33 +000030__weak int __imx8_clk_enable(struct clk *clk, bool enable)
Peng Fan5e80d5a2018-10-18 14:28:30 +020031{
Simon Glass29ff16a2021-03-25 10:26:08 +130032 return -EINVAL;
Peng Fan5e80d5a2018-10-18 14:28:30 +020033}
34
35static int imx8_clk_disable(struct clk *clk)
36{
37 return __imx8_clk_enable(clk, 0);
38}
39
40static int imx8_clk_enable(struct clk *clk)
41{
42 return __imx8_clk_enable(clk, 1);
43}
44
Simon Glass495e80f2023-02-05 15:36:26 -070045#if IS_ENABLED(CONFIG_CMD_CLK)
Igor Prusov1a3427b2023-11-09 13:55:15 +030046static void imx8_clk_dump(struct udevice *dev)
Peng Fan5e80d5a2018-10-18 14:28:30 +020047{
Peng Fan5e80d5a2018-10-18 14:28:30 +020048 struct clk clk;
49 unsigned long rate;
50 int i, ret;
51
Peng Fan5e80d5a2018-10-18 14:28:30 +020052 printf("Clk\t\tHz\n");
53
Peng Fan6a8e5f92019-03-05 02:32:33 +000054 for (i = 0; i < num_clks; i++) {
Peng Fan5e80d5a2018-10-18 14:28:30 +020055 clk.id = imx8_clk_names[i].id;
56 ret = clk_request(dev, &clk);
57 if (ret < 0) {
58 debug("%s clk_request() failed: %d\n", __func__, ret);
59 continue;
60 }
61
62 ret = clk_get_rate(&clk);
63 rate = ret;
64
Simon Glass29ff16a2021-03-25 10:26:08 +130065 if (ret == -EINVAL) {
Peng Fan5e80d5a2018-10-18 14:28:30 +020066 printf("clk ID %lu not supported yet\n",
67 imx8_clk_names[i].id);
68 continue;
69 }
70 if (ret < 0) {
71 printf("%s %lu: get_rate err: %d\n",
72 __func__, imx8_clk_names[i].id, ret);
73 continue;
74 }
75
76 printf("%s(%3lu):\t%lu\n",
77 imx8_clk_names[i].name, imx8_clk_names[i].id, rate);
78 }
Peng Fan5e80d5a2018-10-18 14:28:30 +020079}
80#endif
81
82static struct clk_ops imx8_clk_ops = {
83 .set_rate = imx8_clk_set_rate,
84 .get_rate = imx8_clk_get_rate,
85 .enable = imx8_clk_enable,
86 .disable = imx8_clk_disable,
Igor Prusov1a3427b2023-11-09 13:55:15 +030087#if IS_ENABLED(CONFIG_CMD_CLK)
88 .dump = imx8_clk_dump,
89#endif
Peng Fan5e80d5a2018-10-18 14:28:30 +020090};
91
92static int imx8_clk_probe(struct udevice *dev)
93{
94 return 0;
95}
96
97static const struct udevice_id imx8_clk_ids[] = {
98 { .compatible = "fsl,imx8qxp-clk" },
Peng Fan9a0dc912019-03-05 02:32:35 +000099 { .compatible = "fsl,imx8qm-clk" },
Peng Fan5e80d5a2018-10-18 14:28:30 +0200100 { },
101};
102
103U_BOOT_DRIVER(imx8_clk) = {
104 .name = "clk_imx8",
105 .id = UCLASS_CLK,
106 .of_match = imx8_clk_ids,
107 .ops = &imx8_clk_ops,
108 .probe = imx8_clk_probe,
109 .flags = DM_FLAG_PRE_RELOC,
110};