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wdenkde887eb2003-09-10 18:20:28 +00001/*
2 * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400.
3 *
4 * (C) Copyright 2003
Detlev Zundelf1b3f2b2009-05-13 10:54:10 +02005 * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
wdenkde887eb2003-09-10 18:20:28 +00006 *
wdenkbfad55d2005-03-14 23:56:42 +00007 * Note: Much of this code has been derived from Linux 2.4
8 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
9 * (C) Copyright 2000-2002 David Brownell
10 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020011 * SPDX-License-Identifier: GPL-2.0+
wdenkde887eb2003-09-10 18:20:28 +000012 */
13/*
14 * IMPORTANT NOTES
Mike Frysingercc93fc02009-01-01 18:27:27 -050015 * 1 - this driver is intended for use with USB Mass Storage Devices
wdenkde887eb2003-09-10 18:20:28 +000016 * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
17 */
18
19#include <common.h>
wdenk4ea537d2003-12-07 18:32:37 +000020/* #include <pci.h> no PCI on the S3C24X0 */
wdenkde887eb2003-09-10 18:20:28 +000021
kevin.morfitt@fearnside-systems.co.uke0d81312009-11-17 18:30:34 +090022#if defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0)
wdenkde887eb2003-09-10 18:20:28 +000023
kevin.morfitt@fearnside-systems.co.uke0d81312009-11-17 18:30:34 +090024#include <asm/arch/s3c24x0_cpu.h>
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +090025#include <asm/io.h>
wdenkde887eb2003-09-10 18:20:28 +000026#include <malloc.h>
27#include <usb.h>
Marek Vasute917a7c2012-07-21 05:02:22 +000028#include "ohci-s3c24xx.h"
wdenkde887eb2003-09-10 18:20:28 +000029
30#define OHCI_USE_NPS /* force NoPowerSwitching mode */
31#undef OHCI_VERBOSE_DEBUG /* not always helpful */
32
33
34/* For initializing controller (mask in an HCFS mode too) */
35#define OHCI_CONTROL_INIT \
36 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
37
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +090038#define min_t(type, x, y) \
39 ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
wdenkde887eb2003-09-10 18:20:28 +000040
41#undef DEBUG
42#ifdef DEBUG
43#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
44#else
45#define dbg(format, arg...) do {} while(0)
46#endif /* DEBUG */
47#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
48#undef SHOW_INFO
49#ifdef SHOW_INFO
50#define info(format, arg...) printf("INFO: " format "\n", ## arg)
51#else
52#define info(format, arg...) do {} while(0)
53#endif
54
55#define m16_swap(x) swap_16(x)
56#define m32_swap(x) swap_32(x)
57
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +090058/* global struct ohci */
59static struct ohci gohci;
wdenkde887eb2003-09-10 18:20:28 +000060/* this must be aligned to a 256 byte boundary */
61struct ohci_hcca ghcca[1];
62/* a pointer to the aligned storage */
63struct ohci_hcca *phcca;
64/* this allocates EDs for all possible endpoints */
65struct ohci_device ohci_dev;
66/* urb_priv */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +090067struct urb_priv urb_priv;
dzu8d7e4d12003-09-29 21:55:54 +000068/* RHSC flag */
69int got_rhsc;
70/* device which was disconnected */
71struct usb_device *devgone;
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +020072/* flag guarding URB transation */
73int urb_finished = 0;
wdenkde887eb2003-09-10 18:20:28 +000074
75/*-------------------------------------------------------------------------*/
76
77/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
78 * The erratum (#4) description is incorrect. AMD's workaround waits
79 * till some bits (mostly reserved) are clear; ok for all revs.
80 */
81#define OHCI_QUIRK_AMD756 0xabcd
82#define read_roothub(hc, register, mask) ({ \
83 u32 temp = readl (&hc->regs->roothub.register); \
84 if (hc->flags & OHCI_QUIRK_AMD756) \
85 while (temp & mask) \
86 temp = readl (&hc->regs->roothub.register); \
87 temp; })
88
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +090089static u32 roothub_a(struct ohci *hc)
90{
91 return read_roothub(hc, a, 0xfc0fe000);
92}
93static inline u32 roothub_b(struct ohci *hc)
94{
95 return readl(&hc->regs->roothub.b);
96}
97static inline u32 roothub_status(struct ohci *hc)
98{
99 return readl(&hc->regs->roothub.status);
100}
101static u32 roothub_portstatus(struct ohci *hc, int i)
102{
103 return read_roothub(hc, portstatus[i], 0xffe0fce0);
104}
wdenkde887eb2003-09-10 18:20:28 +0000105
106/* forward declaration */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900107static int hc_interrupt(void);
108static void td_submit_job(struct usb_device *dev, unsigned long pipe,
109 void *buffer, int transfer_len,
110 struct devrequest *setup, struct urb_priv *urb,
111 int interval);
wdenkde887eb2003-09-10 18:20:28 +0000112
113/*-------------------------------------------------------------------------*
114 * URB support functions
115 *-------------------------------------------------------------------------*/
116
117/* free HCD-private data associated with this URB */
118
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900119static void urb_free_priv(struct urb_priv *urb)
wdenkde887eb2003-09-10 18:20:28 +0000120{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900121 int i;
122 int last;
123 struct td *td;
wdenkde887eb2003-09-10 18:20:28 +0000124
125 last = urb->length - 1;
126 if (last >= 0) {
127 for (i = 0; i <= last; i++) {
128 td = urb->td[i];
129 if (td) {
130 td->usb_dev = NULL;
131 urb->td[i] = NULL;
132 }
133 }
134 }
135}
136
137/*-------------------------------------------------------------------------*/
138
139#ifdef DEBUG
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900140static int sohci_get_current_frame_number(struct usb_device *dev);
wdenkde887eb2003-09-10 18:20:28 +0000141
142/* debug| print the main components of an URB
143 * small: 0) header + data packets 1) just header */
144
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900145static void pkt_print(struct usb_device *dev, unsigned long pipe, void *buffer,
146 int transfer_len, struct devrequest *setup, char *str,
147 int small)
wdenkde887eb2003-09-10 18:20:28 +0000148{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900149 struct urb_priv *purb = &urb_priv;
wdenkde887eb2003-09-10 18:20:28 +0000150
151 dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900152 str,
153 sohci_get_current_frame_number(dev),
154 usb_pipedevice(pipe),
155 usb_pipeendpoint(pipe),
156 usb_pipeout(pipe) ? 'O' : 'I',
157 usb_pipetype(pipe) < 2 ?
158 (usb_pipeint(pipe) ? "INTR" : "ISOC") :
159 (usb_pipecontrol(pipe) ? "CTRL" : "BULK"),
160 purb->actual_length, transfer_len, dev->status);
wdenkde887eb2003-09-10 18:20:28 +0000161#ifdef OHCI_VERBOSE_DEBUG
162 if (!small) {
163 int i, len;
164
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900165 if (usb_pipecontrol(pipe)) {
166 printf(__FILE__ ": cmd(8):");
167 for (i = 0; i < 8; i++)
168 printf(" %02x", ((__u8 *) setup)[i]);
169 printf("\n");
wdenkde887eb2003-09-10 18:20:28 +0000170 }
171 if (transfer_len > 0 && buffer) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900172 printf(__FILE__ ": data(%d/%d):",
173 purb->actual_length, transfer_len);
174 len = usb_pipeout(pipe) ?
175 transfer_len : purb->actual_length;
wdenkde887eb2003-09-10 18:20:28 +0000176 for (i = 0; i < 16 && i < len; i++)
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900177 printf(" %02x", ((__u8 *) buffer)[i]);
178 printf("%s\n", i < len ? "..." : "");
wdenkde887eb2003-09-10 18:20:28 +0000179 }
180 }
181#endif
182}
183
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900184/* just for debugging; prints non-empty branches of the
185 int ed tree inclusive iso eds*/
186void ep_print_int_eds(struct ohci *ohci, char *str)
187{
wdenkde887eb2003-09-10 18:20:28 +0000188 int i, j;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900189 __u32 *ed_p;
190 for (i = 0; i < 32; i++) {
wdenkde887eb2003-09-10 18:20:28 +0000191 j = 5;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900192 ed_p = &(ohci->hcca->int_table[i]);
wdenkde887eb2003-09-10 18:20:28 +0000193 if (*ed_p == 0)
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900194 continue;
195 printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
wdenkde887eb2003-09-10 18:20:28 +0000196 while (*ed_p != 0 && j--) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900197 struct ed *ed = (struct ed *) m32_swap(ed_p);
198 printf(" ed: %4x;", ed->hwINFO);
wdenkde887eb2003-09-10 18:20:28 +0000199 ed_p = &ed->hwNextED;
200 }
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900201 printf("\n");
wdenkde887eb2003-09-10 18:20:28 +0000202 }
203}
204
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900205static void ohci_dump_intr_mask(char *label, __u32 mask)
wdenkde887eb2003-09-10 18:20:28 +0000206{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900207 dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
208 label,
209 mask,
210 (mask & OHCI_INTR_MIE) ? " MIE" : "",
211 (mask & OHCI_INTR_OC) ? " OC" : "",
212 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
213 (mask & OHCI_INTR_FNO) ? " FNO" : "",
214 (mask & OHCI_INTR_UE) ? " UE" : "",
215 (mask & OHCI_INTR_RD) ? " RD" : "",
216 (mask & OHCI_INTR_SF) ? " SF" : "",
217 (mask & OHCI_INTR_WDH) ? " WDH" : "",
218 (mask & OHCI_INTR_SO) ? " SO" : "");
wdenkde887eb2003-09-10 18:20:28 +0000219}
220
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900221static void maybe_print_eds(char *label, __u32 value)
wdenkde887eb2003-09-10 18:20:28 +0000222{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900223 struct ed *edp = (struct ed *) value;
wdenkde887eb2003-09-10 18:20:28 +0000224
225 if (value) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900226 dbg("%s %08x", label, value);
227 dbg("%08x", edp->hwINFO);
228 dbg("%08x", edp->hwTailP);
229 dbg("%08x", edp->hwHeadP);
230 dbg("%08x", edp->hwNextED);
wdenkde887eb2003-09-10 18:20:28 +0000231 }
232}
233
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900234static char *hcfs2string(int state)
wdenkde887eb2003-09-10 18:20:28 +0000235{
236 switch (state) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900237 case OHCI_USB_RESET:
238 return "reset";
239 case OHCI_USB_RESUME:
240 return "resume";
241 case OHCI_USB_OPER:
242 return "operational";
243 case OHCI_USB_SUSPEND:
244 return "suspend";
wdenkde887eb2003-09-10 18:20:28 +0000245 }
246 return "?";
247}
248
249/* dump control and status registers */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900250static void ohci_dump_status(struct ohci *controller)
wdenkde887eb2003-09-10 18:20:28 +0000251{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900252 struct ohci_regs *regs = controller->regs;
253 __u32 temp;
wdenkde887eb2003-09-10 18:20:28 +0000254
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900255 temp = readl(&regs->revision) & 0xff;
wdenkde887eb2003-09-10 18:20:28 +0000256 if (temp != 0x10)
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900257 dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
wdenkde887eb2003-09-10 18:20:28 +0000258
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900259 temp = readl(&regs->control);
260 dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
261 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
262 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
263 (temp & OHCI_CTRL_IR) ? " IR" : "",
264 hcfs2string(temp & OHCI_CTRL_HCFS),
265 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
266 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
267 (temp & OHCI_CTRL_IE) ? " IE" : "",
268 (temp & OHCI_CTRL_PLE) ? " PLE" : "", temp & OHCI_CTRL_CBSR);
wdenkde887eb2003-09-10 18:20:28 +0000269
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900270 temp = readl(&regs->cmdstatus);
271 dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
272 (temp & OHCI_SOC) >> 16,
273 (temp & OHCI_OCR) ? " OCR" : "",
274 (temp & OHCI_BLF) ? " BLF" : "",
275 (temp & OHCI_CLF) ? " CLF" : "", (temp & OHCI_HCR) ? " HCR" : "");
wdenkde887eb2003-09-10 18:20:28 +0000276
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900277 ohci_dump_intr_mask("intrstatus", readl(&regs->intrstatus));
278 ohci_dump_intr_mask("intrenable", readl(&regs->intrenable));
wdenkde887eb2003-09-10 18:20:28 +0000279
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900280 maybe_print_eds("ed_periodcurrent", readl(&regs->ed_periodcurrent));
wdenkde887eb2003-09-10 18:20:28 +0000281
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900282 maybe_print_eds("ed_controlhead", readl(&regs->ed_controlhead));
283 maybe_print_eds("ed_controlcurrent", readl(&regs->ed_controlcurrent));
wdenkde887eb2003-09-10 18:20:28 +0000284
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900285 maybe_print_eds("ed_bulkhead", readl(&regs->ed_bulkhead));
286 maybe_print_eds("ed_bulkcurrent", readl(&regs->ed_bulkcurrent));
wdenkde887eb2003-09-10 18:20:28 +0000287
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900288 maybe_print_eds("donehead", readl(&regs->donehead));
wdenkde887eb2003-09-10 18:20:28 +0000289}
290
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900291static void ohci_dump_roothub(struct ohci *controller, int verbose)
wdenkde887eb2003-09-10 18:20:28 +0000292{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900293 __u32 temp, ndp, i;
wdenkde887eb2003-09-10 18:20:28 +0000294
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900295 temp = roothub_a(controller);
wdenkde887eb2003-09-10 18:20:28 +0000296 ndp = (temp & RH_A_NDP);
297
298 if (verbose) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900299 dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
300 ((temp & RH_A_POTPGT) >> 24) & 0xff,
301 (temp & RH_A_NOCP) ? " NOCP" : "",
302 (temp & RH_A_OCPM) ? " OCPM" : "",
303 (temp & RH_A_DT) ? " DT" : "",
304 (temp & RH_A_NPS) ? " NPS" : "",
305 (temp & RH_A_PSM) ? " PSM" : "", ndp);
306 temp = roothub_b(controller);
307 dbg("roothub.b: %08x PPCM=%04x DR=%04x",
308 temp, (temp & RH_B_PPCM) >> 16, (temp & RH_B_DR)
309 );
310 temp = roothub_status(controller);
311 dbg("roothub.status: %08x%s%s%s%s%s%s",
312 temp,
313 (temp & RH_HS_CRWE) ? " CRWE" : "",
314 (temp & RH_HS_OCIC) ? " OCIC" : "",
315 (temp & RH_HS_LPSC) ? " LPSC" : "",
316 (temp & RH_HS_DRWE) ? " DRWE" : "",
317 (temp & RH_HS_OCI) ? " OCI" : "",
318 (temp & RH_HS_LPS) ? " LPS" : "");
wdenkde887eb2003-09-10 18:20:28 +0000319 }
320
321 for (i = 0; i < ndp; i++) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900322 temp = roothub_portstatus(controller, i);
323 dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
324 i,
325 temp,
326 (temp & RH_PS_PRSC) ? " PRSC" : "",
327 (temp & RH_PS_OCIC) ? " OCIC" : "",
328 (temp & RH_PS_PSSC) ? " PSSC" : "",
329 (temp & RH_PS_PESC) ? " PESC" : "",
330 (temp & RH_PS_CSC) ? " CSC" : "",
331 (temp & RH_PS_LSDA) ? " LSDA" : "",
332 (temp & RH_PS_PPS) ? " PPS" : "",
333 (temp & RH_PS_PRS) ? " PRS" : "",
334 (temp & RH_PS_POCI) ? " POCI" : "",
335 (temp & RH_PS_PSS) ? " PSS" : "",
336 (temp & RH_PS_PES) ? " PES" : "",
337 (temp & RH_PS_CCS) ? " CCS" : "");
wdenkde887eb2003-09-10 18:20:28 +0000338 }
339}
340
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900341static void ohci_dump(struct ohci *controller, int verbose)
wdenkde887eb2003-09-10 18:20:28 +0000342{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900343 dbg("OHCI controller usb-%s state", controller->slot_name);
wdenkde887eb2003-09-10 18:20:28 +0000344
345 /* dumps some of the state we know about */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900346 ohci_dump_status(controller);
wdenkde887eb2003-09-10 18:20:28 +0000347 if (verbose)
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900348 ep_print_int_eds(controller, "hcca");
349 dbg("hcca frame #%04x", controller->hcca->frame_no);
350 ohci_dump_roothub(controller, 1);
wdenkde887eb2003-09-10 18:20:28 +0000351}
352
wdenkde887eb2003-09-10 18:20:28 +0000353#endif /* DEBUG */
354
355/*-------------------------------------------------------------------------*
356 * Interface functions (URB)
357 *-------------------------------------------------------------------------*/
358
359/* get a transfer request */
360
361int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900362 int transfer_len, struct devrequest *setup, int interval)
wdenkde887eb2003-09-10 18:20:28 +0000363{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900364 struct ohci *ohci;
365 struct ed *ed;
366 struct urb_priv *purb_priv;
wdenkde887eb2003-09-10 18:20:28 +0000367 int i, size = 0;
368
369 ohci = &gohci;
370
371 /* when controller's hung, permit only roothub cleanup attempts
372 * such as powering down ports */
373 if (ohci->disabled) {
374 err("sohci_submit_job: EPIPE");
375 return -1;
376 }
377
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +0200378 /* if we have an unfinished URB from previous transaction let's
379 * fail and scream as quickly as possible so as not to corrupt
380 * further communication */
381 if (!urb_finished) {
382 err("sohci_submit_job: URB NOT FINISHED");
383 return -1;
384 }
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900385 /* we're about to begin a new transaction here
386 so mark the URB unfinished */
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +0200387 urb_finished = 0;
388
wdenkde887eb2003-09-10 18:20:28 +0000389 /* every endpoint has a ed, locate and fill it */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900390 ed = ep_add_ed(dev, pipe);
391 if (!ed) {
wdenkde887eb2003-09-10 18:20:28 +0000392 err("sohci_submit_job: ENOMEM");
393 return -1;
394 }
395
396 /* for the private part of the URB we need the number of TDs (size) */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900397 switch (usb_pipetype(pipe)) {
398 case PIPE_BULK:
399 /* one TD for every 4096 Byte */
400 size = (transfer_len - 1) / 4096 + 1;
401 break;
402 case PIPE_CONTROL:
403 /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
404 size = (transfer_len == 0) ? 2 : (transfer_len - 1) / 4096 + 3;
405 break;
wdenkde887eb2003-09-10 18:20:28 +0000406 }
407
408 if (size >= (N_URB_TD - 1)) {
409 err("need %d TDs, only have %d", size, N_URB_TD);
410 return -1;
411 }
412 purb_priv = &urb_priv;
413 purb_priv->pipe = pipe;
414
415 /* fill the private part of the URB */
416 purb_priv->length = size;
417 purb_priv->ed = ed;
418 purb_priv->actual_length = 0;
419
420 /* allocate the TDs */
421 /* note that td[0] was allocated in ep_add_ed */
422 for (i = 0; i < size; i++) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900423 purb_priv->td[i] = td_alloc(dev);
wdenkde887eb2003-09-10 18:20:28 +0000424 if (!purb_priv->td[i]) {
425 purb_priv->length = i;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900426 urb_free_priv(purb_priv);
wdenkde887eb2003-09-10 18:20:28 +0000427 err("sohci_submit_job: ENOMEM");
428 return -1;
429 }
430 }
431
432 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900433 urb_free_priv(purb_priv);
wdenkde887eb2003-09-10 18:20:28 +0000434 err("sohci_submit_job: EINVAL");
435 return -1;
436 }
437
438 /* link the ed into a chain if is not already */
439 if (ed->state != ED_OPER)
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900440 ep_link(ohci, ed);
wdenkde887eb2003-09-10 18:20:28 +0000441
442 /* fill the TDs and link it to the ed */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900443 td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv,
444 interval);
wdenkde887eb2003-09-10 18:20:28 +0000445
446 return 0;
447}
448
449/*-------------------------------------------------------------------------*/
450
451#ifdef DEBUG
452/* tell us the current USB frame number */
453
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900454static int sohci_get_current_frame_number(struct usb_device *usb_dev)
wdenkde887eb2003-09-10 18:20:28 +0000455{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900456 struct ohci *ohci = &gohci;
wdenkde887eb2003-09-10 18:20:28 +0000457
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900458 return m16_swap(ohci->hcca->frame_no);
wdenkde887eb2003-09-10 18:20:28 +0000459}
460#endif
461
462/*-------------------------------------------------------------------------*
463 * ED handling functions
464 *-------------------------------------------------------------------------*/
465
466/* link an ed into one of the HC chains */
467
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900468static int ep_link(struct ohci *ohci, struct ed *edi)
wdenkde887eb2003-09-10 18:20:28 +0000469{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900470 struct ed *ed = edi;
wdenkde887eb2003-09-10 18:20:28 +0000471
472 ed->state = ED_OPER;
473
474 switch (ed->type) {
475 case PIPE_CONTROL:
476 ed->hwNextED = 0;
477 if (ohci->ed_controltail == NULL) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900478 writel((u32)ed, &ohci->regs->ed_controlhead);
wdenkde887eb2003-09-10 18:20:28 +0000479 } else {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900480 ohci->ed_controltail->hwNextED = (__u32) m32_swap(ed);
wdenkde887eb2003-09-10 18:20:28 +0000481 }
482 ed->ed_prev = ohci->ed_controltail;
483 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900484 !ohci->ed_rm_list[1] && !ohci->sleeping) {
wdenkde887eb2003-09-10 18:20:28 +0000485 ohci->hc_control |= OHCI_CTRL_CLE;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900486 writel(ohci->hc_control, &ohci->regs->control);
wdenkde887eb2003-09-10 18:20:28 +0000487 }
488 ohci->ed_controltail = edi;
489 break;
490
491 case PIPE_BULK:
492 ed->hwNextED = 0;
493 if (ohci->ed_bulktail == NULL) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900494 writel((u32)ed, &ohci->regs->ed_bulkhead);
wdenkde887eb2003-09-10 18:20:28 +0000495 } else {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900496 ohci->ed_bulktail->hwNextED = (__u32) m32_swap(ed);
wdenkde887eb2003-09-10 18:20:28 +0000497 }
498 ed->ed_prev = ohci->ed_bulktail;
499 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900500 !ohci->ed_rm_list[1] && !ohci->sleeping) {
wdenkde887eb2003-09-10 18:20:28 +0000501 ohci->hc_control |= OHCI_CTRL_BLE;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900502 writel(ohci->hc_control, &ohci->regs->control);
wdenkde887eb2003-09-10 18:20:28 +0000503 }
504 ohci->ed_bulktail = edi;
505 break;
506 }
507 return 0;
508}
509
510/*-------------------------------------------------------------------------*/
511
512/* unlink an ed from one of the HC chains.
513 * just the link to the ed is unlinked.
514 * the link from the ed still points to another operational ed or 0
515 * so the HC can eventually finish the processing of the unlinked ed */
516
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900517static int ep_unlink(struct ohci *ohci, struct ed *ed)
wdenkde887eb2003-09-10 18:20:28 +0000518{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900519 struct ed *next;
520 ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
wdenkde887eb2003-09-10 18:20:28 +0000521
522 switch (ed->type) {
523 case PIPE_CONTROL:
524 if (ed->ed_prev == NULL) {
525 if (!ed->hwNextED) {
526 ohci->hc_control &= ~OHCI_CTRL_CLE;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900527 writel(ohci->hc_control, &ohci->regs->control);
wdenkde887eb2003-09-10 18:20:28 +0000528 }
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900529 writel(m32_swap(*((__u32 *) &ed->hwNextED)),
530 &ohci->regs->ed_controlhead);
wdenkde887eb2003-09-10 18:20:28 +0000531 } else {
532 ed->ed_prev->hwNextED = ed->hwNextED;
533 }
534 if (ohci->ed_controltail == ed) {
535 ohci->ed_controltail = ed->ed_prev;
536 } else {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900537 next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
538 next->ed_prev = ed->ed_prev;
wdenkde887eb2003-09-10 18:20:28 +0000539 }
540 break;
541
542 case PIPE_BULK:
543 if (ed->ed_prev == NULL) {
544 if (!ed->hwNextED) {
545 ohci->hc_control &= ~OHCI_CTRL_BLE;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900546 writel(ohci->hc_control, &ohci->regs->control);
wdenkde887eb2003-09-10 18:20:28 +0000547 }
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900548 writel(m32_swap(*((__u32 *) &ed->hwNextED)),
549 &ohci->regs->ed_bulkhead);
wdenkde887eb2003-09-10 18:20:28 +0000550 } else {
551 ed->ed_prev->hwNextED = ed->hwNextED;
552 }
553 if (ohci->ed_bulktail == ed) {
554 ohci->ed_bulktail = ed->ed_prev;
555 } else {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900556 next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
557 next->ed_prev = ed->ed_prev;
wdenkde887eb2003-09-10 18:20:28 +0000558 }
559 break;
560 }
561 ed->state = ED_UNLINK;
562 return 0;
563}
564
wdenkde887eb2003-09-10 18:20:28 +0000565/*-------------------------------------------------------------------------*/
566
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900567/* add/reinit an endpoint; this should be done once at the usb_set_configuration
568 * command, but the USB stack is a little bit stateless so we do it at every
569 * transaction. If the state of the ed is ED_NEW then a dummy td is added and
570 * the state is changed to ED_UNLINK. In all other cases the state is left
571 * unchanged. The ed info fields are setted anyway even though most of them
572 * should not change */
wdenkde887eb2003-09-10 18:20:28 +0000573
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900574static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe)
wdenkde887eb2003-09-10 18:20:28 +0000575{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900576 struct td *td;
577 struct ed *ed_ret;
578 struct ed *ed;
wdenkde887eb2003-09-10 18:20:28 +0000579
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900580 ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) |
581 (usb_pipecontrol(pipe) ? 0 :
582 usb_pipeout(pipe))];
wdenkde887eb2003-09-10 18:20:28 +0000583
584 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
585 err("ep_add_ed: pending delete");
586 /* pending delete request */
587 return NULL;
588 }
589
590 if (ed->state == ED_NEW) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900591 ed->hwINFO = m32_swap(OHCI_ED_SKIP); /* skip ed */
wdenk9c53f402003-10-15 23:53:47 +0000592 /* dummy td; end of td list for ed */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900593 td = td_alloc(usb_dev);
594 ed->hwTailP = (__u32) m32_swap(td);
wdenkde887eb2003-09-10 18:20:28 +0000595 ed->hwHeadP = ed->hwTailP;
596 ed->state = ED_UNLINK;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900597 ed->type = usb_pipetype(pipe);
wdenkde887eb2003-09-10 18:20:28 +0000598 ohci_dev.ed_cnt++;
599 }
600
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900601 ed->hwINFO = m32_swap(usb_pipedevice(pipe)
602 | usb_pipeendpoint(pipe) << 7
603 | (usb_pipeisoc(pipe) ? 0x8000 : 0)
604 | (usb_pipecontrol(pipe) ? 0 :
605 (usb_pipeout(pipe) ? 0x800 : 0x1000))
Ilya Yanoka1cf10f2012-11-06 13:48:20 +0000606 | (usb_dev->speed == USB_SPEED_LOW) << 13 |
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900607 usb_maxpacket(usb_dev, pipe) << 16);
wdenkde887eb2003-09-10 18:20:28 +0000608
609 return ed_ret;
610}
611
612/*-------------------------------------------------------------------------*
613 * TD handling functions
614 *-------------------------------------------------------------------------*/
615
616/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
617
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900618static void td_fill(struct ohci *ohci, unsigned int info, void *data, int len,
619 struct usb_device *dev, int index,
620 struct urb_priv *urb_priv)
wdenkde887eb2003-09-10 18:20:28 +0000621{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900622 struct td *td, *td_pt;
wdenkde887eb2003-09-10 18:20:28 +0000623#ifdef OHCI_FILL_TRACE
624 int i;
625#endif
626
627 if (index > urb_priv->length) {
628 err("index > length");
629 return;
630 }
631 /* use this td as the next dummy */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900632 td_pt = urb_priv->td[index];
wdenkde887eb2003-09-10 18:20:28 +0000633 td_pt->hwNextTD = 0;
634
635 /* fill the old dummy TD */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900636 td = urb_priv->td[index] =
637 (struct td *) (m32_swap(urb_priv->ed->hwTailP) & ~0xf);
wdenkde887eb2003-09-10 18:20:28 +0000638
639 td->ed = urb_priv->ed;
640 td->next_dl_td = NULL;
641 td->index = index;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900642 td->data = (__u32) data;
wdenkde887eb2003-09-10 18:20:28 +0000643#ifdef OHCI_FILL_TRACE
Remy Bohmerd8c55ab2008-10-10 10:23:22 +0200644 if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
wdenkde887eb2003-09-10 18:20:28 +0000645 for (i = 0; i < len; i++)
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900646 printf("td->data[%d] %#2x ", i,
647 ((unsigned char *)td->data)[i]);
wdenkde887eb2003-09-10 18:20:28 +0000648 printf("\n");
649 }
650#endif
651 if (!len)
652 data = 0;
653
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900654 td->hwINFO = (__u32) m32_swap(info);
655 td->hwCBP = (__u32) m32_swap(data);
wdenkde887eb2003-09-10 18:20:28 +0000656 if (data)
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900657 td->hwBE = (__u32) m32_swap(data + len - 1);
wdenkde887eb2003-09-10 18:20:28 +0000658 else
659 td->hwBE = 0;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900660 td->hwNextTD = (__u32) m32_swap(td_pt);
wdenkde887eb2003-09-10 18:20:28 +0000661
662 /* append to queue */
663 td->ed->hwTailP = td->hwNextTD;
664}
665
666/*-------------------------------------------------------------------------*/
667
668/* prepare all TDs of a transfer */
669
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900670static void td_submit_job(struct usb_device *dev, unsigned long pipe,
671 void *buffer, int transfer_len,
672 struct devrequest *setup, struct urb_priv *urb,
673 int interval)
wdenkde887eb2003-09-10 18:20:28 +0000674{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900675 struct ohci *ohci = &gohci;
wdenkde887eb2003-09-10 18:20:28 +0000676 int data_len = transfer_len;
677 void *data;
678 int cnt = 0;
679 __u32 info = 0;
wdenk9c53f402003-10-15 23:53:47 +0000680 unsigned int toggle = 0;
wdenkde887eb2003-09-10 18:20:28 +0000681
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900682 /* OHCI handles the DATA-toggles itself, we just
683 use the USB-toggle bits for reseting */
684 if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
wdenk9c53f402003-10-15 23:53:47 +0000685 toggle = TD_T_TOGGLE;
wdenkde887eb2003-09-10 18:20:28 +0000686 } else {
wdenk9c53f402003-10-15 23:53:47 +0000687 toggle = TD_T_DATA0;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900688 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe),
689 1);
wdenkde887eb2003-09-10 18:20:28 +0000690 }
691 urb->td_cnt = 0;
692 if (data_len)
693 data = buffer;
694 else
695 data = 0;
696
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900697 switch (usb_pipetype(pipe)) {
wdenkde887eb2003-09-10 18:20:28 +0000698 case PIPE_BULK:
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900699 info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN;
700 while (data_len > 4096) {
701 td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
702 4096, dev, cnt, urb);
703 data += 4096;
704 data_len -= 4096;
705 cnt++;
wdenkde887eb2003-09-10 18:20:28 +0000706 }
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900707 info = usb_pipeout(pipe) ?
708 TD_CC | TD_DP_OUT :
709 TD_CC | TD_R | TD_DP_IN;
710 td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
711 data_len, dev, cnt, urb);
wdenkde887eb2003-09-10 18:20:28 +0000712 cnt++;
713
714 if (!ohci->sleeping)
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900715 /* start bulk list */
716 writel(OHCI_BLF, &ohci->regs->cmdstatus);
wdenkde887eb2003-09-10 18:20:28 +0000717 break;
718
719 case PIPE_CONTROL:
720 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900721 td_fill(ohci, info, setup, 8, dev, cnt++, urb);
wdenkde887eb2003-09-10 18:20:28 +0000722 if (data_len > 0) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900723 info = usb_pipeout(pipe) ?
724 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 :
725 TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
wdenkde887eb2003-09-10 18:20:28 +0000726 /* NOTE: mishandles transfers >8K, some >4K */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900727 td_fill(ohci, info, data, data_len, dev, cnt++, urb);
wdenkde887eb2003-09-10 18:20:28 +0000728 }
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900729 info = usb_pipeout(pipe) ?
730 TD_CC | TD_DP_IN | TD_T_DATA1 :
731 TD_CC | TD_DP_OUT | TD_T_DATA1;
732 td_fill(ohci, info, data, 0, dev, cnt++, urb);
wdenkde887eb2003-09-10 18:20:28 +0000733 if (!ohci->sleeping)
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900734 /* start Control list */
735 writel(OHCI_CLF, &ohci->regs->cmdstatus);
wdenkde887eb2003-09-10 18:20:28 +0000736 break;
737 }
738 if (urb->length != cnt)
739 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
740}
741
742/*-------------------------------------------------------------------------*
743 * Done List handling functions
744 *-------------------------------------------------------------------------*/
745
746
747/* calculate the transfer length and update the urb */
748
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900749static void dl_transfer_length(struct td *td)
wdenkde887eb2003-09-10 18:20:28 +0000750{
Wolfgang Denka0ebb902011-10-06 09:22:52 +0200751 __u32 tdBE, tdCBP;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900752 struct urb_priv *lurb_priv = &urb_priv;
wdenkde887eb2003-09-10 18:20:28 +0000753
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900754 tdBE = m32_swap(td->hwBE);
755 tdCBP = m32_swap(td->hwCBP);
wdenkde887eb2003-09-10 18:20:28 +0000756
Remy Bohmerd8c55ab2008-10-10 10:23:22 +0200757 if (!(usb_pipecontrol(lurb_priv->pipe) &&
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900758 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
wdenkde887eb2003-09-10 18:20:28 +0000759 if (tdBE != 0) {
760 if (td->hwCBP == 0)
761 lurb_priv->actual_length += tdBE - td->data + 1;
762 else
763 lurb_priv->actual_length += tdCBP - td->data;
764 }
765 }
766}
767
768/*-------------------------------------------------------------------------*/
769
770/* replies to the request have to be on a FIFO basis so
771 * we reverse the reversed done-list */
772
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900773static struct td *dl_reverse_done_list(struct ohci *ohci)
wdenkde887eb2003-09-10 18:20:28 +0000774{
775 __u32 td_list_hc;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900776 __u32 tmp;
777 struct td *td_rev = NULL;
778 struct td *td_list = NULL;
779 struct urb_priv *lurb_priv = NULL;
wdenkde887eb2003-09-10 18:20:28 +0000780
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900781 td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0;
wdenkde887eb2003-09-10 18:20:28 +0000782 ohci->hcca->done_head = 0;
783
784 while (td_list_hc) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900785 td_list = (struct td *) td_list_hc;
wdenkde887eb2003-09-10 18:20:28 +0000786
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900787 if (TD_CC_GET(m32_swap(td_list->hwINFO))) {
wdenkde887eb2003-09-10 18:20:28 +0000788 lurb_priv = &urb_priv;
789 dbg(" USB-error/status: %x : %p",
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900790 TD_CC_GET(m32_swap(td_list->hwINFO)), td_list);
791 if (td_list->ed->hwHeadP & m32_swap(0x1)) {
792 if (lurb_priv &&
793 ((td_list->index+1) < lurb_priv->length)) {
794 tmp = lurb_priv->length - 1;
wdenkde887eb2003-09-10 18:20:28 +0000795 td_list->ed->hwHeadP =
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900796 (lurb_priv->td[tmp]->hwNextTD &
797 m32_swap(0xfffffff0)) |
798 (td_list->ed->hwHeadP &
799 m32_swap(0x2));
800 lurb_priv->td_cnt += lurb_priv->length -
801 td_list->index - 1;
wdenkde887eb2003-09-10 18:20:28 +0000802 } else
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900803 td_list->ed->hwHeadP &=
804 m32_swap(0xfffffff2);
wdenkde887eb2003-09-10 18:20:28 +0000805 }
806 }
807
808 td_list->next_dl_td = td_rev;
809 td_rev = td_list;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900810 td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
wdenkde887eb2003-09-10 18:20:28 +0000811 }
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +0200812
wdenkde887eb2003-09-10 18:20:28 +0000813 return td_list;
814}
815
816/*-------------------------------------------------------------------------*/
817
818/* td done list */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900819static int dl_done_list(struct ohci *ohci, struct td *td_list)
wdenkde887eb2003-09-10 18:20:28 +0000820{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900821 struct td *td_list_next = NULL;
822 struct ed *ed;
wdenkde887eb2003-09-10 18:20:28 +0000823 int cc = 0;
824 int stat = 0;
825 /* urb_t *urb; */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900826 struct urb_priv *lurb_priv;
wdenk9c53f402003-10-15 23:53:47 +0000827 __u32 tdINFO, edHeadP, edTailP;
wdenkde887eb2003-09-10 18:20:28 +0000828
wdenk9c53f402003-10-15 23:53:47 +0000829 while (td_list) {
830 td_list_next = td_list->next_dl_td;
wdenkde887eb2003-09-10 18:20:28 +0000831
wdenk9c53f402003-10-15 23:53:47 +0000832 lurb_priv = &urb_priv;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900833 tdINFO = m32_swap(td_list->hwINFO);
wdenkde887eb2003-09-10 18:20:28 +0000834
wdenk9c53f402003-10-15 23:53:47 +0000835 ed = td_list->ed;
wdenkde887eb2003-09-10 18:20:28 +0000836
wdenk9c53f402003-10-15 23:53:47 +0000837 dl_transfer_length(td_list);
wdenkde887eb2003-09-10 18:20:28 +0000838
wdenk9c53f402003-10-15 23:53:47 +0000839 /* error code of transfer */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900840 cc = TD_CC_GET(tdINFO);
wdenkde887eb2003-09-10 18:20:28 +0000841 if (cc != 0) {
842 dbg("ConditionCode %#x", cc);
843 stat = cc_to_error[cc];
844 }
845
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +0200846 /* see if this done list makes for all TD's of current URB,
847 * and mark the URB finished if so */
848 if (++(lurb_priv->td_cnt) == lurb_priv->length) {
849 if ((ed->state & (ED_OPER | ED_UNLINK)))
850 urb_finished = 1;
851 else
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900852 dbg("dl_done_list: strange.., ED state %x, "
853 "ed->state\n");
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +0200854 } else
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900855 dbg("dl_done_list: processing TD %x, len %x\n",
856 lurb_priv->td_cnt, lurb_priv->length);
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +0200857
wdenk9c53f402003-10-15 23:53:47 +0000858 if (ed->state != ED_NEW) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900859 edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
860 edTailP = m32_swap(ed->hwTailP);
wdenkde887eb2003-09-10 18:20:28 +0000861
862 /* unlink eds if they are not busy */
wdenk9c53f402003-10-15 23:53:47 +0000863 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900864 ep_unlink(ohci, ed);
wdenk9c53f402003-10-15 23:53:47 +0000865 }
wdenkde887eb2003-09-10 18:20:28 +0000866
wdenk9c53f402003-10-15 23:53:47 +0000867 td_list = td_list_next;
868 }
wdenkde887eb2003-09-10 18:20:28 +0000869 return stat;
870}
871
872/*-------------------------------------------------------------------------*
873 * Virtual Root Hub
874 *-------------------------------------------------------------------------*/
875
876/* Device descriptor */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900877static __u8 root_hub_dev_des[] = {
878 0x12, /* __u8 bLength; */
879 0x01, /* __u8 bDescriptorType; Device */
880 0x10, /* __u16 bcdUSB; v1.1 */
wdenkde887eb2003-09-10 18:20:28 +0000881 0x01,
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900882 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
883 0x00, /* __u8 bDeviceSubClass; */
884 0x00, /* __u8 bDeviceProtocol; */
885 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
886 0x00, /* __u16 idVendor; */
wdenkde887eb2003-09-10 18:20:28 +0000887 0x00,
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900888 0x00, /* __u16 idProduct; */
wdenk9c53f402003-10-15 23:53:47 +0000889 0x00,
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900890 0x00, /* __u16 bcdDevice; */
wdenk9c53f402003-10-15 23:53:47 +0000891 0x00,
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900892 0x00, /* __u8 iManufacturer; */
893 0x01, /* __u8 iProduct; */
894 0x00, /* __u8 iSerialNumber; */
895 0x01 /* __u8 bNumConfigurations; */
wdenkde887eb2003-09-10 18:20:28 +0000896};
897
wdenkde887eb2003-09-10 18:20:28 +0000898/* Configuration descriptor */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900899static __u8 root_hub_config_des[] = {
900 0x09, /* __u8 bLength; */
901 0x02, /* __u8 bDescriptorType; Configuration */
902 0x19, /* __u16 wTotalLength; */
wdenkde887eb2003-09-10 18:20:28 +0000903 0x00,
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900904 0x01, /* __u8 bNumInterfaces; */
905 0x01, /* __u8 bConfigurationValue; */
906 0x00, /* __u8 iConfiguration; */
907 0x40, /* __u8 bmAttributes;
908 Bit 7: Bus-powered, 6: Self-powered,
909 5 Remote-wakwup, 4..0: resvd */
910 0x00, /* __u8 MaxPower; */
wdenkde887eb2003-09-10 18:20:28 +0000911
912 /* interface */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900913 0x09, /* __u8 if_bLength; */
914 0x04, /* __u8 if_bDescriptorType; Interface */
915 0x00, /* __u8 if_bInterfaceNumber; */
916 0x00, /* __u8 if_bAlternateSetting; */
917 0x01, /* __u8 if_bNumEndpoints; */
918 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
919 0x00, /* __u8 if_bInterfaceSubClass; */
920 0x00, /* __u8 if_bInterfaceProtocol; */
921 0x00, /* __u8 if_iInterface; */
wdenkde887eb2003-09-10 18:20:28 +0000922
923 /* endpoint */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900924 0x07, /* __u8 ep_bLength; */
925 0x05, /* __u8 ep_bDescriptorType; Endpoint */
926 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
927 0x03, /* __u8 ep_bmAttributes; Interrupt */
928 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
wdenk9c53f402003-10-15 23:53:47 +0000929 0x00,
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900930 0xff /* __u8 ep_bInterval; 255 ms */
wdenkde887eb2003-09-10 18:20:28 +0000931};
932
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900933static unsigned char root_hub_str_index0[] = {
934 0x04, /* __u8 bLength; */
935 0x03, /* __u8 bDescriptorType; String-descriptor */
936 0x09, /* __u8 lang ID */
937 0x04, /* __u8 lang ID */
wdenkde887eb2003-09-10 18:20:28 +0000938};
939
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900940static unsigned char root_hub_str_index1[] = {
941 28, /* __u8 bLength; */
942 0x03, /* __u8 bDescriptorType; String-descriptor */
943 'O', /* __u8 Unicode */
944 0, /* __u8 Unicode */
945 'H', /* __u8 Unicode */
946 0, /* __u8 Unicode */
947 'C', /* __u8 Unicode */
948 0, /* __u8 Unicode */
949 'I', /* __u8 Unicode */
950 0, /* __u8 Unicode */
951 ' ', /* __u8 Unicode */
952 0, /* __u8 Unicode */
953 'R', /* __u8 Unicode */
954 0, /* __u8 Unicode */
955 'o', /* __u8 Unicode */
956 0, /* __u8 Unicode */
957 'o', /* __u8 Unicode */
958 0, /* __u8 Unicode */
959 't', /* __u8 Unicode */
960 0, /* __u8 Unicode */
961 ' ', /* __u8 Unicode */
962 0, /* __u8 Unicode */
963 'H', /* __u8 Unicode */
964 0, /* __u8 Unicode */
965 'u', /* __u8 Unicode */
966 0, /* __u8 Unicode */
967 'b', /* __u8 Unicode */
968 0, /* __u8 Unicode */
wdenkde887eb2003-09-10 18:20:28 +0000969};
970
971/* Hub class-specific descriptor is constructed dynamically */
972
973
974/*-------------------------------------------------------------------------*/
975
Wolfgang Denka1be4762008-05-20 16:00:29 +0200976#define OK(x) len = (x); break
wdenkde887eb2003-09-10 18:20:28 +0000977#ifdef DEBUG
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900978#define WR_RH_STAT(x) \
979{ \
980 info("WR:status %#8x", (x)); \
981 writel((x), &gohci.regs->roothub.status); \
982}
983#define WR_RH_PORTSTAT(x) \
984{ \
985 info("WR:portstatus[%d] %#8x", wIndex-1, (x)); \
986 writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); \
987}
wdenkde887eb2003-09-10 18:20:28 +0000988#else
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900989#define WR_RH_STAT(x) \
990 writel((x), &gohci.regs->roothub.status)
991#define WR_RH_PORTSTAT(x)\
992 writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
wdenkde887eb2003-09-10 18:20:28 +0000993#endif
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900994#define RD_RH_STAT roothub_status(&gohci)
995#define RD_RH_PORTSTAT roothub_portstatus(&gohci, wIndex-1)
wdenkde887eb2003-09-10 18:20:28 +0000996
997/* request to virtual root hub */
998
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900999int rh_check_port_status(struct ohci *controller)
dzu8d7e4d12003-09-29 21:55:54 +00001000{
1001 __u32 temp, ndp, i;
1002 int res;
1003
1004 res = -1;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001005 temp = roothub_a(controller);
dzu8d7e4d12003-09-29 21:55:54 +00001006 ndp = (temp & RH_A_NDP);
1007 for (i = 0; i < ndp; i++) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001008 temp = roothub_portstatus(controller, i);
dzu8d7e4d12003-09-29 21:55:54 +00001009 /* check for a device disconnect */
1010 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001011 (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) {
dzu8d7e4d12003-09-29 21:55:54 +00001012 res = i;
1013 break;
1014 }
1015 }
1016 return res;
1017}
1018
1019static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001020 void *buffer, int transfer_len,
1021 struct devrequest *cmd)
wdenkde887eb2003-09-10 18:20:28 +00001022{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001023 void *data = buffer;
wdenkde887eb2003-09-10 18:20:28 +00001024 int leni = transfer_len;
1025 int len = 0;
1026 int stat = 0;
Simon Glass28cace12011-11-15 18:17:06 +00001027 union {
1028 __u32 word[4];
1029 __u16 hword[8];
1030 __u8 byte[16];
1031 } datab;
1032 __u8 *data_buf = datab.byte;
wdenk9c53f402003-10-15 23:53:47 +00001033 __u16 bmRType_bReq;
wdenkde887eb2003-09-10 18:20:28 +00001034 __u16 wValue;
1035 __u16 wIndex;
1036 __u16 wLength;
1037
1038#ifdef DEBUG
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001039 urb_priv.actual_length = 0;
1040 pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)",
1041 usb_pipein(pipe));
wdenkde887eb2003-09-10 18:20:28 +00001042#else
Mike Frysinger60ce19a2012-03-05 13:47:00 +00001043 mdelay(1);
wdenkde887eb2003-09-10 18:20:28 +00001044#endif
Remy Bohmerd8c55ab2008-10-10 10:23:22 +02001045 if (usb_pipeint(pipe)) {
wdenkde887eb2003-09-10 18:20:28 +00001046 info("Root-Hub submit IRQ: NOT implemented");
1047 return 0;
1048 }
1049
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001050 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
1051 wValue = m16_swap(cmd->value);
1052 wIndex = m16_swap(cmd->index);
1053 wLength = m16_swap(cmd->length);
wdenkde887eb2003-09-10 18:20:28 +00001054
1055 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001056 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
wdenkde887eb2003-09-10 18:20:28 +00001057
1058 switch (bmRType_bReq) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001059 /* Request Destination:
1060 without flags: Device,
1061 RH_INTERFACE: interface,
1062 RH_ENDPOINT: endpoint,
1063 RH_CLASS means HUB here,
1064 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
1065 */
wdenkde887eb2003-09-10 18:20:28 +00001066
1067 case RH_GET_STATUS:
Simon Glass28cace12011-11-15 18:17:06 +00001068 datab.hword[0] = m16_swap(1);
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001069 OK(2);
wdenkde887eb2003-09-10 18:20:28 +00001070 case RH_GET_STATUS | RH_INTERFACE:
Simon Glass28cace12011-11-15 18:17:06 +00001071 datab.hword[0] = m16_swap(0);
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001072 OK(2);
wdenkde887eb2003-09-10 18:20:28 +00001073 case RH_GET_STATUS | RH_ENDPOINT:
Simon Glass28cace12011-11-15 18:17:06 +00001074 datab.hword[0] = m16_swap(0);
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001075 OK(2);
wdenkde887eb2003-09-10 18:20:28 +00001076 case RH_GET_STATUS | RH_CLASS:
Simon Glass28cace12011-11-15 18:17:06 +00001077 datab.word[0] =
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001078 m32_swap(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
1079 OK(4);
wdenkde887eb2003-09-10 18:20:28 +00001080 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
Simon Glass28cace12011-11-15 18:17:06 +00001081 datab.word[0] = m32_swap(RD_RH_PORTSTAT);
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001082 OK(4);
wdenkde887eb2003-09-10 18:20:28 +00001083
1084 case RH_CLEAR_FEATURE | RH_ENDPOINT:
1085 switch (wValue) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001086 case (RH_ENDPOINT_STALL):
1087 OK(0);
wdenkde887eb2003-09-10 18:20:28 +00001088 }
1089 break;
1090
1091 case RH_CLEAR_FEATURE | RH_CLASS:
1092 switch (wValue) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001093 case RH_C_HUB_LOCAL_POWER:
1094 OK(0);
1095 case (RH_C_HUB_OVER_CURRENT):
1096 WR_RH_STAT(RH_HS_OCIC);
1097 OK(0);
wdenkde887eb2003-09-10 18:20:28 +00001098 }
1099 break;
1100
1101 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
1102 switch (wValue) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001103 case (RH_PORT_ENABLE):
1104 WR_RH_PORTSTAT(RH_PS_CCS);
1105 OK(0);
1106 case (RH_PORT_SUSPEND):
1107 WR_RH_PORTSTAT(RH_PS_POCI);
1108 OK(0);
1109 case (RH_PORT_POWER):
1110 WR_RH_PORTSTAT(RH_PS_LSDA);
1111 OK(0);
1112 case (RH_C_PORT_CONNECTION):
1113 WR_RH_PORTSTAT(RH_PS_CSC);
1114 OK(0);
1115 case (RH_C_PORT_ENABLE):
1116 WR_RH_PORTSTAT(RH_PS_PESC);
1117 OK(0);
1118 case (RH_C_PORT_SUSPEND):
1119 WR_RH_PORTSTAT(RH_PS_PSSC);
1120 OK(0);
1121 case (RH_C_PORT_OVER_CURRENT):
1122 WR_RH_PORTSTAT(RH_PS_OCIC);
1123 OK(0);
1124 case (RH_C_PORT_RESET):
1125 WR_RH_PORTSTAT(RH_PS_PRSC);
1126 OK(0);
wdenkde887eb2003-09-10 18:20:28 +00001127 }
1128 break;
1129
1130 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
1131 switch (wValue) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001132 case (RH_PORT_SUSPEND):
1133 WR_RH_PORTSTAT(RH_PS_PSS);
1134 OK(0);
1135 case (RH_PORT_RESET): /* BUG IN HUP CODE ******** */
1136 if (RD_RH_PORTSTAT & RH_PS_CCS)
1137 WR_RH_PORTSTAT(RH_PS_PRS);
1138 OK(0);
1139 case (RH_PORT_POWER):
1140 WR_RH_PORTSTAT(RH_PS_PPS);
1141 OK(0);
1142 case (RH_PORT_ENABLE): /* BUG IN HUP CODE ******** */
1143 if (RD_RH_PORTSTAT & RH_PS_CCS)
1144 WR_RH_PORTSTAT(RH_PS_PES);
1145 OK(0);
wdenkde887eb2003-09-10 18:20:28 +00001146 }
1147 break;
1148
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001149 case RH_SET_ADDRESS:
1150 gohci.rh.devnum = wValue;
1151 OK(0);
wdenkde887eb2003-09-10 18:20:28 +00001152
1153 case RH_GET_DESCRIPTOR:
1154 switch ((wValue & 0xff00) >> 8) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001155 case (0x01): /* device descriptor */
1156 len = min_t(unsigned int,
1157 leni,
1158 min_t(unsigned int,
1159 sizeof(root_hub_dev_des), wLength));
1160 data_buf = root_hub_dev_des;
1161 OK(len);
1162 case (0x02): /* configuration descriptor */
1163 len = min_t(unsigned int,
1164 leni,
1165 min_t(unsigned int,
1166 sizeof(root_hub_config_des),
1167 wLength));
1168 data_buf = root_hub_config_des;
1169 OK(len);
1170 case (0x03): /* string descriptors */
1171 if (wValue == 0x0300) {
wdenkde887eb2003-09-10 18:20:28 +00001172 len = min_t(unsigned int,
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001173 leni,
1174 min_t(unsigned int,
1175 sizeof(root_hub_str_index0),
1176 wLength));
1177 data_buf = root_hub_str_index0;
1178 OK(len);
1179 }
1180 if (wValue == 0x0301) {
wdenkde887eb2003-09-10 18:20:28 +00001181 len = min_t(unsigned int,
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001182 leni,
1183 min_t(unsigned int,
1184 sizeof(root_hub_str_index1),
1185 wLength));
1186 data_buf = root_hub_str_index1;
1187 OK(len);
wdenkde887eb2003-09-10 18:20:28 +00001188 }
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001189 default:
1190 stat = USB_ST_STALLED;
wdenkde887eb2003-09-10 18:20:28 +00001191 }
1192 break;
1193
1194 case RH_GET_DESCRIPTOR | RH_CLASS:
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001195 {
1196 __u32 temp = roothub_a(&gohci);
wdenkde887eb2003-09-10 18:20:28 +00001197
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001198 data_buf[0] = 9; /* min length; */
1199 data_buf[1] = 0x29;
1200 data_buf[2] = temp & RH_A_NDP;
1201 data_buf[3] = 0;
1202 if (temp & RH_A_PSM)
1203 /* per-port power switching? */
1204 data_buf[3] |= 0x1;
1205 if (temp & RH_A_NOCP)
1206 /* no overcurrent reporting? */
1207 data_buf[3] |= 0x10;
1208 else if (temp & RH_A_OCPM)
1209 /* per-port overcurrent reporting? */
1210 data_buf[3] |= 0x8;
wdenkde887eb2003-09-10 18:20:28 +00001211
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001212 /* corresponds to data_buf[4-7] */
Simon Glass28cace12011-11-15 18:17:06 +00001213 datab.word[1] = 0;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001214 data_buf[5] = (temp & RH_A_POTPGT) >> 24;
1215 temp = roothub_b(&gohci);
1216 data_buf[7] = temp & RH_B_DR;
1217 if (data_buf[2] < 7) {
1218 data_buf[8] = 0xff;
1219 } else {
1220 data_buf[0] += 2;
1221 data_buf[8] = (temp & RH_B_DR) >> 8;
1222 data_buf[10] = data_buf[9] = 0xff;
1223 }
wdenkde887eb2003-09-10 18:20:28 +00001224
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001225 len = min_t(unsigned int, leni,
1226 min_t(unsigned int, data_buf[0], wLength));
1227 OK(len);
wdenkde887eb2003-09-10 18:20:28 +00001228 }
1229
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001230 case RH_GET_CONFIGURATION:
1231 *(__u8 *) data_buf = 0x01;
1232 OK(1);
wdenkde887eb2003-09-10 18:20:28 +00001233
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001234 case RH_SET_CONFIGURATION:
1235 WR_RH_STAT(0x10000);
1236 OK(0);
wdenkde887eb2003-09-10 18:20:28 +00001237
1238 default:
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001239 dbg("unsupported root hub command");
wdenkde887eb2003-09-10 18:20:28 +00001240 stat = USB_ST_STALLED;
1241 }
1242
1243#ifdef DEBUG
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001244 ohci_dump_roothub(&gohci, 1);
wdenkde887eb2003-09-10 18:20:28 +00001245#else
Mike Frysinger60ce19a2012-03-05 13:47:00 +00001246 mdelay(1);
wdenkde887eb2003-09-10 18:20:28 +00001247#endif
1248
1249 len = min_t(int, len, leni);
1250 if (data != data_buf)
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001251 memcpy(data, data_buf, len);
wdenk9c53f402003-10-15 23:53:47 +00001252 dev->act_len = len;
wdenkde887eb2003-09-10 18:20:28 +00001253 dev->status = stat;
1254
1255#ifdef DEBUG
1256 if (transfer_len)
1257 urb_priv.actual_length = transfer_len;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001258 pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)",
1259 0 /*usb_pipein(pipe) */);
wdenkde887eb2003-09-10 18:20:28 +00001260#else
Mike Frysinger60ce19a2012-03-05 13:47:00 +00001261 mdelay(1);
wdenkde887eb2003-09-10 18:20:28 +00001262#endif
1263
1264 return stat;
1265}
1266
1267/*-------------------------------------------------------------------------*/
1268
1269/* common code for handling submit messages - used for all but root hub */
1270/* accesses. */
1271int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001272 int transfer_len, struct devrequest *setup, int interval)
wdenkde887eb2003-09-10 18:20:28 +00001273{
1274 int stat = 0;
1275 int maxsize = usb_maxpacket(dev, pipe);
1276 int timeout;
1277
dzu8d7e4d12003-09-29 21:55:54 +00001278 /* device pulled? Shortcut the action. */
1279 if (devgone == dev) {
1280 dev->status = USB_ST_CRC_ERR;
1281 return 0;
1282 }
wdenkde887eb2003-09-10 18:20:28 +00001283#ifdef DEBUG
1284 urb_priv.actual_length = 0;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001285 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
1286 usb_pipein(pipe));
wdenkde887eb2003-09-10 18:20:28 +00001287#else
Mike Frysinger60ce19a2012-03-05 13:47:00 +00001288 mdelay(1);
wdenkde887eb2003-09-10 18:20:28 +00001289#endif
1290 if (!maxsize) {
1291 err("submit_common_message: pipesize for pipe %lx is zero",
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001292 pipe);
wdenkde887eb2003-09-10 18:20:28 +00001293 return -1;
1294 }
1295
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001296 if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) <
1297 0) {
wdenkde887eb2003-09-10 18:20:28 +00001298 err("sohci_submit_job failed");
1299 return -1;
1300 }
1301
Mike Frysinger60ce19a2012-03-05 13:47:00 +00001302 mdelay(10);
wdenkde887eb2003-09-10 18:20:28 +00001303 /* ohci_dump_status(&gohci); */
wdenk9c53f402003-10-15 23:53:47 +00001304
wdenk934c4f82003-09-11 19:48:06 +00001305 /* allow more time for a BULK device to react - some are slow */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001306#define BULK_TO 5000 /* timeout in milliseconds */
Remy Bohmerd8c55ab2008-10-10 10:23:22 +02001307 if (usb_pipebulk(pipe))
wdenk934c4f82003-09-11 19:48:06 +00001308 timeout = BULK_TO;
1309 else
1310 timeout = 100;
1311
wdenkde887eb2003-09-10 18:20:28 +00001312 /* wait for it to complete */
wdenkde887eb2003-09-10 18:20:28 +00001313 for (;;) {
1314 /* check whether the controller is done */
1315 stat = hc_interrupt();
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001316
wdenkde887eb2003-09-10 18:20:28 +00001317 if (stat < 0) {
dzu8d7e4d12003-09-29 21:55:54 +00001318 stat = USB_ST_CRC_ERR;
wdenkde887eb2003-09-10 18:20:28 +00001319 break;
1320 }
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001321
1322 /* NOTE: since we are not interrupt driven in U-Boot and always
1323 * handle only one URB at a time, we cannot assume the
1324 * transaction finished on the first successful return from
1325 * hc_interrupt().. unless the flag for current URB is set,
1326 * meaning that all TD's to/from device got actually
1327 * transferred and processed. If the current URB is not
1328 * finished we need to re-iterate this loop so as
1329 * hc_interrupt() gets called again as there needs to be some
1330 * more TD's to process still */
1331 if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
wdenkde887eb2003-09-10 18:20:28 +00001332 /* 0xff is returned for an SF-interrupt */
1333 break;
1334 }
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001335
wdenkde887eb2003-09-10 18:20:28 +00001336 if (--timeout) {
Mike Frysinger60ce19a2012-03-05 13:47:00 +00001337 mdelay(1);
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001338 if (!urb_finished)
1339 dbg("\%");
Wolfgang Denkd06ce5d2005-08-02 17:06:17 +02001340
wdenkde887eb2003-09-10 18:20:28 +00001341 } else {
dzu8d7e4d12003-09-29 21:55:54 +00001342 err("CTL:TIMEOUT ");
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001343 dbg("submit_common_msg: TO status %x\n", stat);
dzu8d7e4d12003-09-29 21:55:54 +00001344 stat = USB_ST_CRC_ERR;
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001345 urb_finished = 1;
wdenkde887eb2003-09-10 18:20:28 +00001346 break;
1347 }
1348 }
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001349
1350#if 0
dzu8d7e4d12003-09-29 21:55:54 +00001351 /* we got an Root Hub Status Change interrupt */
1352 if (got_rhsc) {
1353#ifdef DEBUG
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001354 ohci_dump_roothub(&gohci, 1);
dzu8d7e4d12003-09-29 21:55:54 +00001355#endif
1356 got_rhsc = 0;
1357 /* abuse timeout */
1358 timeout = rh_check_port_status(&gohci);
1359 if (timeout >= 0) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001360#if 0 /* this does nothing useful, but leave it here
1361 in case that changes */
dzu8d7e4d12003-09-29 21:55:54 +00001362 /* the called routine adds 1 to the passed value */
1363 usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
1364#endif
1365 /*
1366 * XXX
1367 * This is potentially dangerous because it assumes
1368 * that only one device is ever plugged in!
1369 */
1370 devgone = dev;
1371 }
1372 }
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001373#endif
dzu8d7e4d12003-09-29 21:55:54 +00001374
wdenkde887eb2003-09-10 18:20:28 +00001375 dev->status = stat;
wdenk9c53f402003-10-15 23:53:47 +00001376 dev->act_len = transfer_len;
wdenkde887eb2003-09-10 18:20:28 +00001377
1378#ifdef DEBUG
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001379 pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)",
1380 usb_pipein(pipe));
wdenkde887eb2003-09-10 18:20:28 +00001381#else
Mike Frysinger60ce19a2012-03-05 13:47:00 +00001382 mdelay(1);
wdenkde887eb2003-09-10 18:20:28 +00001383#endif
1384
1385 /* free TDs in urb_priv */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001386 urb_free_priv(&urb_priv);
wdenkde887eb2003-09-10 18:20:28 +00001387 return 0;
1388}
1389
1390/* submit routines called from usb.c */
1391int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001392 int transfer_len)
wdenkde887eb2003-09-10 18:20:28 +00001393{
1394 info("submit_bulk_msg");
1395 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1396}
1397
1398int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001399 int transfer_len, struct devrequest *setup)
wdenkde887eb2003-09-10 18:20:28 +00001400{
1401 int maxsize = usb_maxpacket(dev, pipe);
1402
1403 info("submit_control_msg");
1404#ifdef DEBUG
1405 urb_priv.actual_length = 0;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001406 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
1407 usb_pipein(pipe));
wdenkde887eb2003-09-10 18:20:28 +00001408#else
Mike Frysinger60ce19a2012-03-05 13:47:00 +00001409 mdelay(1);
wdenkde887eb2003-09-10 18:20:28 +00001410#endif
1411 if (!maxsize) {
1412 err("submit_control_message: pipesize for pipe %lx is zero",
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001413 pipe);
wdenkde887eb2003-09-10 18:20:28 +00001414 return -1;
1415 }
dzu8d7e4d12003-09-29 21:55:54 +00001416 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1417 gohci.rh.dev = dev;
wdenkde887eb2003-09-10 18:20:28 +00001418 /* root hub - redirect */
1419 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001420 setup);
dzu8d7e4d12003-09-29 21:55:54 +00001421 }
wdenkde887eb2003-09-10 18:20:28 +00001422
1423 return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1424}
1425
1426int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001427 int transfer_len, int interval)
wdenkde887eb2003-09-10 18:20:28 +00001428{
1429 info("submit_int_msg");
1430 return -1;
1431}
1432
1433/*-------------------------------------------------------------------------*
1434 * HC functions
1435 *-------------------------------------------------------------------------*/
1436
1437/* reset the HC and BUS */
1438
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001439static int hc_reset(struct ohci *ohci)
wdenkde887eb2003-09-10 18:20:28 +00001440{
1441 int timeout = 30;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001442 int smm_timeout = 50; /* 0,5 sec */
wdenkde887eb2003-09-10 18:20:28 +00001443
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001444 if (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
1445 /* SMM owns the HC - request ownership */
1446 writel(OHCI_OCR, &ohci->regs->cmdstatus);
wdenkde887eb2003-09-10 18:20:28 +00001447 info("USB HC TakeOver from SMM");
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001448 while (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
Mike Frysinger60ce19a2012-03-05 13:47:00 +00001449 mdelay(10);
wdenkde887eb2003-09-10 18:20:28 +00001450 if (--smm_timeout == 0) {
1451 err("USB HC TakeOver failed!");
1452 return -1;
1453 }
1454 }
1455 }
1456
1457 /* Disable HC interrupts */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001458 writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
wdenkde887eb2003-09-10 18:20:28 +00001459
1460 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001461 ohci->slot_name, readl(&ohci->regs->control));
wdenkde887eb2003-09-10 18:20:28 +00001462
wdenk9c53f402003-10-15 23:53:47 +00001463 /* Reset USB (needed by some controllers) */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001464 writel(0, &ohci->regs->control);
wdenkde887eb2003-09-10 18:20:28 +00001465
1466 /* HC Reset requires max 10 us delay */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001467 writel(OHCI_HCR, &ohci->regs->cmdstatus);
1468 while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
wdenkde887eb2003-09-10 18:20:28 +00001469 if (--timeout == 0) {
1470 err("USB HC reset timed out!");
1471 return -1;
1472 }
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001473 udelay(1);
wdenkde887eb2003-09-10 18:20:28 +00001474 }
1475 return 0;
1476}
1477
1478/*-------------------------------------------------------------------------*/
1479
1480/* Start an OHCI controller, set the BUS operational
1481 * enable interrupts
1482 * connect the virtual root hub */
1483
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001484static int hc_start(struct ohci *ohci)
wdenkde887eb2003-09-10 18:20:28 +00001485{
wdenk9c53f402003-10-15 23:53:47 +00001486 __u32 mask;
1487 unsigned int fminterval;
wdenkde887eb2003-09-10 18:20:28 +00001488
1489 ohci->disabled = 1;
1490
1491 /* Tell the controller where the control and bulk lists are
1492 * The lists are empty now. */
1493
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001494 writel(0, &ohci->regs->ed_controlhead);
1495 writel(0, &ohci->regs->ed_bulkhead);
wdenkde887eb2003-09-10 18:20:28 +00001496
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001497 /* a reset clears this */
1498 writel((__u32) ohci->hcca, &ohci->regs->hcca);
wdenkde887eb2003-09-10 18:20:28 +00001499
wdenk9c53f402003-10-15 23:53:47 +00001500 fminterval = 0x2edf;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001501 writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
wdenkde887eb2003-09-10 18:20:28 +00001502 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001503 writel(fminterval, &ohci->regs->fminterval);
1504 writel(0x628, &ohci->regs->lsthresh);
wdenkde887eb2003-09-10 18:20:28 +00001505
wdenk9c53f402003-10-15 23:53:47 +00001506 /* start controller operations */
1507 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
wdenkde887eb2003-09-10 18:20:28 +00001508 ohci->disabled = 0;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001509 writel(ohci->hc_control, &ohci->regs->control);
wdenkde887eb2003-09-10 18:20:28 +00001510
dzu8d7e4d12003-09-29 21:55:54 +00001511 /* disable all interrupts */
1512 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001513 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1514 OHCI_INTR_OC | OHCI_INTR_MIE);
1515 writel(mask, &ohci->regs->intrdisable);
dzu8d7e4d12003-09-29 21:55:54 +00001516 /* clear all interrupts */
1517 mask &= ~OHCI_INTR_MIE;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001518 writel(mask, &ohci->regs->intrstatus);
dzu8d7e4d12003-09-29 21:55:54 +00001519 /* Choose the interrupts we care about now - but w/o MIE */
1520 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001521 writel(mask, &ohci->regs->intrenable);
wdenkde887eb2003-09-10 18:20:28 +00001522
1523#ifdef OHCI_USE_NPS
1524 /* required for AMD-756 and some Mac platforms */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001525 writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
1526 &ohci->regs->roothub.a);
1527 writel(RH_HS_LPSC, &ohci->regs->roothub.status);
1528#endif /* OHCI_USE_NPS */
wdenkde887eb2003-09-10 18:20:28 +00001529
wdenkde887eb2003-09-10 18:20:28 +00001530 /* POTPGT delay is bits 24-31, in 2 ms units. */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001531 mdelay((roothub_a(ohci) >> 23) & 0x1fe);
wdenkde887eb2003-09-10 18:20:28 +00001532
1533 /* connect the virtual root hub */
1534 ohci->rh.devnum = 0;
1535
1536 return 0;
1537}
1538
1539/*-------------------------------------------------------------------------*/
1540
1541/* an interrupt happens */
1542
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001543static int hc_interrupt(void)
wdenkde887eb2003-09-10 18:20:28 +00001544{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001545 struct ohci *ohci = &gohci;
wdenkde887eb2003-09-10 18:20:28 +00001546 struct ohci_regs *regs = ohci->regs;
wdenk9c53f402003-10-15 23:53:47 +00001547 int ints;
wdenkde887eb2003-09-10 18:20:28 +00001548 int stat = -1;
1549
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001550 if ((ohci->hcca->done_head != 0) &&
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001551 !(m32_swap(ohci->hcca->done_head) & 0x01)) {
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001552
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001553 ints = OHCI_INTR_WDH;
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001554
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001555 } else {
1556 ints = readl(&regs->intrstatus);
1557 if (ints == ~(u32) 0) {
1558 ohci->disabled++;
1559 err("%s device removed!", ohci->slot_name);
1560 return -1;
1561 }
1562 ints &= readl(&regs->intrenable);
1563 if (ints == 0) {
1564 dbg("hc_interrupt: returning..\n");
1565 return 0xff;
1566 }
wdenkde887eb2003-09-10 18:20:28 +00001567 }
1568
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001569 /* dbg("Interrupt: %x frame: %x", ints,
1570 le16_to_cpu(ohci->hcca->frame_no)); */
wdenkde887eb2003-09-10 18:20:28 +00001571
dzu8d7e4d12003-09-29 21:55:54 +00001572 if (ints & OHCI_INTR_RHSC) {
1573 got_rhsc = 1;
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001574 stat = 0xff;
dzu8d7e4d12003-09-29 21:55:54 +00001575 }
1576
wdenkde887eb2003-09-10 18:20:28 +00001577 if (ints & OHCI_INTR_UE) {
1578 ohci->disabled++;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001579 err("OHCI Unrecoverable Error, controller usb-%s disabled",
1580 ohci->slot_name);
wdenkde887eb2003-09-10 18:20:28 +00001581 /* e.g. due to PCI Master/Target Abort */
1582
1583#ifdef DEBUG
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001584 ohci_dump(ohci, 1);
wdenkde887eb2003-09-10 18:20:28 +00001585#else
Mike Frysinger60ce19a2012-03-05 13:47:00 +00001586 mdelay(1);
wdenkde887eb2003-09-10 18:20:28 +00001587#endif
1588 /* FIXME: be optimistic, hope that bug won't repeat often. */
1589 /* Make some non-interrupt context restart the controller. */
1590 /* Count and limit the retries though; either hardware or */
1591 /* software errors can go forever... */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001592 hc_reset(ohci);
wdenkde887eb2003-09-10 18:20:28 +00001593 return -1;
1594 }
1595
1596 if (ints & OHCI_INTR_WDH) {
Mike Frysinger60ce19a2012-03-05 13:47:00 +00001597 mdelay(1);
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001598
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001599 writel(OHCI_INTR_WDH, &regs->intrdisable);
1600 stat = dl_done_list(&gohci, dl_reverse_done_list(&gohci));
1601 writel(OHCI_INTR_WDH, &regs->intrenable);
wdenkde887eb2003-09-10 18:20:28 +00001602 }
1603
1604 if (ints & OHCI_INTR_SO) {
1605 dbg("USB Schedule overrun\n");
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001606 writel(OHCI_INTR_SO, &regs->intrenable);
wdenkde887eb2003-09-10 18:20:28 +00001607 stat = -1;
1608 }
1609
1610 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1611 if (ints & OHCI_INTR_SF) {
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001612 unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
Mike Frysinger60ce19a2012-03-05 13:47:00 +00001613 mdelay(1);
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001614 writel(OHCI_INTR_SF, &regs->intrdisable);
wdenkde887eb2003-09-10 18:20:28 +00001615 if (ohci->ed_rm_list[frame] != NULL)
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001616 writel(OHCI_INTR_SF, &regs->intrenable);
wdenkde887eb2003-09-10 18:20:28 +00001617 stat = 0xff;
1618 }
1619
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001620 writel(ints, &regs->intrstatus);
wdenkde887eb2003-09-10 18:20:28 +00001621 return stat;
1622}
1623
1624/*-------------------------------------------------------------------------*/
1625
1626/*-------------------------------------------------------------------------*/
1627
1628/* De-allocate all resources.. */
1629
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001630static void hc_release_ohci(struct ohci *ohci)
wdenkde887eb2003-09-10 18:20:28 +00001631{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001632 dbg("USB HC release ohci usb-%s", ohci->slot_name);
wdenkde887eb2003-09-10 18:20:28 +00001633
1634 if (!ohci->disabled)
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001635 hc_reset(ohci);
wdenkde887eb2003-09-10 18:20:28 +00001636}
1637
1638/*-------------------------------------------------------------------------*/
1639
1640/*
1641 * low level initalisation routine, called from usb.c
1642 */
1643static char ohci_inited = 0;
1644
Troy Kisky8f9c49d2013-10-10 15:27:56 -07001645int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
wdenkde887eb2003-09-10 18:20:28 +00001646{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001647 struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
1648 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
wdenkde887eb2003-09-10 18:20:28 +00001649
wdenk9c53f402003-10-15 23:53:47 +00001650 /*
1651 * Set the 48 MHz UPLL clocking. Values are taken from
1652 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
1653 */
C Nauman383c43e2010-10-26 23:04:31 +09001654 clk_power->upllcon = ((40 << 12) + (1 << 4) + 2);
1655 gpio->misccr |= 0x8; /* 1 = use pads related USB for USB host */
wdenkde887eb2003-09-10 18:20:28 +00001656
wdenk9c53f402003-10-15 23:53:47 +00001657 /*
1658 * Enable USB host clock.
1659 */
C Nauman383c43e2010-10-26 23:04:31 +09001660 clk_power->clkcon |= (1 << 4);
wdenkde887eb2003-09-10 18:20:28 +00001661
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001662 memset(&gohci, 0, sizeof(struct ohci));
1663 memset(&urb_priv, 0, sizeof(struct urb_priv));
wdenkde887eb2003-09-10 18:20:28 +00001664
1665 /* align the storage */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001666 if ((__u32) &ghcca[0] & 0xff) {
wdenkde887eb2003-09-10 18:20:28 +00001667 err("HCCA not aligned!!");
1668 return -1;
1669 }
1670 phcca = &ghcca[0];
1671 info("aligned ghcca %p", phcca);
1672 memset(&ohci_dev, 0, sizeof(struct ohci_device));
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001673 if ((__u32) &ohci_dev.ed[0] & 0x7) {
wdenkde887eb2003-09-10 18:20:28 +00001674 err("EDs not aligned!!");
1675 return -1;
1676 }
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001677 memset(gtd, 0, sizeof(struct td) * (NUM_TD + 1));
1678 if ((__u32) gtd & 0x7) {
wdenkde887eb2003-09-10 18:20:28 +00001679 err("TDs not aligned!!");
1680 return -1;
1681 }
1682 ptd = gtd;
1683 gohci.hcca = phcca;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001684 memset(phcca, 0, sizeof(struct ohci_hcca));
wdenkde887eb2003-09-10 18:20:28 +00001685
1686 gohci.disabled = 1;
1687 gohci.sleeping = 0;
1688 gohci.irq = -1;
1689 gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE;
1690
1691 gohci.flags = 0;
1692 gohci.slot_name = "s3c2400";
1693
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001694 if (hc_reset(&gohci) < 0) {
1695 hc_release_ohci(&gohci);
wdenk9c53f402003-10-15 23:53:47 +00001696 /* Initialization failed */
C Nauman383c43e2010-10-26 23:04:31 +09001697 clk_power->clkcon &= ~(1 << 4);
wdenkde887eb2003-09-10 18:20:28 +00001698 return -1;
1699 }
1700
1701 /* FIXME this is a second HC reset; why?? */
Wolfgang Denk10e4f542006-03-11 23:07:09 +01001702 gohci.hc_control = OHCI_USB_RESET;
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001703 writel(gohci.hc_control, &gohci.regs->control);
Mike Frysinger60ce19a2012-03-05 13:47:00 +00001704 mdelay(10);
wdenkde887eb2003-09-10 18:20:28 +00001705
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001706 if (hc_start(&gohci) < 0) {
1707 err("can't start usb-%s", gohci.slot_name);
1708 hc_release_ohci(&gohci);
wdenk9c53f402003-10-15 23:53:47 +00001709 /* Initialization failed */
C Nauman383c43e2010-10-26 23:04:31 +09001710 clk_power->clkcon &= ~(1 << 4);
wdenkde887eb2003-09-10 18:20:28 +00001711 return -1;
1712 }
wdenkde887eb2003-09-10 18:20:28 +00001713#ifdef DEBUG
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001714 ohci_dump(&gohci, 1);
wdenkde887eb2003-09-10 18:20:28 +00001715#else
Mike Frysinger60ce19a2012-03-05 13:47:00 +00001716 mdelay(1);
wdenkde887eb2003-09-10 18:20:28 +00001717#endif
1718 ohci_inited = 1;
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001719 urb_finished = 1;
1720
wdenkde887eb2003-09-10 18:20:28 +00001721 return 0;
1722}
1723
Lucas Stacha3231282012-09-26 00:14:34 +02001724int usb_lowlevel_stop(int index)
wdenkde887eb2003-09-10 18:20:28 +00001725{
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001726 struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
wdenkde887eb2003-09-10 18:20:28 +00001727
1728 /* this gets called really early - before the controller has */
1729 /* even been initialized! */
1730 if (!ohci_inited)
1731 return 0;
1732 /* TODO release any interrupts, etc. */
1733 /* call hc_release_ohci() here ? */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +09001734 hc_reset(&gohci);
wdenkde887eb2003-09-10 18:20:28 +00001735 /* may not want to do this */
C Nauman383c43e2010-10-26 23:04:31 +09001736 clk_power->clkcon &= ~(1 << 4);
wdenkde887eb2003-09-10 18:20:28 +00001737 return 0;
1738}
1739
kevin.morfitt@fearnside-systems.co.uke0d81312009-11-17 18:30:34 +09001740#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) */
Marek Vasute917a7c2012-07-21 05:02:22 +00001741
1742#if defined(CONFIG_USB_OHCI_NEW) && \
1743 defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
1744 defined(CONFIG_S3C24X0)
1745
1746int usb_cpu_init(void)
1747{
1748 struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
1749 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
1750
1751 /*
1752 * Set the 48 MHz UPLL clocking. Values are taken from
1753 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
1754 */
1755 writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
1756 /* 1 = use pads related USB for USB host */
1757 writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
1758
1759 /*
1760 * Enable USB host clock.
1761 */
1762 writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
1763
1764 return 0;
1765}
1766
1767int usb_cpu_stop(void)
1768{
1769 struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
1770 /* may not want to do this */
1771 writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
1772 return 0;
1773}
1774
1775int usb_cpu_init_fail(void)
1776{
1777 struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
1778 writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
1779 return 0;
1780}
1781
1782#endif /* defined(CONFIG_USB_OHCI_NEW) && \
1783 defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
1784 defined(CONFIG_S3C24X0) */