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git01.mediatek.com / filogic / uboot / ea33c6ac0d2c92c8772e005fc1e4c7bd8018d7c1 / . / board / sbc8641d / law.c
blob: c4e736b8aa408680b79500752a187d267cd0157d [file] [log] [blame]
Becky Brucea756ea72008-01-23 16:31:03 -0600[diff] [blame]1/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
Becky Brucea756ea72008-01-23 16:31:03 -0600[diff] [blame]8 */
9
10#include <common.h>
11#include <asm/fsl_law.h>
12#include <asm/mmu.h>
13
14/*
15 * LAW (Local Access Window) configuration:
16 *
17 * 0x0000_0000 DDR 256M
18 * 0x1000_0000 DDR2 256M
Kumar Galae78f6652010-07-09 00:02:34 -0500[diff] [blame]19 * 0x8000_0000 PCIE1 MEM 512M
20 * 0xa000_0000 PCIE2 MEM 512M
Becky Brucea756ea72008-01-23 16:31:03 -0600[diff] [blame]21 * 0xc000_0000 RapidIO 512M
Kumar Galae78f6652010-07-09 00:02:34 -0500[diff] [blame]22 * 0xe200_0000 PCIE1 IO 16M
23 * 0xe300_0000 PCIE2 IO 16M
Becky Brucea756ea72008-01-23 16:31:03 -0600[diff] [blame]24 * 0xf800_0000 CCSRBAR 2M
25 * 0xfe00_0000 FLASH (boot bank) 32M
26 *
27 */
28
29
30struct law_entry law_table[] = {
Paul Gortmaker0253f602009-09-30 16:12:31 -0400[diff] [blame]31#if !defined(CONFIG_SPD_EEPROM)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]32 SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
Paul Gortmaker0253f602009-09-30 16:12:31 -0400[diff] [blame]33 SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
34 LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
35#endif
Kumar Gala994fdba2008-06-11 00:51:45 -0500[diff] [blame]36 SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
Kumar Gala994fdba2008-06-11 00:51:45 -0500[diff] [blame]37 SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
Becky Brucea756ea72008-01-23 16:31:03 -0600[diff] [blame]38};
39
40int num_law_entries = ARRAY_SIZE(law_table);