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git01.mediatek.com / filogic / uboot / ea19a8d49c230a5799443e4e7c17c29ad3831335 / . / drivers / clk / sunxi / clk_a80.c
blob: 80d7407037e553449d1c35ff6593c32cde40e483 [file] [log] [blame]
Jagan Tekie366a0c2019-01-11 15:41:46 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun9i-a80-ccu.h>
13#include <dt-bindings/reset/sun9i-a80-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Jagan Tekie366a0c2019-01-11 15:41:46 +0530[diff] [blame]15
16static const struct ccu_clk_gate a80_gates[] = {
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]17 [CLK_SPI0] = GATE(0x430, BIT(31)),
18 [CLK_SPI1] = GATE(0x434, BIT(31)),
19 [CLK_SPI2] = GATE(0x438, BIT(31)),
20 [CLK_SPI3] = GATE(0x43c, BIT(31)),
21
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]22 [CLK_BUS_MMC] = GATE(0x580, BIT(8)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]23 [CLK_BUS_SPI0] = GATE(0x580, BIT(20)),
24 [CLK_BUS_SPI1] = GATE(0x580, BIT(21)),
25 [CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
26 [CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]27
Jagan Tekie366a0c2019-01-11 15:41:46 +0530[diff] [blame]28 [CLK_BUS_UART0] = GATE(0x594, BIT(16)),
29 [CLK_BUS_UART1] = GATE(0x594, BIT(17)),
30 [CLK_BUS_UART2] = GATE(0x594, BIT(18)),
31 [CLK_BUS_UART3] = GATE(0x594, BIT(19)),
32 [CLK_BUS_UART4] = GATE(0x594, BIT(20)),
33 [CLK_BUS_UART5] = GATE(0x594, BIT(21)),
34};
35
36static const struct ccu_reset a80_resets[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]37 [RST_BUS_MMC] = RESET(0x5a0, BIT(8)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]38 [RST_BUS_SPI0] = RESET(0x5a0, BIT(20)),
39 [RST_BUS_SPI1] = RESET(0x5a0, BIT(21)),
40 [RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
41 [RST_BUS_SPI3] = RESET(0x5a0, BIT(23)),
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]42
Jagan Tekie366a0c2019-01-11 15:41:46 +0530[diff] [blame]43 [RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
44 [RST_BUS_UART1] = RESET(0x5b4, BIT(17)),
45 [RST_BUS_UART2] = RESET(0x5b4, BIT(18)),
46 [RST_BUS_UART3] = RESET(0x5b4, BIT(19)),
47 [RST_BUS_UART4] = RESET(0x5b4, BIT(20)),
48 [RST_BUS_UART5] = RESET(0x5b4, BIT(21)),
49};
50
Andre Przywara8c8c8a42019-01-29 15:54:10 +0000[diff] [blame]51static const struct ccu_clk_gate a80_mmc_gates[] = {
52 [0] = GATE(0x0, BIT(16)),
53 [1] = GATE(0x4, BIT(16)),
54 [2] = GATE(0x8, BIT(16)),
55 [3] = GATE(0xc, BIT(16)),
56};
57
58static const struct ccu_reset a80_mmc_resets[] = {
59 [0] = GATE(0x0, BIT(18)),
60 [1] = GATE(0x4, BIT(18)),
61 [2] = GATE(0x8, BIT(18)),
62 [3] = GATE(0xc, BIT(18)),
63};
64
Jagan Tekie366a0c2019-01-11 15:41:46 +0530[diff] [blame]65static const struct ccu_desc a80_ccu_desc = {
66 .gates = a80_gates,
67 .resets = a80_resets,
68};
69
Andre Przywara8c8c8a42019-01-29 15:54:10 +0000[diff] [blame]70static const struct ccu_desc a80_mmc_clk_desc = {
71 .gates = a80_mmc_gates,
72 .resets = a80_mmc_resets,
73};
74
Jagan Tekie366a0c2019-01-11 15:41:46 +0530[diff] [blame]75static int a80_clk_bind(struct udevice *dev)
76{
Andre Przywara8c8c8a42019-01-29 15:54:10 +0000[diff] [blame]77 ulong count = ARRAY_SIZE(a80_resets);
78
79 if (device_is_compatible(dev, "allwinner,sun9i-a80-mmc-config-clk"))
80 count = ARRAY_SIZE(a80_mmc_resets);
81
82 return sunxi_reset_bind(dev, count);
Jagan Tekie366a0c2019-01-11 15:41:46 +0530[diff] [blame]83}
84
85static const struct udevice_id a80_ccu_ids[] = {
86 { .compatible = "allwinner,sun9i-a80-ccu",
87 .data = (ulong)&a80_ccu_desc },
Andre Przywara8c8c8a42019-01-29 15:54:10 +0000[diff] [blame]88 { .compatible = "allwinner,sun9i-a80-mmc-config-clk",
89 .data = (ulong)&a80_mmc_clk_desc },
Jagan Tekie366a0c2019-01-11 15:41:46 +0530[diff] [blame]90 { }
91};
92
93U_BOOT_DRIVER(clk_sun9i_a80) = {
94 .name = "sun9i_a80_ccu",
95 .id = UCLASS_CLK,
96 .of_match = a80_ccu_ids,
97 .priv_auto_alloc_size = sizeof(struct ccu_priv),
98 .ops = &sunxi_clk_ops,
99 .probe = sunxi_clk_probe,
100 .bind = a80_clk_bind,
101};