Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Stefan Roese | 7be1b9b | 2016-05-25 08:21:21 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2016 Stefan Roese <sr@denx.de> |
Stefan Roese | 7be1b9b | 2016-05-25 08:21:21 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
Stefan Roese | 5c806f1 | 2016-10-25 10:56:19 +0200 | [diff] [blame] | 6 | #ifndef _CONFIG_MVEBU_ARMADA_8K_H |
| 7 | #define _CONFIG_MVEBU_ARMADA_8K_H |
Stefan Roese | 7be1b9b | 2016-05-25 08:21:21 +0200 | [diff] [blame] | 8 | |
| 9 | /* |
| 10 | * High Level Configuration Options (easy to change) |
| 11 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 12 | #define CFG_SYS_TCLK 250000000 /* 250MHz */ |
Stefan Roese | 7be1b9b | 2016-05-25 08:21:21 +0200 | [diff] [blame] | 13 | |
Stefan Roese | 7be1b9b | 2016-05-25 08:21:21 +0200 | [diff] [blame] | 14 | /* additions for new ARM relocation support */ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 15 | #define CFG_SYS_SDRAM_BASE 0x00000000 |
Stefan Roese | 7be1b9b | 2016-05-25 08:21:21 +0200 | [diff] [blame] | 16 | |
Stefan Roese | 7be1b9b | 2016-05-25 08:21:21 +0200 | [diff] [blame] | 17 | /* auto boot */ |
Stefan Roese | 7be1b9b | 2016-05-25 08:21:21 +0200 | [diff] [blame] | 18 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 19 | #define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ |
Stefan Roese | 7be1b9b | 2016-05-25 08:21:21 +0200 | [diff] [blame] | 20 | 115200, 230400, 460800, 921600 } |
| 21 | |
Stefan Roese | 7be1b9b | 2016-05-25 08:21:21 +0200 | [diff] [blame] | 22 | /* |
Stefan Roese | 7be1b9b | 2016-05-25 08:21:21 +0200 | [diff] [blame] | 23 | * Other required minimal configurations |
| 24 | */ |
Stefan Roese | 7be1b9b | 2016-05-25 08:21:21 +0200 | [diff] [blame] | 25 | |
Baruch Siach | 0d02290 | 2018-08-14 18:05:46 +0300 | [diff] [blame] | 26 | /* When runtime detection fails this is the default */ |
Baruch Siach | 0d02290 | 2018-08-14 18:05:46 +0300 | [diff] [blame] | 27 | |
Stefan Roese | 7be1b9b | 2016-05-25 08:21:21 +0200 | [diff] [blame] | 28 | /* USB ethernet */ |
Stefan Roese | 7be1b9b | 2016-05-25 08:21:21 +0200 | [diff] [blame] | 29 | |
| 30 | /* |
Stefan Roese | c20e9d5 | 2016-10-27 13:36:45 +0200 | [diff] [blame] | 31 | * PCI configuration |
| 32 | */ |
Robert Marko | efabf9c | 2024-06-21 11:46:02 +0200 | [diff] [blame] | 33 | #ifdef CONFIG_DISTRO_DEFAULTS |
Mark Kettenis | 8cfb67b | 2018-03-17 09:34:27 +0100 | [diff] [blame] | 34 | #define BOOT_TARGET_DEVICES(func) \ |
| 35 | func(MMC, mmc, 1) \ |
| 36 | func(MMC, mmc, 0) \ |
| 37 | func(USB, usb, 0) \ |
| 38 | func(SCSI, scsi, 0) \ |
| 39 | func(PXE, pxe, na) \ |
| 40 | func(DHCP, dhcp, na) |
| 41 | |
| 42 | #include <config_distro_bootcmd.h> |
Robert Marko | efabf9c | 2024-06-21 11:46:02 +0200 | [diff] [blame] | 43 | #else |
| 44 | #define BOOTENV |
| 45 | #endif |
Mark Kettenis | 8cfb67b | 2018-03-17 09:34:27 +0100 | [diff] [blame] | 46 | |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 47 | #define CFG_EXTRA_ENV_SETTINGS \ |
Heinrich Schuchardt | 3ce7a60 | 2021-06-08 12:00:35 +0200 | [diff] [blame] | 48 | "scriptaddr=0x6d00000\0" \ |
| 49 | "pxefile_addr_r=0x6e00000\0" \ |
| 50 | "fdt_addr_r=0x6f00000\0" \ |
| 51 | "kernel_addr_r=0x7000000\0" \ |
| 52 | "ramdisk_addr_r=0xa000000\0" \ |
Mark Kettenis | 8cfb67b | 2018-03-17 09:34:27 +0100 | [diff] [blame] | 53 | "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ |
| 54 | BOOTENV |
| 55 | |
Stefan Roese | 5c806f1 | 2016-10-25 10:56:19 +0200 | [diff] [blame] | 56 | #endif /* _CONFIG_MVEBU_ARMADA_8K_H */ |