Paul Barker | f4aa550 | 2023-10-16 10:25:42 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | /* |
| 3 | * Device Tree Source for the RZ/{G2L,V2L} SMARC pincontrol parts |
| 4 | * |
| 5 | * Copyright (C) 2021 Renesas Electronics Corp. |
| 6 | */ |
| 7 | |
| 8 | #include <dt-bindings/gpio/gpio.h> |
| 9 | #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> |
| 10 | |
| 11 | &pinctrl { |
| 12 | pinctrl-0 = <&sound_clk_pins>; |
| 13 | pinctrl-names = "default"; |
| 14 | |
| 15 | can0_pins: can0 { |
| 16 | pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */ |
| 17 | <RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */ |
| 18 | }; |
| 19 | |
| 20 | /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */ |
| 21 | can0-stb-hog { |
| 22 | gpio-hog; |
| 23 | gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>; |
| 24 | output-low; |
| 25 | line-name = "can0_stb"; |
| 26 | }; |
| 27 | |
| 28 | can1_pins: can1 { |
| 29 | pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */ |
| 30 | <RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */ |
| 31 | }; |
| 32 | |
| 33 | /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ |
| 34 | can1-stb-hog { |
| 35 | gpio-hog; |
| 36 | gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>; |
| 37 | output-low; |
| 38 | line-name = "can1_stb"; |
| 39 | }; |
| 40 | |
| 41 | i2c0_pins: i2c0 { |
| 42 | pins = "RIIC0_SDA", "RIIC0_SCL"; |
| 43 | input-enable; |
| 44 | }; |
| 45 | |
| 46 | i2c1_pins: i2c1 { |
| 47 | pins = "RIIC1_SDA", "RIIC1_SCL"; |
| 48 | input-enable; |
| 49 | }; |
| 50 | |
| 51 | i2c3_pins: i2c3 { |
| 52 | pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */ |
| 53 | <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */ |
| 54 | }; |
| 55 | |
Paul Barker | aafdcc9 | 2024-02-27 20:40:29 +0000 | [diff] [blame] | 56 | mtu3_pins: mtu3 { |
| 57 | mtu3-ext-clk-input-pin { |
| 58 | pinmux = <RZG2L_PORT_PINMUX(48, 0, 4)>, /* MTCLKA */ |
| 59 | <RZG2L_PORT_PINMUX(48, 1, 4)>; /* MTCLKB */ |
| 60 | }; |
| 61 | |
| 62 | mtu3-pwm { |
| 63 | pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */ |
| 64 | <RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */ |
| 65 | <RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */ |
| 66 | <RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */ |
| 67 | }; |
| 68 | |
| 69 | #if MTU3_COUNTER_Z_PHASE_SIGNAL |
| 70 | mtu3-zphase-clk { |
| 71 | pinmux = <RZG2L_PORT_PINMUX(19, 0, 3)>; /* MTIOC1A */ |
| 72 | }; |
| 73 | #endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */ |
| 74 | }; |
| 75 | |
Paul Barker | f4aa550 | 2023-10-16 10:25:42 +0100 | [diff] [blame] | 76 | scif0_pins: scif0 { |
| 77 | pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */ |
| 78 | <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ |
| 79 | }; |
| 80 | |
| 81 | scif2_pins: scif2 { |
| 82 | pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */ |
| 83 | <RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */ |
| 84 | <RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */ |
| 85 | <RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */ |
| 86 | }; |
| 87 | |
| 88 | sd1-pwr-en-hog { |
| 89 | gpio-hog; |
| 90 | gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>; |
| 91 | output-high; |
| 92 | line-name = "sd1_pwr_en"; |
| 93 | }; |
| 94 | |
| 95 | sdhi1_pins: sd1 { |
| 96 | sd1_data { |
| 97 | pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; |
| 98 | power-source = <3300>; |
| 99 | }; |
| 100 | |
| 101 | sd1_ctrl { |
| 102 | pins = "SD1_CLK", "SD1_CMD"; |
| 103 | power-source = <3300>; |
| 104 | }; |
| 105 | |
| 106 | sd1_mux { |
| 107 | pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */ |
| 108 | }; |
| 109 | }; |
| 110 | |
| 111 | sdhi1_pins_uhs: sd1_uhs { |
| 112 | sd1_data_uhs { |
| 113 | pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; |
| 114 | power-source = <1800>; |
| 115 | }; |
| 116 | |
| 117 | sd1_ctrl_uhs { |
| 118 | pins = "SD1_CLK", "SD1_CMD"; |
| 119 | power-source = <1800>; |
| 120 | }; |
| 121 | |
| 122 | sd1_mux_uhs { |
| 123 | pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */ |
| 124 | }; |
| 125 | }; |
| 126 | |
| 127 | sound_clk_pins: sound_clk { |
| 128 | pins = "AUDIO_CLK1", "AUDIO_CLK2"; |
| 129 | input-enable; |
| 130 | }; |
| 131 | |
| 132 | spi1_pins: spi1 { |
| 133 | pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */ |
| 134 | <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */ |
| 135 | <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */ |
| 136 | <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */ |
| 137 | }; |
| 138 | |
| 139 | ssi0_pins: ssi0 { |
| 140 | pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */ |
| 141 | <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */ |
| 142 | <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */ |
| 143 | <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */ |
| 144 | }; |
| 145 | |
| 146 | usb0_pins: usb0 { |
| 147 | pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */ |
| 148 | <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */ |
| 149 | <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */ |
| 150 | }; |
| 151 | |
| 152 | usb1_pins: usb1 { |
| 153 | pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */ |
| 154 | <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */ |
| 155 | }; |
| 156 | }; |
| 157 | |