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Manivannan Sadhasivam474a5df2018-06-14 23:38:31 +05301// SPDX-License-Identifier: GPL-2.0+
2//
3// Device Tree Source for Actions Semi S900 SoC
4//
5// Copyright (C) 2015 Actions Semi Co., Ltd.
6// Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
7
8/dts-v1/;
Manivannan Sadhasivam611b19f2018-06-14 23:38:34 +05309#include <dt-bindings/clock/s900_cmu.h>
Manivannan Sadhasivam474a5df2018-06-14 23:38:31 +053010
11/ {
12 compatible = "actions,s900";
13 #address-cells = <0x2>;
14 #size-cells = <0x2>;
15
Manivannan Sadhasivam611b19f2018-06-14 23:38:34 +053016 losc: losc {
17 compatible = "fixed-clock";
18 clock-frequency = <32768>;
19 #clock-cells = <0>;
20 };
21
22 diff24M: diff24M {
23 compatible = "fixed-clock";
24 clock-frequency = <24000000>;
25 #clock-cells = <0>;
26 };
27
Manivannan Sadhasivam474a5df2018-06-14 23:38:31 +053028 soc {
29 u-boot,dm-pre-reloc;
30 compatible = "simple-bus";
31 #address-cells = <0x2>;
32 #size-cells = <0x2>;
33 ranges;
Manivannan Sadhasivam611b19f2018-06-14 23:38:34 +053034
Manivannan Sadhasivam1c4d3482018-06-14 23:38:36 +053035 uart5: serial@e012a000 {
36 u-boot,dm-pre-reloc;
37 compatible = "actions,s900-serial";
38 reg = <0x0 0xe012a000 0x0 0x1000>;
39 clocks = <&cmu CLOCK_UART5>;
40 status = "disabled";
41 };
42
Manivannan Sadhasivam611b19f2018-06-14 23:38:34 +053043 cmu: clock-controller@e0160000 {
44 u-boot,dm-pre-reloc;
45 compatible = "actions,s900-cmu";
46 reg = <0x0 0xe0160000 0x0 0x1000>;
47 clocks = <&losc>, <&diff24M>;
48 clock-names = "losc", "diff24M";
49 #clock-cells = <1>;
50 };
Manivannan Sadhasivam474a5df2018-06-14 23:38:31 +053051 };
52};
53