Gabriel Huau | c4824ff | 2012-05-02 10:48:37 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 4 | * Marius Groeger <mgroeger@sysgo.de> |
| 5 | * Gary Jennejohn <gj@denx.de> |
| 6 | * David Mueller <d.mueller@elsoft.ch> |
| 7 | * |
| 8 | * (C) Copyright 2009-2010 |
| 9 | * Michel Pollet <buserror@gmail.com> |
| 10 | * |
| 11 | * (C) Copyright 2012 |
| 12 | * Gabriel Huau <contact@huau-gabriel.fr> |
| 13 | * |
| 14 | * Configuation settings for the MINI2440 board. |
| 15 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 16 | * SPDX-License-Identifier: GPL-2.0+ |
Gabriel Huau | c4824ff | 2012-05-02 10:48:37 +0000 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #ifndef __CONFIG_H |
| 20 | #define __CONFIG_H |
| 21 | |
| 22 | #define CONFIG_SYS_TEXT_BASE 0x0 |
| 23 | #define CONFIG_S3C2440_GPIO |
| 24 | |
| 25 | /* |
| 26 | * High Level Configuration Options |
| 27 | */ |
| 28 | #define CONFIG_ARM920T /* This is an ARM920T Core */ |
| 29 | #define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */ |
| 30 | #define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */ |
| 31 | #define CONFIG_MINI2440 /* on a MIN2440 Board */ |
| 32 | |
| 33 | #define MACH_TYPE_MINI2440 1999 |
| 34 | #define CONFIG_MACH_TYPE MACH_TYPE_MINI2440 |
| 35 | |
| 36 | /* |
| 37 | * We don't use lowlevel_init |
| 38 | */ |
| 39 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 40 | #define CONFIG_BOARD_EARLY_INIT_F |
| 41 | |
| 42 | /* |
| 43 | * input clock of PLL |
| 44 | */ |
| 45 | /* MINI2440 has 12.0000MHz input clock */ |
| 46 | #define CONFIG_SYS_CLK_FREQ 12000000 |
| 47 | |
| 48 | /* |
| 49 | * Size of malloc() pool |
| 50 | */ |
| 51 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024) |
| 52 | |
| 53 | /* |
| 54 | * Hardware drivers |
| 55 | */ |
| 56 | #define CONFIG_DRIVER_DM9000 |
| 57 | #define CONFIG_DRIVER_DM9000_NO_EEPROM |
| 58 | #define CONFIG_DM9000_BASE 0x20000300 |
| 59 | #define DM9000_IO CONFIG_DM9000_BASE |
| 60 | #define DM9000_DATA (CONFIG_DM9000_BASE+4) |
| 61 | |
| 62 | /* |
| 63 | * select serial console configuration |
| 64 | */ |
| 65 | #define CONFIG_S3C24X0_SERIAL |
| 66 | #define CONFIG_SERIAL1 |
| 67 | |
| 68 | /* |
| 69 | * allow to overwrite serial and ethaddr |
| 70 | */ |
| 71 | #define CONFIG_ENV_OVERWRITE |
| 72 | |
| 73 | /* |
| 74 | * Command definition |
| 75 | */ |
| 76 | #include <config_cmd_default.h> |
| 77 | |
| 78 | #define CONFIG_CMD_DHCP |
| 79 | #define CONFIG_CMD_PORTIO |
| 80 | #define CONFIG_CMD_REGINFO |
| 81 | #define CONFIG_CMD_SAVES |
| 82 | |
| 83 | /* |
| 84 | * Miscellaneous configurable options |
| 85 | */ |
| 86 | #define CONFIG_LONGHELP |
| 87 | #define CONFIG_SYS_PROMPT "MINI2440 => " |
| 88 | #define CONFIG_SYS_CBSIZE 256 |
| 89 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
| 90 | #define CONFIG_SYS_MAXARGS 32 |
| 91 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 92 | |
| 93 | #define CONFIG_SYS_MEMTEST_START 0x30000000 |
| 94 | #define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */ |
| 95 | |
| 96 | /* default load address */ |
| 97 | #define CONFIG_SYS_LOAD_ADDR 0x32000000 |
| 98 | |
| 99 | /* boot parameters address */ |
| 100 | #define CONFIG_BOOT_PARAM_ADDR 0x30000100 |
| 101 | |
| 102 | /* |
| 103 | * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need |
| 104 | * it to wrap 100 times (total 1562500) to get 1 sec. |
| 105 | */ |
| 106 | #define CONFIG_SYS_HZ 1562500 |
| 107 | |
| 108 | /* |
| 109 | * valid baudrates |
| 110 | */ |
| 111 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 112 | #define CONFIG_BAUDRATE 115200 |
| 113 | |
| 114 | /* |
| 115 | * Stack sizes |
| 116 | * The stack sizes are set up in start.S using the settings below |
| 117 | */ |
| 118 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
| 119 | #ifdef CONFIG_USE_IRQ |
| 120 | #define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ |
| 121 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
| 122 | #endif |
| 123 | |
| 124 | /* |
| 125 | * Physical Memory Map |
| 126 | */ |
| 127 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
| 128 | #define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */ |
| 129 | #define CONFIG_SYS_SDRAM_BASE 0x30000000 |
| 130 | #define CONFIG_SYS_FLASH_BASE 0x0 |
| 131 | |
| 132 | /* |
| 133 | * Stack should be on the SRAM because |
| 134 | * DRAM is not init |
| 135 | */ |
| 136 | #define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE) |
| 137 | |
| 138 | /* |
| 139 | * NOR FLASH organization |
| 140 | * Now uses the standard CFI interface |
| 141 | * FLASH and environment organization |
| 142 | */ |
| 143 | #define CONFIG_SYS_FLASH_CFI |
| 144 | #define CONFIG_FLASH_CFI_DRIVER |
| 145 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
| 146 | #define CONFIG_SYS_MONITOR_BASE 0x0 |
| 147 | /* max number of memory banks */ |
| 148 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 149 | /* 512 * 4096 sectors, or 32 * 64k blocks */ |
| 150 | #define CONFIG_SYS_MAX_FLASH_SECT 512 |
| 151 | #define CONFIG_FLASH_SHOW_PROGRESS 1 |
| 152 | |
| 153 | /* |
| 154 | * Config for NOR flash |
| 155 | */ |
| 156 | #define CONFIG_ENV_IS_IN_FLASH |
| 157 | #define CONFIG_MY_ENV_OFFSET 0x40000 |
| 158 | /* addr of environment */ |
| 159 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET) |
| 160 | /* 16k Total Size of Environment Sector */ |
| 161 | #define CONFIG_ENV_SIZE 0x4000 |
| 162 | |
| 163 | /* ATAG configuration */ |
| 164 | #define CONFIG_INITRD_TAG |
| 165 | #define CONFIG_SETUP_MEMORY_TAGS |
| 166 | #define CONFIG_CMDLINE_TAG |
| 167 | #define CONFIG_CMDLINE_EDITING |
| 168 | #define CONFIG_AUTO_COMPLETE |
| 169 | |
| 170 | #endif /* __CONFIG_H */ |