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git01.mediatek.com / filogic / uboot / e9748b224336311c79cd6ae0c6f813004392a199 / . / dts / upstream / src / arm64 / ti / k3-am69-sk.dts
blob: 9868c7049bfb9f2ccc0385a2e2f8c33bcd3a6f59 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
4 *
5 * Design Files: https://www.ti.com/lit/zip/SPRR466
6 * TRM: https://www.ti.com/lit/zip/spruj52
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/net/ti-dp83867.h>
12#include <dt-bindings/gpio/gpio.h>
13#include "k3-j784s4.dtsi"
14
15/ {
16 compatible = "ti,am69-sk", "ti,j784s4";
17 model = "Texas Instruments AM69 SK";
18
19 chosen {
20 stdout-path = "serial2:115200n8";
21 };
22
23 aliases {
24 serial0 = &wkup_uart0;
25 serial1 = &mcu_uart0;
26 serial2 = &main_uart8;
27 mmc0 = &main_sdhci0;
28 mmc1 = &main_sdhci1;
29 i2c0 = &wkup_i2c0;
30 i2c3 = &main_i2c0;
31 ethernet0 = &mcu_cpsw_port1;
32 };
33
34 memory@80000000 {
35 device_type = "memory";
36 /* 32G RAM */
37 reg = <0x00 0x80000000 0x00 0x80000000>,
38 <0x08 0x80000000 0x07 0x80000000>;
39 };
40
41 reserved_memory: reserved-memory {
42 #address-cells = <2>;
43 #size-cells = <2>;
44 ranges;
45
46 secure_ddr: optee@9e800000 {
47 reg = <0x00 0x9e800000 0x00 0x01800000>;
48 no-map;
49 };
50
51 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
52 compatible = "shared-dma-pool";
53 reg = <0x00 0xa0000000 0x00 0x100000>;
54 no-map;
55 };
56
57 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
58 compatible = "shared-dma-pool";
59 reg = <0x00 0xa0100000 0x00 0xf00000>;
60 no-map;
61 };
62
63 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
64 compatible = "shared-dma-pool";
65 reg = <0x00 0xa1000000 0x00 0x100000>;
66 no-map;
67 };
68
69 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
70 compatible = "shared-dma-pool";
71 reg = <0x00 0xa1100000 0x00 0xf00000>;
72 no-map;
73 };
74
75 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
76 compatible = "shared-dma-pool";
77 reg = <0x00 0xa2000000 0x00 0x100000>;
78 no-map;
79 };
80
81 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
82 compatible = "shared-dma-pool";
83 reg = <0x00 0xa2100000 0x00 0xf00000>;
84 no-map;
85 };
86
87 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
88 compatible = "shared-dma-pool";
89 reg = <0x00 0xa3000000 0x00 0x100000>;
90 no-map;
91 };
92
93 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
94 compatible = "shared-dma-pool";
95 reg = <0x00 0xa3100000 0x00 0xf00000>;
96 no-map;
97 };
98
99 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
100 compatible = "shared-dma-pool";
101 reg = <0x00 0xa4000000 0x00 0x100000>;
102 no-map;
103 };
104
105 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
106 compatible = "shared-dma-pool";
107 reg = <0x00 0xa4100000 0x00 0xf00000>;
108 no-map;
109 };
110
111 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
112 compatible = "shared-dma-pool";
113 reg = <0x00 0xa5000000 0x00 0x100000>;
114 no-map;
115 };
116
117 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
118 compatible = "shared-dma-pool";
119 reg = <0x00 0xa5100000 0x00 0xf00000>;
120 no-map;
121 };
122
123 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
124 compatible = "shared-dma-pool";
125 reg = <0x00 0xa6000000 0x00 0x100000>;
126 no-map;
127 };
128
129 main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
130 compatible = "shared-dma-pool";
131 reg = <0x00 0xa6100000 0x00 0xf00000>;
132 no-map;
133 };
134
135 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
136 compatible = "shared-dma-pool";
137 reg = <0x00 0xa7000000 0x00 0x100000>;
138 no-map;
139 };
140
141 main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
142 compatible = "shared-dma-pool";
143 reg = <0x00 0xa7100000 0x00 0xf00000>;
144 no-map;
145 };
146
147 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
148 compatible = "shared-dma-pool";
149 reg = <0x00 0xa8000000 0x00 0x100000>;
150 no-map;
151 };
152
153 c71_0_memory_region: c71-memory@a8100000 {
154 compatible = "shared-dma-pool";
155 reg = <0x00 0xa8100000 0x00 0xf00000>;
156 no-map;
157 };
158
159 c71_1_dma_memory_region: c71-dma-memory@a9000000 {
160 compatible = "shared-dma-pool";
161 reg = <0x00 0xa9000000 0x00 0x100000>;
162 no-map;
163 };
164
165 c71_1_memory_region: c71-memory@a9100000 {
166 compatible = "shared-dma-pool";
167 reg = <0x00 0xa9100000 0x00 0xf00000>;
168 no-map;
169 };
170
171 c71_2_dma_memory_region: c71-dma-memory@aa000000 {
172 compatible = "shared-dma-pool";
173 reg = <0x00 0xaa000000 0x00 0x100000>;
174 no-map;
175 };
176
177 c71_2_memory_region: c71-memory@aa100000 {
178 compatible = "shared-dma-pool";
179 reg = <0x00 0xaa100000 0x00 0xf00000>;
180 no-map;
181 };
182
183 c71_3_dma_memory_region: c71-dma-memory@ab000000 {
184 compatible = "shared-dma-pool";
185 reg = <0x00 0xab000000 0x00 0x100000>;
186 no-map;
187 };
188
189 c71_3_memory_region: c71-memory@ab100000 {
190 compatible = "shared-dma-pool";
191 reg = <0x00 0xab100000 0x00 0xf00000>;
192 no-map;
193 };
194 };
195
196 vusb_main: regulator-vusb-main5v0 {
197 /* USB MAIN INPUT 5V DC */
198 compatible = "regulator-fixed";
199 regulator-name = "vusb-main5v0";
200 regulator-min-microvolt = <5000000>;
201 regulator-max-microvolt = <5000000>;
202 regulator-always-on;
203 regulator-boot-on;
204 };
205
206 vsys_5v0: regulator-vsys5v0 {
207 /* Output of LM61460 */
208 compatible = "regulator-fixed";
209 regulator-name = "vsys_5v0";
210 regulator-min-microvolt = <5000000>;
211 regulator-max-microvolt = <5000000>;
212 vin-supply = <&vusb_main>;
213 regulator-always-on;
214 regulator-boot-on;
215 };
216
217 vsys_3v3: regulator-vsys3v3 {
218 /* Output of LM5143 */
219 compatible = "regulator-fixed";
220 regulator-name = "vsys_3v3";
221 regulator-min-microvolt = <3300000>;
222 regulator-max-microvolt = <3300000>;
223 vin-supply = <&vusb_main>;
224 regulator-always-on;
225 regulator-boot-on;
226 };
227
228 vdd_mmc1: regulator-sd {
229 /* Output of TPS22918 */
230 compatible = "regulator-fixed";
231 regulator-name = "vdd_mmc1";
232 regulator-min-microvolt = <3300000>;
233 regulator-max-microvolt = <3300000>;
234 regulator-boot-on;
235 enable-active-high;
236 vin-supply = <&vsys_3v3>;
237 gpio = <&exp1 2 GPIO_ACTIVE_HIGH>;
238 };
239
240 vdd_sd_dv: regulator-tlv71033 {
241 /* Output of TLV71033 */
242 compatible = "regulator-gpio";
243 regulator-name = "tlv71033";
244 pinctrl-names = "default";
245 pinctrl-0 = <&vdd_sd_dv_pins_default>;
246 regulator-min-microvolt = <1800000>;
247 regulator-max-microvolt = <3300000>;
248 regulator-boot-on;
249 vin-supply = <&vsys_5v0>;
250 gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>;
251 states = <1800000 0x0>,
252 <3300000 0x1>;
253 };
254
255 dp0_pwr_3v3: regulator-dp0-pwr {
256 compatible = "regulator-fixed";
257 regulator-name = "dp0-pwr";
258 regulator-min-microvolt = <3300000>;
259 regulator-max-microvolt = <3300000>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&dp_pwr_en_pins_default>;
262 gpio = <&main_gpio0 4 0>; /* DP0_3V3 _EN */
263 enable-active-high;
264 };
265
266 dp0: connector-dp0 {
267 compatible = "dp-connector";
268 label = "DP0";
269 type = "full-size";
270 dp-pwr-supply = <&dp0_pwr_3v3>;
271
272 port {
273 dp0_connector_in: endpoint {
274 remote-endpoint = <&dp0_out>;
275 };
276 };
277 };
278
279 connector-hdmi {
280 compatible = "hdmi-connector";
281 label = "hdmi";
282 type = "a";
283 pinctrl-names = "default";
284 pinctrl-0 = <&hdmi_hpd_pins_default>;
285 ddc-i2c-bus = <&mcu_i2c1>;
286 hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; /* HDMI_HPD */
287
288 port {
289 hdmi_connector_in: endpoint {
290 remote-endpoint = <&tfp410_out>;
291 };
292 };
293 };
294
295 bridge-dvi {
296 compatible = "ti,tfp410";
297 pinctrl-names = "default";
298 pinctrl-0 = <&hdmi_pdn_pins_default>;
299 powerdown-gpios = <&wkup_gpio0 14 GPIO_ACTIVE_LOW>; /* HDMI_PDn */
300 ti,deskew = <0>;
301
302 ports {
303 #address-cells = <1>;
304 #size-cells = <0>;
305
306 port@0 {
307 reg = <0>;
308
309 tfp410_in: endpoint {
310 remote-endpoint = <&dpi1_out0>;
311 pclk-sample = <1>;
312 };
313 };
314
315 port@1 {
316 reg = <1>;
317
318 tfp410_out: endpoint {
319 remote-endpoint = <&hdmi_connector_in>;
320 };
321 };
322 };
323 };
324};
325
326&main_pmx0 {
327 bootph-all;
328 main_uart8_pins_default: main-uart8-default-pins {
329 bootph-all;
330 pinctrl-single,pins = <
331 J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */
332 J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */
333 >;
334 };
335
336 main_i2c0_pins_default: main-i2c0-default-pins {
337 pinctrl-single,pins = <
338 J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */
339 J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */
340 >;
341 };
342
343 main_mmc1_pins_default: main-mmc1-default-pins {
344 bootph-all;
345 pinctrl-single,pins = <
346 J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
347 J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
348 J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */
349 J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */
350 J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */
351 J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */
352 J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */
353 J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */
354 >;
355 };
356
357 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
358 pinctrl-single,pins = <
359 J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */
360 >;
361 };
362
363 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
364 pinctrl-single,pins = <
365 J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */
366 J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */
367 J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */
368 J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */
369 J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */
370 J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */
371 J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */
372 J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */
373 J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */
374 J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */
375 J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */
376 J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */
377 J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */
378 J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */
379 >;
380 };
381
382 dp0_pins_default: dp0-default-pins {
383 pinctrl-single,pins = <
384 J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */
385 >;
386 };
387
388 dp_pwr_en_pins_default: dp-pwr-en-default-pins {
389 pinctrl-single,pins = <
390 J784S4_IOPAD(0x010, PIN_INPUT, 7) /* (AH33) MCAN13_RX.GPIO0_4 */
391 >;
392 };
393
394 dss_vout0_pins_default: dss-vout0-default-pins {
395 pinctrl-single,pins = <
396 J784S4_IOPAD(0x074, PIN_OUTPUT, 2) /* (AC33) MCAN2_TX.VOUT0_DATA0 */
397 J784S4_IOPAD(0x070, PIN_OUTPUT, 2) /* (AH38) MCAN1_RX.VOUT0_DATA1 */
398 J784S4_IOPAD(0x07c, PIN_OUTPUT, 2) /* (AJ38) MCASP0_AXR3.VOUT0_DATA2 */
399 J784S4_IOPAD(0x068, PIN_OUTPUT, 2) /* (AE38) MCAN0_RX.VOUT0_DATA3 */
400 J784S4_IOPAD(0x064, PIN_OUTPUT, 2) /* (AF38) MCAN0_TX.VOUT0_DATA4 */
401 J784S4_IOPAD(0x060, PIN_OUTPUT, 2) /* (AE36) MCASP2_AXR1.VOUT0_DATA5 */
402 J784S4_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AC36) MCASP2_AXR0.VOUT0_DATA6 */
403 J784S4_IOPAD(0x058, PIN_OUTPUT, 2) /* (AE37) MCASP2_AFSX.VOUT0_DATA7 */
404 J784S4_IOPAD(0x054, PIN_OUTPUT, 2) /* (AD37) MCASP2_ACLKX.VOUT0_DATA8 */
405 J784S4_IOPAD(0x050, PIN_OUTPUT, 2) /* (AC37) MCASP1_AXR2.VOUT0_DATA9 */
406 J784S4_IOPAD(0x04c, PIN_OUTPUT, 2) /* (AC32) MCASP1_AXR1.VOUT0_DATA10 */
407 J784S4_IOPAD(0x048, PIN_OUTPUT, 2) /* (AK33) MCASP0_AXR2.VOUT0_DATA11 */
408 J784S4_IOPAD(0x044, PIN_OUTPUT, 2) /* (AG37) MCASP0_AXR1.VOUT0_DATA12 */
409 J784S4_IOPAD(0x040, PIN_OUTPUT, 2) /* (AF37) MCASP0_AXR0.VOUT0_DATA13 */
410 J784S4_IOPAD(0x03c, PIN_OUTPUT, 2) /* (AK38) MCASP0_AFSX.VOUT0_DATA14 */
411 J784S4_IOPAD(0x038, PIN_OUTPUT, 2) /* (AK35) MCASP0_ACLKX.VOUT0_DATA15 */
412 J784S4_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AJ32) EXT_REFCLK1.VOUT0_DATA16 */
413 J784S4_IOPAD(0x030, PIN_OUTPUT, 2) /* (AK37) GPIO0_12.VOUT0_DATA17 */
414 J784S4_IOPAD(0x02c, PIN_OUTPUT, 2) /* (AL32) GPIO0_11.VOUT0_DATA18 */
415 J784S4_IOPAD(0x028, PIN_OUTPUT, 2) /* (AE33) MCAN16_RX.VOUT0_DATA19 */
416 J784S4_IOPAD(0x024, PIN_OUTPUT, 2) /* (AH34) MCAN16_TX.VOUT0_DATA20 */
417 J784S4_IOPAD(0x020, PIN_OUTPUT, 2) /* (AJ35) MCAN15_RX.VOUT0_DATA21 */
418 J784S4_IOPAD(0x01c, PIN_OUTPUT, 2) /* (AG34) MCAN15_TX.VOUT0_DATA22 */
419 J784S4_IOPAD(0x018, PIN_OUTPUT, 2) /* (AK36) MCAN14_RX.VOUT0_DATA23 */
420 J784S4_IOPAD(0x084, PIN_OUTPUT, 2) /* (AG38) MCASP0_AXR5.VOUT0_DE */
421 J784S4_IOPAD(0x080, PIN_OUTPUT, 2) /* (AK34) MCASP0_AXR4.VOUT0_HSYNC */
422 J784S4_IOPAD(0x078, PIN_OUTPUT, 2) /* (AH37) MCAN2_RX.VOUT0_PCLK */
423 J784S4_IOPAD(0x088, PIN_OUTPUT, 2) /* (AF36) MCASP0_AXR6.VOUT0_VSYNC */
424 >;
425 };
426
427 hdmi_hpd_pins_default: hdmi-hpd-default-pins {
428 pinctrl-single,pins = <
429 J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */
430 >;
431 };
432};
433
434&wkup_pmx2 {
435 bootph-all;
436 wkup_uart0_pins_default: wkup-uart0-default-pins {
437 bootph-all;
438 pinctrl-single,pins = <
439 J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */
440 J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */
441 J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */
442 J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */
443 >;
444 };
445
446 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
447 bootph-all;
448 pinctrl-single,pins = <
449 J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */
450 J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
451 >;
452 };
453
454 mcu_uart0_pins_default: mcu-uart0-default-pins {
455 bootph-all;
456 pinctrl-single,pins = <
457 J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */
458 J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */
459 >;
460 };
461
462 mcu_i2c0_pins_default: mcu-i2c0-default-pins {
463 pinctrl-single,pins = <
464 J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */
465 J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */
466 >;
467 };
468
469 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
470 pinctrl-single,pins = <
471 J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
472 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
473 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
474 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
475 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
476 J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
477 J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
478 J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
479 J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
480 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
481 J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
482 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
483 >;
484 };
485
486 mcu_mdio_pins_default: mcu-mdio-default-pins {
487 pinctrl-single,pins = <
488 J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
489 J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
490 >;
491 };
492
493 mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-default-pins {
494 pinctrl-single,pins = <
495 J784S4_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (N34) WKUP_GPIO0_66 */
496 J784S4_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (J34) WKUP_GPIO0_1 */
497 J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */
498 J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (H38) WKUP_GPIO0_0 */
499 J784S4_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (M37) WKUP_GPIO0_56 */
500 J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */
501 J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (K37) WKUP_GPIO0_15 */
502 J784S4_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (J36) WKUP_GPIO0_3 */
503 J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */
504 >;
505 };
506
507 mcu_i2c1_pins_default: mcu-i2c1-default-pins {
508 pinctrl-single,pins = <
509 /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */
510 J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0)
511 /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */
512 J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0)
513 >;
514 };
515
516 hdmi_pdn_pins_default: hdmi-pdn-default-pins {
517 pinctrl-single,pins = <
518 J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */
519 >;
520 };
521};
522
523&wkup_pmx3 {
524 mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-default-pins {
525 pinctrl-single,pins = <
526 J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */
527 >;
528 };
529};
530
531&mailbox0_cluster0 {
532 status = "okay";
533 interrupts = <436>;
534 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
535 ti,mbox-rx = <0 0 0>;
536 ti,mbox-tx = <1 0 0>;
537 };
538
539 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
540 ti,mbox-rx = <2 0 0>;
541 ti,mbox-tx = <3 0 0>;
542 };
543};
544
545&mailbox0_cluster1 {
546 status = "okay";
547 interrupts = <432>;
548 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
549 ti,mbox-rx = <0 0 0>;
550 ti,mbox-tx = <1 0 0>;
551 };
552
553 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
554 ti,mbox-rx = <2 0 0>;
555 ti,mbox-tx = <3 0 0>;
556 };
557};
558
559&mailbox0_cluster2 {
560 status = "okay";
561 interrupts = <428>;
562 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
563 ti,mbox-rx = <0 0 0>;
564 ti,mbox-tx = <1 0 0>;
565 };
566
567 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
568 ti,mbox-rx = <2 0 0>;
569 ti,mbox-tx = <3 0 0>;
570 };
571};
572
573&mailbox0_cluster3 {
574 status = "okay";
575 interrupts = <424>;
576 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
577 ti,mbox-rx = <0 0 0>;
578 ti,mbox-tx = <1 0 0>;
579 };
580
581 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
582 ti,mbox-rx = <2 0 0>;
583 ti,mbox-tx = <3 0 0>;
584 };
585};
586
587&mailbox0_cluster4 {
588 status = "okay";
589 interrupts = <420>;
590 mbox_c71_0: mbox-c71-0 {
591 ti,mbox-rx = <0 0 0>;
592 ti,mbox-tx = <1 0 0>;
593 };
594
595 mbox_c71_1: mbox-c71-1 {
596 ti,mbox-rx = <2 0 0>;
597 ti,mbox-tx = <3 0 0>;
598 };
599};
600
601&mailbox0_cluster5 {
602 status = "okay";
603 interrupts = <416>;
604 mbox_c71_2: mbox-c71-2 {
605 ti,mbox-rx = <0 0 0>;
606 ti,mbox-tx = <1 0 0>;
607 };
608
609 mbox_c71_3: mbox-c71-3 {
610 ti,mbox-rx = <2 0 0>;
611 ti,mbox-tx = <3 0 0>;
612 };
613};
614
615&wkup_uart0 {
616 /* Firmware usage */
617 status = "reserved";
618 pinctrl-names = "default";
619 pinctrl-0 = <&wkup_uart0_pins_default>;
620};
621
622&wkup_i2c0 {
623 bootph-all;
624 status = "okay";
625 pinctrl-names = "default";
626 pinctrl-0 = <&wkup_i2c0_pins_default>;
627 clock-frequency = <400000>;
628
629 eeprom@51 {
630 /* AT24C512C-MAHM-T */
631 compatible = "atmel,24c512";
632 reg = <0x51>;
633 };
634};
635
636&wkup_gpio0 {
637 status = "okay";
638 pinctrl-names = "default";
639 pinctrl-0 = <&mcu_rpi_hdr1_gpio0_pins_default>, <&mcu_rpi_hdr2_gpio0_pins_default>;
640};
641
642&mcu_uart0 {
643 bootph-all;
644 status = "okay";
645 pinctrl-names = "default";
646 pinctrl-0 = <&mcu_uart0_pins_default>;
647};
648
649&mcu_i2c0 {
650 status = "okay";
651 pinctrl-names = "default";
652 pinctrl-0 = <&mcu_i2c0_pins_default>;
653 clock-frequency = <400000>;
654};
655
656&main_uart8 {
657 bootph-all;
658 status = "okay";
659 pinctrl-names = "default";
660 pinctrl-0 = <&main_uart8_pins_default>;
661};
662
663&main_i2c0 {
664 status = "okay";
665 pinctrl-names = "default";
666 pinctrl-0 = <&main_i2c0_pins_default>;
667 clock-frequency = <400000>;
668
669 exp1: gpio@21 {
670 compatible = "ti,tca6416";
671 reg = <0x21>;
672 gpio-controller;
673 #gpio-cells = <2>;
674 gpio-line-names = "BOARDID_EEPROM_WP", "CAN_STB", "GPIO_uSD_PWR_EN",
675 "IO_EXP_MCU_RGMII_RST#", "IO_EXP_PCIe0_4L_PERST#",
676 "IO_EXP_PCIe1_M.2_RTSz", "IO_EXP_PCIe3_M.2_RTSz",
677 "PM_INA_BUS_EN", "ENET1_EXP_PWRDN", "EXP1_ENET_RSTz",
678 "ENET1_I2CMUX_SEL", "PCIe0_CLKREQ#", "PCIe1_M.2_CLKREQ#",
679 "PCIe3_M2_CLKREQ#", "PCIe0_PRSNT2#_1", "PCIe0_PRSNT2#_2";
680 };
681};
682
683&main_sdhci0 {
684 bootph-all;
685 /* eMMC */
686 status = "okay";
687 non-removable;
688 ti,driver-strength-ohm = <50>;
689 disable-wp;
690};
691
692&main_sdhci1 {
693 bootph-all;
694 /* SD card */
695 status = "okay";
696 pinctrl-0 = <&main_mmc1_pins_default>;
697 pinctrl-names = "default";
698 disable-wp;
699 vmmc-supply = <&vdd_mmc1>;
700 vqmmc-supply = <&vdd_sd_dv>;
701};
702
703&main_gpio0 {
704 status = "okay";
705 pinctrl-names = "default";
706 pinctrl-0 = <&rpi_header_gpio0_pins_default>;
707};
708
709&mcu_cpsw {
710 status = "okay";
711 pinctrl-names = "default";
712 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
713};
714
715&davinci_mdio {
716 mcu_phy0: ethernet-phy@0 {
717 reg = <0>;
718 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
719 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
720 ti,min-output-impedance;
721 };
722};
723
724&mcu_cpsw_port1 {
725 status = "okay";
726 phy-mode = "rgmii-rxid";
727 phy-handle = <&mcu_phy0>;
728};
729
730&mcu_r5fss0_core0 {
731 mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
732 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
733 <&mcu_r5fss0_core0_memory_region>;
734};
735
736&mcu_r5fss0_core1 {
737 mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
738 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
739 <&mcu_r5fss0_core1_memory_region>;
740};
741
742&main_r5fss0_core0 {
743 mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
744 memory-region = <&main_r5fss0_core0_dma_memory_region>,
745 <&main_r5fss0_core0_memory_region>;
746};
747
748&main_r5fss0_core1 {
749 mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
750 memory-region = <&main_r5fss0_core1_dma_memory_region>,
751 <&main_r5fss0_core1_memory_region>;
752};
753
754&main_r5fss1_core0 {
755 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
756 memory-region = <&main_r5fss1_core0_dma_memory_region>,
757 <&main_r5fss1_core0_memory_region>;
758};
759
760&main_r5fss1_core1 {
761 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
762 memory-region = <&main_r5fss1_core1_dma_memory_region>,
763 <&main_r5fss1_core1_memory_region>;
764};
765
766&main_r5fss2_core0 {
767 mboxes = <&mailbox0_cluster3>, <&mbox_main_r5fss2_core0>;
768 memory-region = <&main_r5fss2_core0_dma_memory_region>,
769 <&main_r5fss2_core0_memory_region>;
770};
771
772&main_r5fss2_core1 {
773 mboxes = <&mailbox0_cluster3>, <&mbox_main_r5fss2_core1>;
774 memory-region = <&main_r5fss2_core1_dma_memory_region>,
775 <&main_r5fss2_core1_memory_region>;
776};
777
778&c71_0 {
779 status = "okay";
780 mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
781 memory-region = <&c71_0_dma_memory_region>,
782 <&c71_0_memory_region>;
783};
784
785&c71_1 {
786 status = "okay";
787 mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
788 memory-region = <&c71_1_dma_memory_region>,
789 <&c71_1_memory_region>;
790};
791
792&c71_2 {
793 status = "okay";
794 mboxes = <&mailbox0_cluster5>, <&mbox_c71_2>;
795 memory-region = <&c71_2_dma_memory_region>,
796 <&c71_2_memory_region>;
797};
798
799&c71_3 {
800 status = "okay";
801 mboxes = <&mailbox0_cluster5>, <&mbox_c71_3>;
802 memory-region = <&c71_3_dma_memory_region>,
803 <&c71_3_memory_region>;
804};
805
806&wkup_gpio_intr {
807 status = "okay";
808};
809
810&mcu_i2c1 {
811 status = "okay";
812 pinctrl-names = "default";
813 pinctrl-0 = <&mcu_i2c1_pins_default>;
814 clock-frequency = <100000>;
815};
816
817&serdes_refclk {
818 status = "okay";
819 clock-frequency = <100000000>;
820};
821
822&dss {
823 status = "okay";
824 pinctrl-names = "default";
825 pinctrl-0 = <&dss_vout0_pins_default>;
826 assigned-clocks = <&k3_clks 218 2>,
827 <&k3_clks 218 5>,
828 <&k3_clks 218 14>,
829 <&k3_clks 218 18>;
830 assigned-clock-parents = <&k3_clks 218 3>,
831 <&k3_clks 218 7>,
832 <&k3_clks 218 16>,
833 <&k3_clks 218 22>;
834};
835
836&serdes_wiz4 {
837 status = "okay";
838};
839
840&serdes4 {
841 status = "okay";
842 serdes4_dp_link: phy@0 {
843 reg = <0>;
844 cdns,num-lanes = <4>;
845 #phy-cells = <0>;
846 cdns,phy-type = <PHY_TYPE_DP>;
847 resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
848 <&serdes_wiz4 3>, <&serdes_wiz4 4>;
849 };
850};
851
852&mhdp {
853 status = "okay";
854 pinctrl-names = "default";
855 pinctrl-0 = <&dp0_pins_default>;
856 phys = <&serdes4_dp_link>;
857 phy-names = "dpphy";
858};
859
860&dss_ports {
861 #address-cells = <1>;
862 #size-cells = <0>;
863
864 /* DP */
865 port@0 {
866 reg = <0>;
867
868 dpi0_out: endpoint {
869 remote-endpoint = <&dp0_in>;
870 };
871 };
872
873 /* HDMI */
874 port@1 {
875 reg = <1>;
876
877 dpi1_out0: endpoint {
878 remote-endpoint = <&tfp410_in>;
879 };
880 };
881};
882
883&dp0_ports {
884
885 port@0 {
886 reg = <0>;
887
888 dp0_in: endpoint {
889 remote-endpoint = <&dpi0_out>;
890 };
891 };
892
893 port@4 {
894 reg = <4>;
895
896 dp0_out: endpoint {
897 remote-endpoint = <&dp0_connector_in>;
898 };
899 };
900};