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git01.mediatek.com / filogic / uboot / e9748b224336311c79cd6ae0c6f813004392a199 / . / dts / upstream / src / arm64 / freescale / imx93-tqma9352-mba93xxla.dts
blob: 3c5c67ebee5d306e47277439532c55b62d7a1c3c [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2/*
3 * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
5 * Author: Markus Niebel
6 * Author: Alexander Stein
7 */
8/dts-v1/;
9
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/leds/common.h>
12#include <dt-bindings/net/ti-dp83867.h>
13#include <dt-bindings/pwm/pwm.h>
14#include <dt-bindings/usb/pd.h>
15#include "imx93-tqma9352.dtsi"
16
17/{
18 model = "TQ-Systems i.MX93 TQMa93xxLA on MBa93xxLA SBC";
19 compatible = "tq,imx93-tqma9352-mba93xxla",
20 "tq,imx93-tqma9352", "fsl,imx93";
21
22 chosen {
23 stdout-path = &lpuart1;
24 };
25
26 aliases {
27 eeprom0 = &eeprom0;
28 rtc0 = &pcf85063;
29 rtc1 = &bbnsm_rtc;
30 };
31
32 backlight_lvds: backlight {
33 compatible = "pwm-backlight";
34 pwms = <&tpm5 0 5000000 0>;
35 brightness-levels = <0 4 8 16 32 64 128 255>;
36 default-brightness-level = <7>;
37 power-supply = <&reg_12v0>;
38 enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>;
39 status = "disabled";
40 };
41
42 clk_dp: clk-dp {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <26000000>;
46 };
47
48 gpio-keys {
49 compatible = "gpio-keys";
50 autorepeat;
51
52 switch-a {
53 label = "switcha";
54 linux,code = <BTN_0>;
55 gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
56 wakeup-source;
57 };
58
59 switch-b {
60 label = "switchb";
61 linux,code = <BTN_1>;
62 gpios = <&expander0 7 GPIO_ACTIVE_LOW>;
63 wakeup-source;
64 };
65 };
66
67 gpio-leds {
68 compatible = "gpio-leds";
69
70 led-1 {
71 color = <LED_COLOR_ID_GREEN>;
72 function = LED_FUNCTION_STATUS;
73 gpios = <&expander2 6 GPIO_ACTIVE_HIGH>;
74 linux,default-trigger = "default-on";
75 };
76
77 led-2 {
78 color = <LED_COLOR_ID_AMBER>;
79 function = LED_FUNCTION_HEARTBEAT;
80 gpios = <&expander2 7 GPIO_ACTIVE_HIGH>;
81 linux,default-trigger = "heartbeat";
82 };
83 };
84
85 iio-hwmon {
86 compatible = "iio-hwmon";
87 io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>;
88 };
89
90 reg_3v3: regulator-3v3 {
91 compatible = "regulator-fixed";
92 regulator-name = "V_3V3_MB";
93 regulator-min-microvolt = <3300000>;
94 regulator-max-microvolt = <3300000>;
95 };
96
97 reg_3v8: regulator-3v8 {
98 compatible = "regulator-fixed";
99 regulator-name = "V_3V8";
100 regulator-min-microvolt = <3800000>;
101 regulator-max-microvolt = <3800000>;
102 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
103 enable-active-high;
104 /* TODO: this is supply for IOT module */
105 regulator-always-on;
106 };
107
108 reg_5v0: regulator-5v0 {
109 compatible = "regulator-fixed";
110 regulator-name = "V_5V0_MB";
111 regulator-min-microvolt = <5000000>;
112 regulator-max-microvolt = <5000000>;
113 };
114
115 reg_12v0: regulator-12v0 {
116 compatible = "regulator-fixed";
117 regulator-name = "V_12V";
118 regulator-min-microvolt = <12000000>;
119 regulator-max-microvolt = <12000000>;
120 gpio = <&expander1 7 GPIO_ACTIVE_HIGH>;
121 enable-active-high;
122 };
123};
124
125&adc1 {
126 status = "okay";
127};
128
129&eqos {
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_eqos>;
132 phy-mode = "rgmii-id";
133 phy-handle = <&ethphy_eqos>;
134 status = "okay";
135
136 mdio {
137 compatible = "snps,dwmac-mdio";
138 #address-cells = <1>;
139 #size-cells = <0>;
140
141 ethphy_eqos: ethernet-phy@0 {
142 compatible = "ethernet-phy-ieee802.3-c22";
143 reg = <0>;
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_eqos_phy>;
146 interrupt-parent = <&gpio3>;
147 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
148 reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>;
149 reset-assert-us = <500000>;
150 reset-deassert-us = <50000>;
151 enet-phy-lane-no-swap;
152 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
153 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
154 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
155 ti,dp83867-rxctrl-strap-quirk;
156 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
157 };
158 };
159};
160
161&fec {
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_fec>;
164 phy-mode = "rgmii-id";
165 phy-handle = <&ethphy_fec>;
166 fsl,magic-packet;
167 status = "okay";
168
169 mdio {
170 #address-cells = <1>;
171 #size-cells = <0>;
172 clock-frequency = <5000000>;
173
174 ethphy_fec: ethernet-phy@0 {
175 compatible = "ethernet-phy-ieee802.3-c22";
176 reg = <0>;
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_fec_phy>;
179 interrupt-parent = <&gpio3>;
180 interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
181 reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
182 reset-assert-us = <500000>;
183 reset-deassert-us = <50000>;
184 enet-phy-lane-no-swap;
185 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
186 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
187 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
188 ti,dp83867-rxctrl-strap-quirk;
189 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
190 };
191 };
192};
193
194&flexcan1 {
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_flexcan1>;
197 xceiver-supply = <&reg_3v3>;
198 status = "okay";
199};
200
201&flexcan2 {
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_flexcan2>;
204 xceiver-supply = <&reg_3v3>;
205 status = "okay";
206};
207
208&gpio1 {
209 expander-irq-hog {
210 gpio-hog;
211 gpios = <12 GPIO_ACTIVE_LOW>;
212 input;
213 line-name = "PEX_INT#";
214 };
215
216 rtc-irq-hog {
217 gpio-hog;
218 gpios = <14 GPIO_ACTIVE_LOW>;
219 input;
220 line-name = "RTC_EVENT#";
221 };
222};
223
224&gpio3 {
225 ethphy-eqos-irq-hog {
226 gpio-hog;
227 gpios = <26 GPIO_ACTIVE_LOW>;
228 input;
229 line-name = "ENET0_IRQ#";
230 };
231
232 ethphy-fec-irq-hog {
233 gpio-hog;
234 gpios = <27 GPIO_ACTIVE_LOW>;
235 input;
236 line-name = "ENET1_IRQ#";
237 };
238};
239
240&lpi2c3 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 clock-frequency = <400000>;
244 pinctrl-names = "default", "sleep";
245 pinctrl-0 = <&pinctrl_lpi2c3>;
246 pinctrl-1 = <&pinctrl_lpi2c3>;
247 status = "okay";
248
249 temperature-sensor@1c {
250 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
251 reg = <0x1c>;
252 };
253
254 eeprom2: eeprom@54 {
255 compatible = "nxp,se97b", "atmel,24c02";
256 reg = <0x54>;
257 pagesize = <16>;
258 vcc-supply = <&reg_3v3>;
259 };
260
261 expander0: gpio@70 {
262 compatible = "nxp,pca9538";
263 reg = <0x70>;
264 pinctrl-names = "default";
265 pinctrl-0 = <&pinctrl_pexp_irq>;
266 gpio-controller;
267 #gpio-cells = <2>;
268 interrupt-controller;
269 #interrupt-cells = <2>;
270 interrupt-parent = <&gpio1>;
271 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
272 vcc-supply = <&reg_3v3>;
273 gpio-line-names = "3V8_EN", "",
274 "", "IOT_PWRKEY",
275 "IOT_RESET", "IOT_W_DISABLE",
276 "BUTTON_A#", "BUTTON_B#";
277
278 /*
279 * Controls the IOT W_DISABLE pin which is low active
280 * as disable signal but inverted as seen from the CPU.
281 * The output-low states, the signal is
282 * inactive, e.g. not disabled
283 */
284 iot_wdisable_hog: iot-wdisable-hog {
285 gpio-hog;
286 gpios = <5 GPIO_ACTIVE_HIGH>;
287 output-low;
288 line-name = "IOT_W_DISABLE";
289 };
290 };
291
292 expander1: gpio@71 {
293 compatible = "nxp,pca9538";
294 reg = <0x71>;
295 gpio-controller;
296 #gpio-cells = <2>;
297 vcc-supply = <&reg_3v3>;
298 gpio-line-names = "ENET1_RESET#", "ENET2_RESET#",
299 "USB_RESET#", "",
300 "WLAN_PD#", "WLAN_W_DISABLE#",
301 "WLAN_PERST#", "12V_EN";
302
303 /*
304 * Controls the WiFi card PD pin which is low active
305 * as power down signal. The output-low states, the signal
306 * is inactive, e.g. not power down
307 */
308 wlan-pd-hog {
309 gpio-hog;
310 gpios = <4 GPIO_ACTIVE_LOW>;
311 output-low;
312 line-name = "WLAN_PD#";
313 };
314
315 /*
316 * Controls the WiFi card disable pin which is low active
317 * as disable signal. The output-low states, the signal
318 * is inactive, e.g. not disabled
319 */
320 wlan-wdisable-hog {
321 gpio-hog;
322 gpios = <5 GPIO_ACTIVE_LOW>;
323 output-low;
324 line-name = "WLAN_W_DISABLE#";
325 };
326
327 /*
328 * Controls the WiFi card reset pin which is low active
329 * as reset signal. The output-low states, the signal
330 * is inactive, e.g. not in reset
331 */
332 wlan-perst-hog {
333 gpio-hog;
334 gpios = <6 GPIO_ACTIVE_LOW>;
335 output-low;
336 line-name = "WLAN_PERST#";
337 };
338 };
339
340 expander2: gpio@72 {
341 compatible = "nxp,pca9538";
342 reg = <0x72>;
343 gpio-controller;
344 #gpio-cells = <2>;
345 vcc-supply = <&reg_3v3>;
346 gpio-line-names = "LCD_RESET#", "LCD_PWR_EN",
347 "LCD_BL_EN", "DP_EN",
348 "MIPI_CSI_EN", "MIPI_CSI_RST#",
349 "USER_LED1", "USER_LED2";
350 };
351};
352
353&lpi2c5 {
354 #address-cells = <1>;
355 #size-cells = <0>;
356 clock-frequency = <400000>;
357 pinctrl-names = "default", "sleep";
358 pinctrl-0 = <&pinctrl_lpi2c5>;
359 pinctrl-1 = <&pinctrl_lpi2c5>;
360 status = "okay";
361
362 dp_bridge: dp-bridge@f {
363 compatible = "toshiba,tc9595", "toshiba,tc358767";
364 reg = <0x0f>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_tc9595>;
367 clock-names = "ref";
368 clocks = <&clk_dp>;
369 reset-gpios = <&expander2 3 GPIO_ACTIVE_HIGH>;
370 interrupt-parent = <&gpio4>;
371 interrupts = <29 IRQ_TYPE_EDGE_RISING>;
372 toshiba,hpd-pin = <0>;
373 status = "disabled";
374
375 ports {
376 #address-cells = <1>;
377 #size-cells = <0>;
378
379 port@0 {
380 reg = <0>;
381
382 dp_dsi_in: endpoint {
383 data-lanes = <1 2 3 4>;
384 };
385 };
386 };
387 };
388};
389
390&lpuart1 {
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_uart1>;
393 status = "okay";
394};
395
396&lpuart2 {
397 pinctrl-names = "default";
398 pinctrl-0 = <&pinctrl_uart2>;
399 linux,rs485-enabled-at-boot-time;
400 status = "okay";
401};
402
403/* disabled per default, console for M33 */
404&lpuart3 {
405 pinctrl-names = "default";
406 pinctrl-0 = <&pinctrl_uart3>;
407 status = "disabled";
408};
409
410&lpuart6 {
411 pinctrl-names = "default";
412 pinctrl-0 = <&pinctrl_uart6>;
413 status = "okay";
414};
415
416&lpuart8 {
417 pinctrl-names = "default";
418 pinctrl-0 = <&pinctrl_uart8>;
419 status = "okay";
420};
421
422&pcf85063 {
423 /* RTC_EVENT# is connected on MBa93xxLA */
424 pinctrl-names = "default";
425 pinctrl-0 = <&pinctrl_pcf85063>;
426 interrupt-parent = <&gpio1>;
427 interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
428};
429
430&tpm5 {
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_tpm5>;
433};
434
435&usdhc2 {
436 pinctrl-names = "default", "state_100mhz", "state_200mhz";
437 pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
438 pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
439 pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
440 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
441 vmmc-supply = <&reg_usdhc2_vmmc>;
442 bus-width = <4>;
443 no-sdio;
444 no-mmc;
445 disable-wp;
446 status = "okay";
447};
448
449&iomuxc {
450 pinctrl_eqos: eqosgrp {
451 fsl,pins = <
452 /* PD | FSEL_2 | DSE X4 */
453 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e
454 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000051e
455 /* PD | FSEL_2 | DSE X6 */
456 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
457 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
458 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
459 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
460 /* PD | FSEL_3 | DSE X6 */
461 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
462 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
463 /* PD | FSEL_2 | DSE X4 */
464 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e
465 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e
466 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e
467 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e
468 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e
469 /* PD | FSEL_3 | DSE X3 */
470 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
471 >;
472 };
473
474 pinctrl_eqos_phy: eqosphygrp {
475 fsl,pins = <
476 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1306
477 >;
478 };
479
480 pinctrl_fec: fecgrp {
481 fsl,pins = <
482 /* PD | FSEL_2 | DSE X4 */
483 MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e
484 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000051e
485 /* PD | FSEL_2 | DSE X6 */
486 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
487 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
488 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
489 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
490 /* PD | FSEL_3 | DSE X6 */
491 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
492 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
493 /* PD | FSEL_2 | DSE X4 */
494 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x51e
495 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x51e
496 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x51e
497 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x51e
498 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x51e
499 /* PD | FSEL_3 | DSE X3 */
500 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
501 >;
502 };
503
504 pinctrl_fec_phy: fecphygrp {
505 fsl,pins = <
506 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x1306
507 >;
508 };
509
510 pinctrl_flexcan1: flexcan1grp {
511 fsl,pins = <
512 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
513 MX93_PAD_PDM_CLK__CAN1_TX 0x139e
514 >;
515 };
516
517 pinctrl_flexcan2: flexcan2grp {
518 fsl,pins = <
519 MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
520 MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
521 >;
522 };
523
524 pinctrl_lpi2c3: lpi2c3grp {
525 fsl,pins = <
526 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
527 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
528 >;
529 };
530
531 pinctrl_lpi2c5: lpi2c5grp {
532 fsl,pins = <
533 MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e
534 MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e
535 >;
536 };
537
538 pinctrl_pcf85063: pcf85063grp {
539 fsl,pins = <
540 MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x1306
541 >;
542 };
543
544 pinctrl_pexp_irq: pexpirqgrp {
545 fsl,pins = <
546 MX93_PAD_SAI1_TXC__GPIO1_IO12 0x1306
547 >;
548 };
549
550 pinctrl_tc9595: tc9595-grp {
551 fsl,pins = <
552 /* DP_IRQ */
553 MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x1306
554 >;
555 };
556
557 pinctrl_tpm5: tpm5grp {
558 fsl,pins = <
559 MX93_PAD_GPIO_IO06__TPM5_CH0 0x57e
560 >;
561 };
562
563 pinctrl_typec: typecgrp {
564 fsl,pins = <
565 MX93_PAD_I2C2_SCL__GPIO1_IO02 0x1306
566 >;
567 };
568
569 pinctrl_uart1: uart1grp {
570 fsl,pins = <
571 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
572 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
573 >;
574 };
575
576 pinctrl_uart2: uart2grp {
577 fsl,pins = <
578 MX93_PAD_UART2_TXD__LPUART2_TX 0x31e
579 MX93_PAD_UART2_RXD__LPUART2_RX 0x31e
580 MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x51e
581 >;
582 };
583
584 pinctrl_uart3: uart3grp {
585 fsl,pins = <
586 MX93_PAD_GPIO_IO14__LPUART3_TX 0x31e
587 MX93_PAD_GPIO_IO15__LPUART3_RX 0x31e
588 >;
589 };
590
591 pinctrl_uart6: uart6grp {
592 fsl,pins = <
593 MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e
594 MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e
595 >;
596 };
597
598 pinctrl_uart8: uart8grp {
599 fsl,pins = <
600 MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e
601 MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e
602 >;
603 };
604
605 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
606 fsl,pins = <
607 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
608 >;
609 };
610
611 pinctrl_usdhc2_hs: usdhc2hsgrp {
612 fsl,pins = <
613 /* HYS | PD | PU | FSEL_3 | DSE X5 */
614 MX93_PAD_SD2_CLK__USDHC2_CLK 0x17be
615 /* HYS | PD | PU | FSEL_3 | DSE X4 */
616 MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
617 /* HYS | PD | PU | FSEL_3 | DSE X3 */
618 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
619 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
620 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
621 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
622 /* PD | PU | FSEL_2 | DSE X3 */
623 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e
624 >;
625 };
626
627 pinctrl_usdhc2_uhs: usdhc2uhsgrp {
628 fsl,pins = <
629 /* HYS | PD | PU | FSEL_3 | DSE X6 */
630 MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe
631 /* HYS | PD | PU | FSEL_3 | DSE X4 */
632 MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
633 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e
634 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e
635 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
636 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
637 /* PD | PU | FSEL_2 | DSE X3 */
638 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e
639 >;
640 };
641};