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git01.mediatek.com / filogic / uboot / e9748b224336311c79cd6ae0c6f813004392a199 / . / dts / upstream / Bindings / usb / qcom,dwc3.yaml
blob: 915c8205623b3abf98a43c9ab851e2bdb32c36f7 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SuperSpeed DWC3 USB SoC controller
8
9maintainers:
10 - Wesley Cheng <quic_wcheng@quicinc.com>
11
12properties:
13 compatible:
14 items:
15 - enum:
16 - qcom,ipq4019-dwc3
17 - qcom,ipq5018-dwc3
18 - qcom,ipq5332-dwc3
19 - qcom,ipq6018-dwc3
20 - qcom,ipq8064-dwc3
21 - qcom,ipq8074-dwc3
22 - qcom,ipq9574-dwc3
23 - qcom,msm8953-dwc3
24 - qcom,msm8994-dwc3
25 - qcom,msm8996-dwc3
26 - qcom,msm8998-dwc3
27 - qcom,qcm2290-dwc3
28 - qcom,qcs404-dwc3
29 - qcom,sa8775p-dwc3
30 - qcom,sc7180-dwc3
31 - qcom,sc7280-dwc3
32 - qcom,sc8280xp-dwc3
33 - qcom,sdm660-dwc3
34 - qcom,sdm670-dwc3
35 - qcom,sdm845-dwc3
36 - qcom,sdx55-dwc3
37 - qcom,sdx65-dwc3
38 - qcom,sdx75-dwc3
39 - qcom,sm4250-dwc3
40 - qcom,sm6115-dwc3
41 - qcom,sm6125-dwc3
42 - qcom,sm6350-dwc3
43 - qcom,sm6375-dwc3
44 - qcom,sm8150-dwc3
45 - qcom,sm8250-dwc3
46 - qcom,sm8350-dwc3
47 - qcom,sm8450-dwc3
48 - qcom,sm8550-dwc3
49 - const: qcom,dwc3
50
51 reg:
52 description: Offset and length of register set for QSCRATCH wrapper
53 maxItems: 1
54
55 "#address-cells":
56 enum: [ 1, 2 ]
57
58 "#size-cells":
59 enum: [ 1, 2 ]
60
61 ranges: true
62
63 power-domains:
64 description: specifies a phandle to PM domain provider node
65 maxItems: 1
66
67 required-opps:
68 maxItems: 1
69
70 clocks:
71 description: |
72 Several clocks are used, depending on the variant. Typical ones are::
73 - cfg_noc:: System Config NOC clock.
74 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
75 60MHz for HS operation.
76 - iface:: System bus AXI clock.
77 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low
78 power mode (U3).
79 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host
80 mode. Its frequency should be 19.2MHz.
81 minItems: 1
82 maxItems: 9
83
84 clock-names:
85 minItems: 1
86 maxItems: 9
87
88 resets:
89 maxItems: 1
90
91 interconnects:
92 maxItems: 2
93
94 interconnect-names:
95 items:
96 - const: usb-ddr
97 - const: apps-usb
98
99 interrupts:
100 minItems: 1
101 maxItems: 4
102
103 interrupt-names:
104 minItems: 1
105 maxItems: 4
106
107 qcom,select-utmi-as-pipe-clk:
108 description:
109 If present, disable USB3 pipe_clk requirement.
110 Used when dwc3 operates without SSPHY and only
111 HS/FS/LS modes are supported.
112 type: boolean
113
114 wakeup-source: true
115
116# Required child node:
117
118patternProperties:
119 "^usb@[0-9a-f]+$":
120 $ref: snps,dwc3.yaml#
121 unevaluatedProperties: false
122
123 properties:
124 wakeup-source: false
125
126required:
127 - compatible
128 - reg
129 - "#address-cells"
130 - "#size-cells"
131 - ranges
132 - clocks
133 - clock-names
134 - interrupts
135 - interrupt-names
136
137allOf:
138 - if:
139 properties:
140 compatible:
141 contains:
142 enum:
143 - qcom,ipq4019-dwc3
144 then:
145 properties:
146 clocks:
147 maxItems: 3
148 clock-names:
149 items:
150 - const: core
151 - const: sleep
152 - const: mock_utmi
153
154 - if:
155 properties:
156 compatible:
157 contains:
158 enum:
159 - qcom,ipq8064-dwc3
160 then:
161 properties:
162 clocks:
163 items:
164 - description: Master/Core clock, has to be >= 125 MHz
165 for SS operation and >= 60MHz for HS operation.
166 clock-names:
167 items:
168 - const: core
169
170 - if:
171 properties:
172 compatible:
173 contains:
174 enum:
175 - qcom,ipq9574-dwc3
176 - qcom,msm8953-dwc3
177 - qcom,msm8996-dwc3
178 - qcom,msm8998-dwc3
179 - qcom,sa8775p-dwc3
180 - qcom,sc7180-dwc3
181 - qcom,sc7280-dwc3
182 - qcom,sdm670-dwc3
183 - qcom,sdm845-dwc3
184 - qcom,sdx55-dwc3
185 - qcom,sdx65-dwc3
186 - qcom,sdx75-dwc3
187 - qcom,sm6350-dwc3
188 then:
189 properties:
190 clocks:
191 maxItems: 5
192 clock-names:
193 items:
194 - const: cfg_noc
195 - const: core
196 - const: iface
197 - const: sleep
198 - const: mock_utmi
199
200 - if:
201 properties:
202 compatible:
203 contains:
204 enum:
205 - qcom,ipq6018-dwc3
206 then:
207 properties:
208 clocks:
209 minItems: 3
210 maxItems: 4
211 clock-names:
212 oneOf:
213 - items:
214 - const: core
215 - const: sleep
216 - const: mock_utmi
217 - items:
218 - const: cfg_noc
219 - const: core
220 - const: sleep
221 - const: mock_utmi
222
223 - if:
224 properties:
225 compatible:
226 contains:
227 enum:
228 - qcom,ipq8074-dwc3
229 then:
230 properties:
231 clocks:
232 maxItems: 4
233 clock-names:
234 items:
235 - const: cfg_noc
236 - const: core
237 - const: sleep
238 - const: mock_utmi
239
240 - if:
241 properties:
242 compatible:
243 contains:
244 enum:
245 - qcom,ipq5018-dwc3
246 - qcom,ipq5332-dwc3
247 - qcom,msm8994-dwc3
248 - qcom,qcs404-dwc3
249 then:
250 properties:
251 clocks:
252 maxItems: 4
253 clock-names:
254 items:
255 - const: core
256 - const: iface
257 - const: sleep
258 - const: mock_utmi
259
260 - if:
261 properties:
262 compatible:
263 contains:
264 enum:
265 - qcom,sc8280xp-dwc3
266 then:
267 properties:
268 clocks:
269 maxItems: 9
270 clock-names:
271 items:
272 - const: cfg_noc
273 - const: core
274 - const: iface
275 - const: sleep
276 - const: mock_utmi
277 - const: noc_aggr
278 - const: noc_aggr_north
279 - const: noc_aggr_south
280 - const: noc_sys
281
282 - if:
283 properties:
284 compatible:
285 contains:
286 enum:
287 - qcom,sdm660-dwc3
288 then:
289 properties:
290 clocks:
291 minItems: 5
292 maxItems: 6
293 clock-names:
294 oneOf:
295 - items:
296 - const: cfg_noc
297 - const: core
298 - const: iface
299 - const: sleep
300 - const: mock_utmi
301 - const: bus
302 - items:
303 - const: cfg_noc
304 - const: core
305 - const: sleep
306 - const: mock_utmi
307 - const: bus
308
309 - if:
310 properties:
311 compatible:
312 contains:
313 enum:
314 - qcom,qcm2290-dwc3
315 - qcom,sm6115-dwc3
316 - qcom,sm6125-dwc3
317 - qcom,sm8150-dwc3
318 - qcom,sm8250-dwc3
319 - qcom,sm8450-dwc3
320 - qcom,sm8550-dwc3
321 then:
322 properties:
323 clocks:
324 minItems: 6
325 clock-names:
326 items:
327 - const: cfg_noc
328 - const: core
329 - const: iface
330 - const: sleep
331 - const: mock_utmi
332 - const: xo
333
334 - if:
335 properties:
336 compatible:
337 contains:
338 enum:
339 - qcom,sm8350-dwc3
340 then:
341 properties:
342 clocks:
343 minItems: 5
344 maxItems: 6
345 clock-names:
346 minItems: 5
347 items:
348 - const: cfg_noc
349 - const: core
350 - const: iface
351 - const: sleep
352 - const: mock_utmi
353 - const: xo
354
355 - if:
356 properties:
357 compatible:
358 contains:
359 enum:
360 - qcom,ipq4019-dwc3
361 - qcom,ipq6018-dwc3
362 - qcom,ipq8064-dwc3
363 - qcom,ipq8074-dwc3
364 - qcom,msm8994-dwc3
365 - qcom,qcs404-dwc3
366 - qcom,sc7180-dwc3
367 - qcom,sdm670-dwc3
368 - qcom,sdm845-dwc3
369 - qcom,sdx55-dwc3
370 - qcom,sdx65-dwc3
371 - qcom,sdx75-dwc3
372 - qcom,sm4250-dwc3
373 - qcom,sm6125-dwc3
374 - qcom,sm6350-dwc3
375 - qcom,sm8150-dwc3
376 - qcom,sm8250-dwc3
377 - qcom,sm8350-dwc3
378 - qcom,sm8450-dwc3
379 - qcom,sm8550-dwc3
380 then:
381 properties:
382 interrupts:
383 items:
384 - description: The interrupt that is asserted
385 when a wakeup event is received on USB2 bus.
386 - description: The interrupt that is asserted
387 when a wakeup event is received on USB3 bus.
388 - description: Wakeup event on DM line.
389 - description: Wakeup event on DP line.
390 interrupt-names:
391 items:
392 - const: hs_phy_irq
393 - const: ss_phy_irq
394 - const: dm_hs_phy_irq
395 - const: dp_hs_phy_irq
396
397 - if:
398 properties:
399 compatible:
400 contains:
401 enum:
402 - qcom,msm8953-dwc3
403 - qcom,msm8996-dwc3
404 - qcom,msm8998-dwc3
405 - qcom,sm6115-dwc3
406 then:
407 properties:
408 interrupts:
409 maxItems: 2
410 interrupt-names:
411 items:
412 - const: hs_phy_irq
413 - const: ss_phy_irq
414
415 - if:
416 properties:
417 compatible:
418 contains:
419 enum:
420 - qcom,ipq5018-dwc3
421 - qcom,ipq5332-dwc3
422 - qcom,sdm660-dwc3
423 then:
424 properties:
425 interrupts:
426 minItems: 1
427 maxItems: 2
428 interrupt-names:
429 minItems: 1
430 items:
431 - const: hs_phy_irq
432 - const: ss_phy_irq
433
434 - if:
435 properties:
436 compatible:
437 contains:
438 enum:
439 - qcom,sc7280-dwc3
440 then:
441 properties:
442 interrupts:
443 minItems: 3
444 maxItems: 4
445 interrupt-names:
446 minItems: 3
447 items:
448 - const: hs_phy_irq
449 - const: dp_hs_phy_irq
450 - const: dm_hs_phy_irq
451 - const: ss_phy_irq
452
453 - if:
454 properties:
455 compatible:
456 contains:
457 enum:
458 - qcom,sc8280xp-dwc3
459 then:
460 properties:
461 interrupts:
462 maxItems: 4
463 interrupt-names:
464 items:
465 - const: pwr_event
466 - const: dp_hs_phy_irq
467 - const: dm_hs_phy_irq
468 - const: ss_phy_irq
469
470 - if:
471 properties:
472 compatible:
473 contains:
474 enum:
475 - qcom,sa8775p-dwc3
476 then:
477 properties:
478 interrupts:
479 minItems: 3
480 maxItems: 4
481 interrupt-names:
482 minItems: 3
483 items:
484 - const: pwr_event
485 - const: dp_hs_phy_irq
486 - const: dm_hs_phy_irq
487 - const: ss_phy_irq
488
489additionalProperties: false
490
491examples:
492 - |
493 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
494 #include <dt-bindings/interrupt-controller/arm-gic.h>
495 #include <dt-bindings/interrupt-controller/irq.h>
496 soc {
497 #address-cells = <2>;
498 #size-cells = <2>;
499
500 usb@a6f8800 {
501 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
502 reg = <0 0x0a6f8800 0 0x400>;
503
504 #address-cells = <2>;
505 #size-cells = <2>;
506 ranges;
507 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
508 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
509 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
510 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
511 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
512 clock-names = "cfg_noc",
513 "core",
514 "iface",
515 "sleep",
516 "mock_utmi";
517
518 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
519 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
520 assigned-clock-rates = <19200000>, <150000000>;
521
522 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
525 <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>;
526 interrupt-names = "hs_phy_irq", "ss_phy_irq",
527 "dm_hs_phy_irq", "dp_hs_phy_irq";
528
529 power-domains = <&gcc USB30_PRIM_GDSC>;
530
531 resets = <&gcc GCC_USB30_PRIM_BCR>;
532
533 usb@a600000 {
534 compatible = "snps,dwc3";
535 reg = <0 0x0a600000 0 0xcd00>;
536 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
537 iommus = <&apps_smmu 0x740 0>;
538 snps,dis_u2_susphy_quirk;
539 snps,dis_enblslpm_quirk;
540 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
541 phy-names = "usb2-phy", "usb3-phy";
542 };
543 };
544 };