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Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: (GPL-2.0 OR MIT)
2# Copyright 2019 Linaro Ltd.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: QCOM SoC Temperature Sensor (TSENS)
9
10maintainers:
11 - Amit Kucheria <amitk@kernel.org>
12
13description: |
14 QCOM SoCs have TSENS IP to allow temperature measurement. There are currently
15 three distinct major versions of the IP that is supported by a single driver.
16 The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures
17 everything before v1 when there was no versioning information.
18
19properties:
20 compatible:
21 oneOf:
22 - description: msm8960 TSENS based
23 items:
24 - enum:
25 - qcom,ipq8064-tsens
26 - qcom,msm8960-tsens
27
28 - description: v0.1 of TSENS
29 items:
30 - enum:
31 - qcom,mdm9607-tsens
32 - qcom,msm8226-tsens
33 - qcom,msm8909-tsens
34 - qcom,msm8916-tsens
35 - qcom,msm8939-tsens
36 - qcom,msm8974-tsens
37 - const: qcom,tsens-v0_1
38
39 - description: v1 of TSENS
40 items:
41 - enum:
42 - qcom,msm8956-tsens
43 - qcom,msm8976-tsens
44 - qcom,qcs404-tsens
45 - const: qcom,tsens-v1
46
47 - description: v2 of TSENS
48 items:
49 - enum:
50 - qcom,msm8953-tsens
51 - qcom,msm8996-tsens
52 - qcom,msm8998-tsens
53 - qcom,qcm2290-tsens
54 - qcom,sa8775p-tsens
55 - qcom,sc7180-tsens
56 - qcom,sc7280-tsens
57 - qcom,sc8180x-tsens
58 - qcom,sc8280xp-tsens
59 - qcom,sdm630-tsens
60 - qcom,sdm845-tsens
61 - qcom,sm6115-tsens
62 - qcom,sm6350-tsens
63 - qcom,sm6375-tsens
64 - qcom,sm8150-tsens
65 - qcom,sm8250-tsens
66 - qcom,sm8350-tsens
67 - qcom,sm8450-tsens
68 - qcom,sm8550-tsens
69 - const: qcom,tsens-v2
70
71 - description: v2 of TSENS with combined interrupt
72 enum:
73 - qcom,ipq8074-tsens
74
75 - description: v2 of TSENS with combined interrupt
76 items:
77 - enum:
78 - qcom,ipq9574-tsens
79 - const: qcom,ipq8074-tsens
80
81 reg:
82 items:
83 - description: TM registers
84 - description: SROT registers
85
86 interrupts:
87 minItems: 1
88 maxItems: 2
89
90 interrupt-names:
91 minItems: 1
92 maxItems: 2
93
94 nvmem-cells:
95 oneOf:
96 - minItems: 1
97 maxItems: 2
98 description:
99 Reference to an nvmem node for the calibration data
100 - minItems: 5
101 maxItems: 35
102 description: |
103 Reference to nvmem cells for the calibration mode, two calibration
104 bases and two cells per each sensor
105 # special case for msm8974 / apq8084
106 - maxItems: 51
107 description: |
108 Reference to nvmem cells for the calibration mode, two calibration
109 bases and two cells per each sensor, main and backup copies, plus use_backup cell
110
111 nvmem-cell-names:
112 oneOf:
113 - minItems: 1
114 items:
115 - const: calib
116 - enum:
117 - calib_backup
118 - calib_sel
119 - minItems: 5
120 items:
121 - const: mode
122 - const: base1
123 - const: base2
124 - pattern: '^s[0-9]+_p1$'
125 - pattern: '^s[0-9]+_p2$'
126 - pattern: '^s[0-9]+_p1$'
127 - pattern: '^s[0-9]+_p2$'
128 - pattern: '^s[0-9]+_p1$'
129 - pattern: '^s[0-9]+_p2$'
130 - pattern: '^s[0-9]+_p1$'
131 - pattern: '^s[0-9]+_p2$'
132 - pattern: '^s[0-9]+_p1$'
133 - pattern: '^s[0-9]+_p2$'
134 - pattern: '^s[0-9]+_p1$'
135 - pattern: '^s[0-9]+_p2$'
136 - pattern: '^s[0-9]+_p1$'
137 - pattern: '^s[0-9]+_p2$'
138 - pattern: '^s[0-9]+_p1$'
139 - pattern: '^s[0-9]+_p2$'
140 - pattern: '^s[0-9]+_p1$'
141 - pattern: '^s[0-9]+_p2$'
142 - pattern: '^s[0-9]+_p1$'
143 - pattern: '^s[0-9]+_p2$'
144 - pattern: '^s[0-9]+_p1$'
145 - pattern: '^s[0-9]+_p2$'
146 - pattern: '^s[0-9]+_p1$'
147 - pattern: '^s[0-9]+_p2$'
148 - pattern: '^s[0-9]+_p1$'
149 - pattern: '^s[0-9]+_p2$'
150 - pattern: '^s[0-9]+_p1$'
151 - pattern: '^s[0-9]+_p2$'
152 - pattern: '^s[0-9]+_p1$'
153 - pattern: '^s[0-9]+_p2$'
154 - pattern: '^s[0-9]+_p1$'
155 - pattern: '^s[0-9]+_p2$'
156 # special case for msm8974 / apq8084
157 - items:
158 - const: mode
159 - const: base1
160 - const: base2
161 - const: use_backup
162 - const: mode_backup
163 - const: base1_backup
164 - const: base2_backup
165 - const: s0_p1
166 - const: s0_p2
167 - const: s1_p1
168 - const: s1_p2
169 - const: s2_p1
170 - const: s2_p2
171 - const: s3_p1
172 - const: s3_p2
173 - const: s4_p1
174 - const: s4_p2
175 - const: s5_p1
176 - const: s5_p2
177 - const: s6_p1
178 - const: s6_p2
179 - const: s7_p1
180 - const: s7_p2
181 - const: s8_p1
182 - const: s8_p2
183 - const: s9_p1
184 - const: s9_p2
185 - const: s10_p1
186 - const: s10_p2
187 - const: s0_p1_backup
188 - const: s0_p2_backup
189 - const: s1_p1_backup
190 - const: s1_p2_backup
191 - const: s2_p1_backup
192 - const: s2_p2_backup
193 - const: s3_p1_backup
194 - const: s3_p2_backup
195 - const: s4_p1_backup
196 - const: s4_p2_backup
197 - const: s5_p1_backup
198 - const: s5_p2_backup
199 - const: s6_p1_backup
200 - const: s6_p2_backup
201 - const: s7_p1_backup
202 - const: s7_p2_backup
203 - const: s8_p1_backup
204 - const: s8_p2_backup
205 - const: s9_p1_backup
206 - const: s9_p2_backup
207 - const: s10_p1_backup
208 - const: s10_p2_backup
209
210 "#qcom,sensors":
211 description:
212 Number of sensors enabled on this platform
213 $ref: /schemas/types.yaml#/definitions/uint32
214 minimum: 1
215 maximum: 16
216
217 "#thermal-sensor-cells":
218 const: 1
219 description:
220 Number of cells required to uniquely identify the thermal sensors. Since
221 we have multiple sensors this is set to 1
222
223required:
224 - compatible
225 - interrupts
226 - interrupt-names
227 - "#thermal-sensor-cells"
228 - "#qcom,sensors"
229
230allOf:
231 - if:
232 properties:
233 compatible:
234 contains:
235 enum:
236 - qcom,ipq8064-tsens
237 - qcom,msm8960-tsens
238 - qcom,tsens-v0_1
239 - qcom,tsens-v1
240 then:
241 properties:
242 interrupts:
243 items:
244 - description: Combined interrupt if upper or lower threshold crossed
245 interrupt-names:
246 items:
247 - const: uplow
248
249 - if:
250 properties:
251 compatible:
252 contains:
253 const: qcom,tsens-v2
254 then:
255 properties:
256 interrupts:
257 items:
258 - description: Combined interrupt if upper or lower threshold crossed
259 - description: Interrupt if critical threshold crossed
260 interrupt-names:
261 items:
262 - const: uplow
263 - const: critical
264
265 - if:
266 properties:
267 compatible:
268 contains:
269 enum:
270 - qcom,ipq8074-tsens
271 then:
272 properties:
273 interrupts:
274 items:
275 - description: Combined interrupt if upper, lower or critical thresholds crossed
276 interrupt-names:
277 items:
278 - const: combined
279
280 - if:
281 properties:
282 compatible:
283 contains:
284 enum:
285 - qcom,ipq8074-tsens
286 - qcom,tsens-v0_1
287 - qcom,tsens-v1
288 - qcom,tsens-v2
289
290 then:
291 required:
292 - reg
293
294additionalProperties: false
295
296examples:
297 - |
298 #include <dt-bindings/interrupt-controller/arm-gic.h>
299 // Example msm9860 based SoC (ipq8064):
300 gcc: clock-controller {
301
302 /* ... */
303
304 tsens: thermal-sensor {
305 compatible = "qcom,ipq8064-tsens";
306
307 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
308 nvmem-cell-names = "calib", "calib_backup";
309 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
310 interrupt-names = "uplow";
311
312 #qcom,sensors = <11>;
313 #thermal-sensor-cells = <1>;
314 };
315 };
316
317 - |
318 #include <dt-bindings/interrupt-controller/arm-gic.h>
319 // Example 1 (new calbiration data: for pre v1 IP):
320 thermal-sensor@4a9000 {
321 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
322 reg = <0x4a9000 0x1000>, /* TM */
323 <0x4a8000 0x1000>; /* SROT */
324
325 nvmem-cells = <&tsens_mode>,
326 <&tsens_base1>, <&tsens_base2>,
327 <&tsens_s0_p1>, <&tsens_s0_p2>,
328 <&tsens_s1_p1>, <&tsens_s1_p2>,
329 <&tsens_s2_p1>, <&tsens_s2_p2>,
330 <&tsens_s4_p1>, <&tsens_s4_p2>,
331 <&tsens_s5_p1>, <&tsens_s5_p2>;
332 nvmem-cell-names = "mode",
333 "base1", "base2",
334 "s0_p1", "s0_p2",
335 "s1_p1", "s1_p2",
336 "s2_p1", "s2_p2",
337 "s4_p1", "s4_p2",
338 "s5_p1", "s5_p2";
339
340 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
341 interrupt-names = "uplow";
342
343 #qcom,sensors = <5>;
344 #thermal-sensor-cells = <1>;
345 };
346
347 - |
348 #include <dt-bindings/interrupt-controller/arm-gic.h>
349 // Example 1 (legacy: for pre v1 IP):
350 tsens1: thermal-sensor@4a9000 {
351 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
352 reg = <0x4a9000 0x1000>, /* TM */
353 <0x4a8000 0x1000>; /* SROT */
354
355 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
356 nvmem-cell-names = "calib", "calib_sel";
357
358 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
359 interrupt-names = "uplow";
360
361 #qcom,sensors = <5>;
362 #thermal-sensor-cells = <1>;
363 };
364
365 - |
366 #include <dt-bindings/interrupt-controller/arm-gic.h>
367 // Example 2 (for any platform containing v1 of the TSENS IP):
368 tsens2: thermal-sensor@4a9000 {
369 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
370 reg = <0x004a9000 0x1000>, /* TM */
371 <0x004a8000 0x1000>; /* SROT */
372
373 nvmem-cells = <&tsens_caldata>;
374 nvmem-cell-names = "calib";
375
376 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
377 interrupt-names = "uplow";
378
379 #qcom,sensors = <10>;
380 #thermal-sensor-cells = <1>;
381 };
382
383 - |
384 #include <dt-bindings/interrupt-controller/arm-gic.h>
385 // Example 3 (for any platform containing v2 of the TSENS IP):
386 tsens3: thermal-sensor@c263000 {
387 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
388 reg = <0xc263000 0x1ff>,
389 <0xc222000 0x1ff>;
390
391 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
393 interrupt-names = "uplow", "critical";
394
395 #qcom,sensors = <13>;
396 #thermal-sensor-cells = <1>;
397 };
398
399 - |
400 #include <dt-bindings/interrupt-controller/arm-gic.h>
401 // Example 4 (for any IPQ8074 based SoC-s):
402 tsens4: thermal-sensor@4a9000 {
403 compatible = "qcom,ipq8074-tsens";
404 reg = <0x4a9000 0x1000>,
405 <0x4a8000 0x1000>;
406
407 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
408 interrupt-names = "combined";
409
410 #qcom,sensors = <16>;
411 #thermal-sensor-cells = <1>;
412 };
413...