| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Mediatek display merge |
| 8 | |
| 9 | maintainers: |
| 10 | - Chun-Kuang Hu <chunkuang.hu@kernel.org> |
| 11 | - Philipp Zabel <p.zabel@pengutronix.de> |
| 12 | |
| 13 | description: | |
| 14 | Mediatek display merge, namely MERGE, is used to merge two slice-per-line |
| 15 | inputs into one side-by-side output. |
| 16 | MERGE device node must be siblings to the central MMSYS_CONFIG node. |
| 17 | For a description of the MMSYS_CONFIG binding, see |
| 18 | Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml |
| 19 | for details. |
| 20 | |
| 21 | properties: |
| 22 | compatible: |
| 23 | oneOf: |
| 24 | - enum: |
| 25 | - mediatek,mt8173-disp-merge |
| 26 | - mediatek,mt8195-disp-merge |
| 27 | - items: |
| 28 | - const: mediatek,mt6795-disp-merge |
| 29 | - const: mediatek,mt8173-disp-merge |
| 30 | |
| 31 | reg: |
| 32 | maxItems: 1 |
| 33 | |
| 34 | interrupts: |
| 35 | maxItems: 1 |
| 36 | |
| 37 | power-domains: |
| 38 | description: A phandle and PM domain specifier as defined by bindings of |
| 39 | the power controller specified by phandle. See |
| 40 | Documentation/devicetree/bindings/power/power-domain.yaml for details. |
| 41 | |
| 42 | clocks: |
| 43 | minItems: 1 |
| 44 | maxItems: 2 |
| 45 | |
| 46 | clock-names: |
| 47 | oneOf: |
| 48 | - items: |
| 49 | - const: merge |
| 50 | - items: |
| 51 | - const: merge |
| 52 | - const: merge_async |
| 53 | |
| 54 | mediatek,merge-fifo-en: |
| 55 | description: |
| 56 | The setting of merge fifo is mainly provided for the display latency |
| 57 | buffer to ensure that the back-end panel display data will not be |
| 58 | underrun, a little more data is needed in the fifo. |
| 59 | According to the merge fifo settings, when the water level is detected |
| 60 | to be insufficient, it will trigger RDMA sending ultra and preulra |
| 61 | command to SMI to speed up the data rate. |
| 62 | type: boolean |
| 63 | |
| 64 | mediatek,merge-mute: |
| 65 | description: Support mute function. Mute the content of merge output. |
| 66 | type: boolean |
| 67 | |
| 68 | mediatek,gce-client-reg: |
| 69 | description: The register of client driver can be configured by gce with |
| 70 | 4 arguments defined in this property, such as phandle of gce, subsys id, |
| 71 | register offset and size. Each GCE subsys id is mapping to a client |
| 72 | defined in the header include/dt-bindings/gce/<chip>-gce.h. |
| 73 | $ref: /schemas/types.yaml#/definitions/phandle-array |
| 74 | maxItems: 1 |
| 75 | |
| 76 | resets: |
| 77 | description: reset controller |
| 78 | See Documentation/devicetree/bindings/reset/reset.txt for details. |
| 79 | maxItems: 1 |
| 80 | |
| 81 | required: |
| 82 | - compatible |
| 83 | - reg |
| 84 | - power-domains |
| 85 | - clocks |
| 86 | |
| 87 | additionalProperties: false |
| 88 | |
| 89 | examples: |
| 90 | - | |
| 91 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 92 | #include <dt-bindings/clock/mt8173-clk.h> |
| 93 | #include <dt-bindings/power/mt8173-power.h> |
| 94 | |
| 95 | soc { |
| 96 | #address-cells = <2>; |
| 97 | #size-cells = <2>; |
| 98 | |
| 99 | merge@14017000 { |
| 100 | compatible = "mediatek,mt8173-disp-merge"; |
| 101 | reg = <0 0x14017000 0 0x1000>; |
| 102 | power-domains = <&spm MT8173_POWER_DOMAIN_MM>; |
| 103 | clocks = <&mmsys CLK_MM_DISP_MERGE>; |
| 104 | clock-names = "merge"; |
| 105 | }; |
| 106 | }; |