| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Calxeda Highbank L2 cache ECC |
| 8 | |
| 9 | description: | |
| 10 | Binding for the Calxeda Highbank L2 cache controller ECC device. |
| 11 | This does not cover the actual L2 cache controller control registers, |
| 12 | but just the error reporting functionality. |
| 13 | |
| 14 | maintainers: |
| 15 | - Andre Przywara <andre.przywara@arm.com> |
| 16 | |
| 17 | properties: |
| 18 | compatible: |
| 19 | const: "calxeda,hb-sregs-l2-ecc" |
| 20 | |
| 21 | reg: |
| 22 | maxItems: 1 |
| 23 | |
| 24 | interrupts: |
| 25 | items: |
| 26 | - description: single bit error interrupt |
| 27 | - description: double bit error interrupt |
| 28 | |
| 29 | required: |
| 30 | - compatible |
| 31 | - reg |
| 32 | - interrupts |
| 33 | |
| 34 | additionalProperties: false |
| 35 | |
| 36 | examples: |
| 37 | - | |
| 38 | sregs@fff3c200 { |
| 39 | compatible = "calxeda,hb-sregs-l2-ecc"; |
| 40 | reg = <0xfff3c200 0x100>; |
| 41 | interrupts = <0 71 4>, <0 72 4>; |
| 42 | }; |