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Bo Shen58645902014-11-10 15:24:02 +08001/*
2 * Copyright (C) 2014 Atmel
3 * Bo Shen <voice.shen@atmel.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <asm/io.h>
10#include <asm/arch/at91_common.h>
Bo Shen58645902014-11-10 15:24:02 +080011#include <asm/arch/at91_rstc.h>
Bo Shen05f95632014-12-15 13:24:38 +080012#include <asm/arch/atmel_mpddrc.h>
Bo Shen58645902014-11-10 15:24:02 +080013#include <asm/arch/gpio.h>
14#include <asm/arch/clk.h>
15#include <asm/arch/sama5d3_smc.h>
16#include <asm/arch/sama5d4.h>
Bo Shenad042262015-01-08 15:20:12 +080017#include <atmel_hlcdc.h>
Bo Shen58645902014-11-10 15:24:02 +080018#include <lcd.h>
Bo Shen58645902014-11-10 15:24:02 +080019#include <nand.h>
Wu, Josh1d55b502015-02-04 11:03:32 +080020#include <version.h>
Bo Shen58645902014-11-10 15:24:02 +080021
22DECLARE_GLOBAL_DATA_PTR;
23
Bo Shen58645902014-11-10 15:24:02 +080024#ifdef CONFIG_NAND_ATMEL
25static void sama5d4ek_nand_hw_init(void)
26{
27 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
28
29 at91_periph_clk_enable(ATMEL_ID_SMC);
30
31 /* Configure SMC CS3 for NAND */
32 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
33 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
34 &smc->cs[3].setup);
35 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
36 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
37 &smc->cs[3].pulse);
38 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
39 &smc->cs[3].cycle);
40 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
41 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
42 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)|
43 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
44 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
45 AT91_SMC_MODE_EXNW_DISABLE |
46 AT91_SMC_MODE_DBW_8 |
47 AT91_SMC_MODE_TDF_CYCLE(3),
48 &smc->cs[3].mode);
49
Wenyou Yang4a92a3e2017-03-23 12:44:36 +080050 at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
51 at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
52 at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
53 at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
54 at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
55 at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
56 at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
57 at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
58 at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
59 at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
60 at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
61 at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
62 at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
63 at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
Bo Shen58645902014-11-10 15:24:02 +080064}
65#endif
66
67#ifdef CONFIG_CMD_USB
68static void sama5d4ek_usb_hw_init(void)
69{
70 at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
71 at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
72 at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
73}
74#endif
75
76#ifdef CONFIG_LCD
77vidinfo_t panel_info = {
78 .vl_col = 800,
79 .vl_row = 480,
80 .vl_clk = 33260000,
Bo Shen58645902014-11-10 15:24:02 +080081 .vl_bpix = LCD_BPP,
82 .vl_tft = 1,
83 .vl_hsync_len = 5,
84 .vl_left_margin = 128,
85 .vl_right_margin = 0,
86 .vl_vsync_len = 5,
87 .vl_upper_margin = 23,
88 .vl_lower_margin = 22,
89 .mmio = ATMEL_BASE_LCDC,
90};
91
92/* No power up/down pin for the LCD pannel */
93void lcd_enable(void) { /* Empty! */ }
94void lcd_disable(void) { /* Empty! */ }
95
96unsigned int has_lcdc(void)
97{
98 return 1;
99}
100
101static void sama5d4ek_lcd_hw_init(void)
102{
Wenyou Yang4a92a3e2017-03-23 12:44:36 +0800103 at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
104 at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
105 at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
106 at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
107 at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
108 at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
Bo Shen58645902014-11-10 15:24:02 +0800109
Wenyou Yang4a92a3e2017-03-23 12:44:36 +0800110 at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
111 at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
112 at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
113 at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
114 at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
115 at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
Bo Shen58645902014-11-10 15:24:02 +0800116
Wenyou Yang4a92a3e2017-03-23 12:44:36 +0800117 at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
118 at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
119 at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
120 at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
121 at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
122 at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
Bo Shen58645902014-11-10 15:24:02 +0800123
Wenyou Yang4a92a3e2017-03-23 12:44:36 +0800124 at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
125 at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
126 at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
127 at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
128 at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
129 at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
Bo Shen58645902014-11-10 15:24:02 +0800130
131 /* Enable clock */
132 at91_periph_clk_enable(ATMEL_ID_LCDC);
133}
134
135#ifdef CONFIG_LCD_INFO
136void lcd_show_board_info(void)
137{
138 ulong dram_size, nand_size;
139 int i;
140 char temp[32];
141
Wu, Josh1d55b502015-02-04 11:03:32 +0800142 lcd_printf("%s\n", U_BOOT_VERSION);
Bo Shen58645902014-11-10 15:24:02 +0800143 lcd_printf("2014 ATMEL Corp\n");
144 lcd_printf("at91@atmel.com\n");
145 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
146 strmhz(temp, get_cpu_clk_rate()));
147
148 dram_size = 0;
149 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
150 dram_size += gd->bd->bi_dram[i].size;
151
152 nand_size = 0;
153#ifdef CONFIG_NAND_ATMEL
154 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
Scott Wood2c1b7e12016-05-30 13:57:55 -0500155 nand_size += nand_info[i]->size;
Bo Shen58645902014-11-10 15:24:02 +0800156#endif
157 lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
158 dram_size >> 20, nand_size >> 20);
159}
160#endif /* CONFIG_LCD_INFO */
161
162#endif /* CONFIG_LCD */
163
Bo Shen58645902014-11-10 15:24:02 +0800164static void sama5d4ek_serial3_hw_init(void)
165{
Wenyou Yang4a92a3e2017-03-23 12:44:36 +0800166 at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
167 at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
Bo Shen58645902014-11-10 15:24:02 +0800168
169 /* Enable clock */
170 at91_periph_clk_enable(ATMEL_ID_USART3);
171}
172
173int board_early_init_f(void)
174{
Bo Shen58645902014-11-10 15:24:02 +0800175 sama5d4ek_serial3_hw_init();
176
177 return 0;
178}
179
180int board_init(void)
181{
182 /* adress of boot parameters */
183 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
184
Bo Shen58645902014-11-10 15:24:02 +0800185#ifdef CONFIG_NAND_ATMEL
186 sama5d4ek_nand_hw_init();
187#endif
Bo Shen58645902014-11-10 15:24:02 +0800188#ifdef CONFIG_LCD
189 sama5d4ek_lcd_hw_init();
190#endif
191#ifdef CONFIG_CMD_USB
192 sama5d4ek_usb_hw_init();
193#endif
194
195 return 0;
196}
197
198int dram_init(void)
199{
200 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
201 CONFIG_SYS_SDRAM_SIZE);
202 return 0;
203}
204
Bo Shen05f95632014-12-15 13:24:38 +0800205/* SPL */
206#ifdef CONFIG_SPL_BUILD
207void spl_board_init(void)
208{
Wenyou Yange95e3332017-04-13 10:31:20 +0800209#if CONFIG_SYS_USE_NANDFLASH
Bo Shen05f95632014-12-15 13:24:38 +0800210 sama5d4ek_nand_hw_init();
Bo Shen05f95632014-12-15 13:24:38 +0800211#endif
212}
213
Wenyou Yangaa0a58d2016-02-01 18:12:15 +0800214static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
Bo Shen05f95632014-12-15 13:24:38 +0800215{
216 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
217
218 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
219 ATMEL_MPDDRC_CR_NR_ROW_14 |
220 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
221 ATMEL_MPDDRC_CR_NB_8BANKS |
222 ATMEL_MPDDRC_CR_NDQS_DISABLED |
223 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
224 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
225
226 ddr2->rtr = 0x2b0;
227
228 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
229 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
230 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
231 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
232 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
233 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
234 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
235 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
236
237 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
238 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
239 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
240 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
241
242 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
243 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
244 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
245 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
246 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
247}
248
249void mem_init(void)
250{
Wenyou Yangaa0a58d2016-02-01 18:12:15 +0800251 struct atmel_mpddrc_config ddr2;
Bo Shen05f95632014-12-15 13:24:38 +0800252
253 ddr2_conf(&ddr2);
254
Wenyou Yang78f89762016-02-03 10:16:50 +0800255 /* Enable MPDDR clock */
Bo Shen05f95632014-12-15 13:24:38 +0800256 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
Wenyou Yang78f89762016-02-03 10:16:50 +0800257 at91_system_clk_enable(AT91_PMC_DDR);
Bo Shen05f95632014-12-15 13:24:38 +0800258
259 /* DDRAM2 Controller initialize */
Erik van Luijk59d780a2015-08-13 15:43:18 +0200260 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
Bo Shen05f95632014-12-15 13:24:38 +0800261}
262
263void at91_pmc_init(void)
264{
Bo Shen05f95632014-12-15 13:24:38 +0800265 u32 tmp;
266
267 tmp = AT91_PMC_PLLAR_29 |
268 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
269 AT91_PMC_PLLXR_MUL(87) |
270 AT91_PMC_PLLXR_DIV(1);
271 at91_plla_init(tmp);
272
Wenyou Yang5265b1e2016-02-02 12:46:14 +0800273 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
Bo Shen05f95632014-12-15 13:24:38 +0800274
275 tmp = AT91_PMC_MCKR_H32MXDIV |
276 AT91_PMC_MCKR_PLLADIV_2 |
277 AT91_PMC_MCKR_MDIV_3 |
278 AT91_PMC_MCKR_CSS_PLLA;
279 at91_mck_init(tmp);
280}
281#endif