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git01.mediatek.com / filogic / uboot / e904f17f9764426b6d2e821bd6981e8e48df1a4d / . / arch / arm / mach-exynos / mmu-arm64.c
blob: fdaacc70c9bd14c5a3567b48cfa0913a9ec250f3 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Thomas Abrahamd23cb312016-04-23 22:18:13 +0530[diff] [blame]2/*
3 * Copyright (C) 2016 Samsung Electronics
4 * Thomas Abraham <thomas.ab@samsung.com>
Thomas Abrahamd23cb312016-04-23 22:18:13 +0530[diff] [blame]5 */
6
Thomas Abrahamd23cb312016-04-23 22:18:13 +0530[diff] [blame]7#include <asm/armv8/mmu.h>
Sam Protsenko4d718732024-01-10 21:09:07 -0600[diff] [blame]8#include <linux/sizes.h>
Thomas Abrahamd23cb312016-04-23 22:18:13 +0530[diff] [blame]9
Simon Glasse365c842023-02-05 15:39:51 -0700[diff] [blame]10#if IS_ENABLED(CONFIG_EXYNOS7420)
Minkyu Kang9478e802021-11-04 16:13:17 +0900[diff] [blame]11
Thomas Abrahamd23cb312016-04-23 22:18:13 +0530[diff] [blame]12static struct mm_region exynos7420_mem_map[] = {
13 {
York Sunc7104e52016-06-24 16:46:22 -0700[diff] [blame]14 .virt = 0x10000000UL,
15 .phys = 0x10000000UL,
Thomas Abrahamd23cb312016-04-23 22:18:13 +0530[diff] [blame]16 .size = 0x10000000UL,
17 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
18 PTE_BLOCK_NON_SHARE |
19 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
20 }, {
York Sunc7104e52016-06-24 16:46:22 -0700[diff] [blame]21 .virt = 0x40000000UL,
22 .phys = 0x40000000UL,
Thomas Abrahamd23cb312016-04-23 22:18:13 +0530[diff] [blame]23 .size = 0x80000000UL,
24 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
25 PTE_BLOCK_INNER_SHARE,
26 }, {
27 /* List terminator */
Thomas Abrahamd23cb312016-04-23 22:18:13 +0530[diff] [blame]28 },
29};
30
31struct mm_region *mem_map = exynos7420_mem_map;
Dzmitry Sankouski0061b6f2021-10-17 13:45:41 +0300[diff] [blame]32
Minkyu Kang9478e802021-11-04 16:13:17 +0900[diff] [blame]33#elif CONFIG_IS_ENABLED(EXYNOS7870)
34
Dzmitry Sankouski0061b6f2021-10-17 13:45:41 +0300[diff] [blame]35static struct mm_region exynos7870_mem_map[] = {
36 {
37 .virt = 0x10000000UL,
38 .phys = 0x10000000UL,
39 .size = 0x10000000UL,
40 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
41 PTE_BLOCK_NON_SHARE |
42 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
43 },
44 {
45 .virt = 0x40000000UL,
46 .phys = 0x40000000UL,
47 .size = 0x3E400000UL,
48 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
49 PTE_BLOCK_INNER_SHARE,
50 },
51 {
52 .virt = 0x80000000UL,
53 .phys = 0x80000000UL,
54 .size = 0x40000000UL,
55 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
56 PTE_BLOCK_INNER_SHARE,
57 },
58
59 {
60 /* List terminator */
61 },
62};
63
64struct mm_region *mem_map = exynos7870_mem_map;
Minkyu Kang9478e802021-11-04 16:13:17 +0900[diff] [blame]65
66#elif CONFIG_IS_ENABLED(EXYNOS7880)
Dzmitry Sankouski0061b6f2021-10-17 13:45:41 +0300[diff] [blame]67
Dzmitry Sankouski0061b6f2021-10-17 13:45:41 +0300[diff] [blame]68static struct mm_region exynos7880_mem_map[] = {
69 {
70 .virt = 0x10000000UL,
71 .phys = 0x10000000UL,
72 .size = 0x10000000UL,
73 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
74 PTE_BLOCK_NON_SHARE |
75 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
76 },
77 {
78 .virt = 0x40000000UL,
79 .phys = 0x40000000UL,
80 .size = 0x3E400000UL,
81 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
82 PTE_BLOCK_INNER_SHARE,
83 },
84 {
85 .virt = 0x80000000UL,
86 .phys = 0x80000000UL,
87 .size = 0x80000000UL,
88 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
89 PTE_BLOCK_INNER_SHARE,
90 },
91
92 {
93 /* List terminator */
94 },
95};
96
97struct mm_region *mem_map = exynos7880_mem_map;
Sam Protsenko4d718732024-01-10 21:09:07 -0600[diff] [blame]98
99#elif IS_ENABLED(CONFIG_EXYNOS850)
100
101static struct mm_region exynos850_mem_map[] = {
102 {
Sam Protsenkoa8152562024-05-25 16:53:30 -0500[diff] [blame]103 /* iRAM */
104 .virt = 0x02000000UL,
105 .phys = 0x02000000UL,
106 .size = SZ_2M,
107 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
108 PTE_BLOCK_NON_SHARE |
109 PTE_BLOCK_PXN | PTE_BLOCK_UXN
110 }, {
Sam Protsenko4d718732024-01-10 21:09:07 -0600[diff] [blame]111 /* Peripheral block */
112 .virt = 0x10000000UL,
113 .phys = 0x10000000UL,
114 .size = SZ_256M,
115 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
116 PTE_BLOCK_NON_SHARE |
117 PTE_BLOCK_PXN | PTE_BLOCK_UXN
118 }, {
119 /* DDR, 32-bit area */
120 .virt = 0x80000000UL,
121 .phys = 0x80000000UL,
122 .size = SZ_2G,
123 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
124 PTE_BLOCK_INNER_SHARE
125 }, {
126 /* DDR, 64-bit area */
127 .virt = 0x880000000UL,
128 .phys = 0x880000000UL,
129 .size = SZ_2G,
130 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
131 PTE_BLOCK_INNER_SHARE
132 }, {
133 /* List terminator */
134 }
135};
136
137struct mm_region *mem_map = exynos850_mem_map;
138
Dzmitry Sankouski0061b6f2021-10-17 13:45:41 +0300[diff] [blame]139#endif