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git01.mediatek.com / filogic / uboot / e8f8d6705a6ea64ecf7efd26f2b621b2094b1af4 / . / arch / arm / dts / stih407-pinctrl.dtsi
blob: f27ae21f676dfd81af250f51fecb145968e972a6 [file] [log] [blame]
Patrice Chotardcdf6b572017-02-21 13:37:11 +0100[diff] [blame]1/*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "st-pincfg.h"
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11/ {
12
13 aliases {
14 /* 0-5: PIO_SBC */
15 gpio0 = &pio0;
16 gpio1 = &pio1;
17 gpio2 = &pio2;
18 gpio3 = &pio3;
19 gpio4 = &pio4;
20 gpio5 = &pio5;
21 /* 10-19: PIO_FRONT0 */
22 gpio6 = &pio10;
23 gpio7 = &pio11;
24 gpio8 = &pio12;
25 gpio9 = &pio13;
26 gpio10 = &pio14;
27 gpio11 = &pio15;
28 gpio12 = &pio16;
29 gpio13 = &pio17;
30 gpio14 = &pio18;
31 gpio15 = &pio19;
32 /* 20: PIO_FRONT1 */
33 gpio16 = &pio20;
34 /* 30-35: PIO_REAR */
35 gpio17 = &pio30;
36 gpio18 = &pio31;
37 gpio19 = &pio32;
38 gpio20 = &pio33;
39 gpio21 = &pio34;
40 gpio22 = &pio35;
41 /* 40-42: PIO_FLASH */
42 gpio23 = &pio40;
43 gpio24 = &pio41;
44 gpio25 = &pio42;
45 };
46
47 soc {
48 pin-controller-sbc {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 compatible = "st,stih407-sbc-pinctrl";
52 st,syscfg = <&syscfg_sbc>;
53 reg = <0x0961f080 0x4>;
54 reg-names = "irqmux";
55 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
56 interrupt-names = "irqmux";
57 ranges = <0 0x09610000 0x6000>;
58
59 pio0: gpio@09610000 {
60 gpio-controller;
61 #gpio-cells = <2>;
62 interrupt-controller;
63 #interrupt-cells = <2>;
64 reg = <0x0 0x100>;
65 st,bank-name = "PIO0";
66 };
67 pio1: gpio@09611000 {
68 gpio-controller;
69 #gpio-cells = <2>;
70 interrupt-controller;
71 #interrupt-cells = <2>;
72 reg = <0x1000 0x100>;
73 st,bank-name = "PIO1";
74 };
75 pio2: gpio@09612000 {
76 gpio-controller;
77 #gpio-cells = <2>;
78 interrupt-controller;
79 #interrupt-cells = <2>;
80 reg = <0x2000 0x100>;
81 st,bank-name = "PIO2";
82 };
83 pio3: gpio@09613000 {
84 gpio-controller;
85 #gpio-cells = <2>;
86 interrupt-controller;
87 #interrupt-cells = <2>;
88 reg = <0x3000 0x100>;
89 st,bank-name = "PIO3";
90 };
91 pio4: gpio@09614000 {
92 gpio-controller;
93 #gpio-cells = <2>;
94 interrupt-controller;
95 #interrupt-cells = <2>;
96 reg = <0x4000 0x100>;
97 st,bank-name = "PIO4";
98 };
99
100 pio5: gpio@09615000 {
101 gpio-controller;
102 #gpio-cells = <2>;
103 interrupt-controller;
104 #interrupt-cells = <2>;
105 reg = <0x5000 0x100>;
106 st,bank-name = "PIO5";
107 st,retime-pin-mask = <0x3f>;
108 };
109
110 cec0 {
111 pinctrl_cec0_default: cec0-default {
112 st,pins {
113 hdmi_cec = <&pio2 4 ALT1 BIDIR>;
114 };
115 };
116 };
117
118 rc {
119 pinctrl_ir: ir0 {
120 st,pins {
121 ir = <&pio4 0 ALT2 IN>;
122 };
123 };
124
125 pinctrl_uhf: uhf0 {
126 st,pins {
127 ir = <&pio4 1 ALT2 IN>;
128 };
129 };
130
131 pinctrl_tx: tx0 {
132 st,pins {
133 tx = <&pio4 2 ALT2 OUT>;
134 };
135 };
136
137 pinctrl_tx_od: tx_od0 {
138 st,pins {
139 tx_od = <&pio4 3 ALT2 OUT>;
140 };
141 };
142 };
143
144 /* SBC_ASC0 - UART10 */
145 sbc_serial0 {
146 pinctrl_sbc_serial0: sbc_serial0-0 {
147 st,pins {
148 tx = <&pio3 4 ALT1 OUT>;
149 rx = <&pio3 5 ALT1 IN>;
150 };
151 };
152 };
153 /* SBC_ASC1 - UART11 */
154 sbc_serial1 {
155 pinctrl_sbc_serial1: sbc_serial1-0 {
156 st,pins {
157 tx = <&pio2 6 ALT3 OUT>;
158 rx = <&pio2 7 ALT3 IN>;
159 };
160 };
161 };
162
163 i2c10 {
164 pinctrl_i2c10_default: i2c10-default {
165 st,pins {
166 sda = <&pio4 6 ALT1 BIDIR>;
167 scl = <&pio4 5 ALT1 BIDIR>;
168 };
169 };
170 };
171
172 i2c11 {
173 pinctrl_i2c11_default: i2c11-default {
174 st,pins {
175 sda = <&pio5 1 ALT1 BIDIR>;
176 scl = <&pio5 0 ALT1 BIDIR>;
177 };
178 };
179 };
180
181 keyscan {
182 pinctrl_keyscan: keyscan {
183 st,pins {
184 keyin0 = <&pio4 0 ALT6 IN>;
185 keyin1 = <&pio4 5 ALT4 IN>;
186 keyin2 = <&pio0 4 ALT2 IN>;
187 keyin3 = <&pio2 6 ALT2 IN>;
188
189 keyout0 = <&pio4 6 ALT4 OUT>;
190 keyout1 = <&pio1 7 ALT2 OUT>;
191 keyout2 = <&pio0 6 ALT2 OUT>;
192 keyout3 = <&pio2 7 ALT2 OUT>;
193 };
194 };
195 };
196
197 gmac1 {
198 /*
199 * Almost all the boards based on STiH407 SoC have an embedded
200 * switch where the mdio/mdc have been used for managing the SMI
201 * iface via I2C. For this reason these lines can be allocated
202 * by using dedicated configuration (in case of there will be a
203 * standard PHY transceiver on-board).
204 */
205 pinctrl_rgmii1: rgmii1-0 {
206 st,pins {
207
208 txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>;
209 txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>;
210 txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>;
211 txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>;
212 txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
213 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
214 rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
215 rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
216 rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
217 rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
218 rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>;
219 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
220 clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
221 phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>;
222 };
223 };
224
225 pinctrl_rgmii1_mdio: rgmii1-mdio {
226 st,pins {
227 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
228 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
229 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
230 };
231 };
232
233 pinctrl_rgmii1_mdio_1: rgmii1-mdio-1 {
234 st,pins {
235 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
236 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
237 };
238 };
239
240 pinctrl_mii1: mii1 {
241 st,pins {
242 txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
243 txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
244 txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
245 txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
246 txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
247 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
248 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
249 col = <&pio0 7 ALT1 IN BYPASS 1000>;
250
251 mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
252 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
253 crs = <&pio1 2 ALT1 IN BYPASS 1000>;
254 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
255 rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
256 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
257 rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
258 rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
259
260 rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
261 rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
262 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
263 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
264 };
265 };
266
267 pinctrl_rmii1: rmii1-0 {
268 st,pins {
269 txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
270 txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
271 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
272 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
273 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
274 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
275 rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>;
276 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>;
277 rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>;
278 rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
279 };
280 };
281
282 pinctrl_rmii1_phyclk: rmii1_phyclk {
283 st,pins {
284 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
285 };
286 };
287
288 pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext {
289 st,pins {
290 phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>;
291 };
292 };
293 };
294
295 pwm1 {
296 pinctrl_pwm1_chan0_default: pwm1-0-default {
297 st,pins {
298 pwm-out = <&pio3 0 ALT1 OUT>;
299 pwm-capturein = <&pio3 2 ALT1 IN>;
300 };
301 };
302 pinctrl_pwm1_chan1_default: pwm1-1-default {
303 st,pins {
304 pwm-capturein = <&pio4 3 ALT1 IN>;
305 pwm-out = <&pio4 4 ALT1 OUT>;
306 };
307 };
308 pinctrl_pwm1_chan2_default: pwm1-2-default {
309 st,pins {
310 pwm-out = <&pio4 6 ALT3 OUT>;
311 };
312 };
313 pinctrl_pwm1_chan3_default: pwm1-3-default {
314 st,pins {
315 pwm-out = <&pio4 7 ALT3 OUT>;
316 };
317 };
318 };
319
320 spi10 {
321 pinctrl_spi10_default: spi10-4w-alt1-0 {
322 st,pins {
323 mtsr = <&pio4 6 ALT1 OUT>;
324 mrst = <&pio4 7 ALT1 IN>;
325 scl = <&pio4 5 ALT1 OUT>;
326 };
327 };
328
329 pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 {
330 st,pins {
331 mtsr = <&pio4 6 ALT1 BIDIR_PU>;
332 scl = <&pio4 5 ALT1 OUT>;
333 };
334 };
335 };
336
337 spi11 {
338 pinctrl_spi11_default: spi11-4w-alt2-0 {
339 st,pins {
340 mtsr = <&pio3 1 ALT2 OUT>;
341 mrst = <&pio3 0 ALT2 IN>;
342 scl = <&pio3 2 ALT2 OUT>;
343 };
344 };
345
346 pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 {
347 st,pins {
348 mtsr = <&pio3 1 ALT2 BIDIR_PU>;
349 scl = <&pio3 2 ALT2 OUT>;
350 };
351 };
352 };
353
354 spi12 {
355 pinctrl_spi12_default: spi12-4w-alt2-0 {
356 st,pins {
357 mtsr = <&pio3 6 ALT2 OUT>;
358 mrst = <&pio3 4 ALT2 IN>;
359 scl = <&pio3 7 ALT2 OUT>;
360 };
361 };
362
363 pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 {
364 st,pins {
365 mtsr = <&pio3 6 ALT2 BIDIR_PU>;
366 scl = <&pio3 7 ALT2 OUT>;
367 };
368 };
369 };
370 };
371
372 pin-controller-front0 {
373 #address-cells = <1>;
374 #size-cells = <1>;
375 compatible = "st,stih407-front-pinctrl";
376 st,syscfg = <&syscfg_front>;
377 reg = <0x0920f080 0x4>;
378 reg-names = "irqmux";
379 interrupts = <GIC_SPI 189 IRQ_TYPE_NONE>;
380 interrupt-names = "irqmux";
381 ranges = <0 0x09200000 0x10000>;
382
383 pio10: pio@09200000 {
384 gpio-controller;
385 #gpio-cells = <2>;
386 interrupt-controller;
387 #interrupt-cells = <2>;
388 reg = <0x0 0x100>;
389 st,bank-name = "PIO10";
390 };
391 pio11: pio@09201000 {
392 gpio-controller;
393 #gpio-cells = <2>;
394 interrupt-controller;
395 #interrupt-cells = <2>;
396 reg = <0x1000 0x100>;
397 st,bank-name = "PIO11";
398 };
399 pio12: pio@09202000 {
400 gpio-controller;
401 #gpio-cells = <2>;
402 interrupt-controller;
403 #interrupt-cells = <2>;
404 reg = <0x2000 0x100>;
405 st,bank-name = "PIO12";
406 };
407 pio13: pio@09203000 {
408 gpio-controller;
409 #gpio-cells = <2>;
410 interrupt-controller;
411 #interrupt-cells = <2>;
412 reg = <0x3000 0x100>;
413 st,bank-name = "PIO13";
414 };
415 pio14: pio@09204000 {
416 gpio-controller;
417 #gpio-cells = <2>;
418 interrupt-controller;
419 #interrupt-cells = <2>;
420 reg = <0x4000 0x100>;
421 st,bank-name = "PIO14";
422 };
423 pio15: pio@09205000 {
424 gpio-controller;
425 #gpio-cells = <2>;
426 interrupt-controller;
427 #interrupt-cells = <2>;
428 reg = <0x5000 0x100>;
429 st,bank-name = "PIO15";
430 };
431 pio16: pio@09206000 {
432 gpio-controller;
433 #gpio-cells = <2>;
434 interrupt-controller;
435 #interrupt-cells = <2>;
436 reg = <0x6000 0x100>;
437 st,bank-name = "PIO16";
438 };
439 pio17: pio@09207000 {
440 gpio-controller;
441 #gpio-cells = <2>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
444 reg = <0x7000 0x100>;
445 st,bank-name = "PIO17";
446 };
447 pio18: pio@09208000 {
448 gpio-controller;
449 #gpio-cells = <2>;
450 interrupt-controller;
451 #interrupt-cells = <2>;
452 reg = <0x8000 0x100>;
453 st,bank-name = "PIO18";
454 };
455 pio19: pio@09209000 {
456 gpio-controller;
457 #gpio-cells = <2>;
458 interrupt-controller;
459 #interrupt-cells = <2>;
460 reg = <0x9000 0x100>;
461 st,bank-name = "PIO19";
462 };
463
464 /* Comms */
465 serial0 {
466 pinctrl_serial0: serial0-0 {
467 st,pins {
468 tx = <&pio17 0 ALT1 OUT>;
469 rx = <&pio17 1 ALT1 IN>;
470 };
471 };
472 pinctrl_serial0_rts: serial0_rts {
473 st,pins {
474 rts = <&pio17 3 ALT1 OUT>;
475 };
476 };
477
478 pinctrl_serial0_cts: serial0_cts {
479 st,pins {
480 cts = <&pio17 2 ALT1 IN>;
481 };
482 };
483 };
484
485 serial1 {
486 pinctrl_serial1: serial1-0 {
487 st,pins {
488 tx = <&pio16 0 ALT1 OUT>;
489 rx = <&pio16 1 ALT1 IN>;
490 };
491 };
492 };
493
494 serial2 {
495 pinctrl_serial2: serial2-0 {
496 st,pins {
497 tx = <&pio15 0 ALT1 OUT>;
498 rx = <&pio15 1 ALT1 IN>;
499 };
500 };
501 };
502
503 mmc1 {
504 pinctrl_sd1: sd1-0 {
505 st,pins {
506 sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>;
507 sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>;
508 sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>;
509 sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>;
510 sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>;
511 sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>;
512 sd_led = <&pio16 6 ALT6 OUT>;
513 sd_pwren = <&pio16 7 ALT6 OUT>;
514 sd_cd = <&pio19 0 ALT6 IN>;
515 sd_wp = <&pio19 1 ALT6 IN>;
516 };
517 };
518 };
519
520
521 i2c0 {
522 pinctrl_i2c0_default: i2c0-default {
523 st,pins {
524 sda = <&pio10 6 ALT2 BIDIR>;
525 scl = <&pio10 5 ALT2 BIDIR>;
526 };
527 };
528 };
529
530 i2c1 {
531 pinctrl_i2c1_default: i2c1-default {
532 st,pins {
533 sda = <&pio11 1 ALT2 BIDIR>;
534 scl = <&pio11 0 ALT2 BIDIR>;
535 };
536 };
537 };
538
539 i2c2 {
540 pinctrl_i2c2_default: i2c2-default {
541 st,pins {
542 sda = <&pio15 6 ALT2 BIDIR>;
543 scl = <&pio15 5 ALT2 BIDIR>;
544 };
545 };
546
547 pinctrl_i2c2_alt2_1: i2c2-alt2-1 {
548 st,pins {
549 sda = <&pio12 6 ALT2 BIDIR>;
550 scl = <&pio12 5 ALT2 BIDIR>;
551 };
552 };
553 };
554
555 i2c3 {
556 pinctrl_i2c3_default: i2c3-alt1-0 {
557 st,pins {
558 sda = <&pio18 6 ALT1 BIDIR>;
559 scl = <&pio18 5 ALT1 BIDIR>;
560 };
561 };
562 pinctrl_i2c3_alt1_1: i2c3-alt1-1 {
563 st,pins {
564 sda = <&pio17 7 ALT1 BIDIR>;
565 scl = <&pio17 6 ALT1 BIDIR>;
566 };
567 };
568 pinctrl_i2c3_alt3_0: i2c3-alt3-0 {
569 st,pins {
570 sda = <&pio13 6 ALT3 BIDIR>;
571 scl = <&pio13 5 ALT3 BIDIR>;
572 };
573 };
574 };
575
576 spi0 {
577 pinctrl_spi0_default: spi0-4w-alt2-0 {
578 st,pins {
579 mtsr = <&pio10 6 ALT2 OUT>;
580 mrst = <&pio10 7 ALT2 IN>;
581 scl = <&pio10 5 ALT2 OUT>;
582 };
583 };
584
585 pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 {
586 st,pins {
587 mtsr = <&pio10 6 ALT2 BIDIR_PU>;
588 scl = <&pio10 5 ALT2 OUT>;
589 };
590 };
591
592 pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 {
593 st,pins {
594 mtsr = <&pio19 7 ALT1 OUT>;
595 mrst = <&pio19 5 ALT1 IN>;
596 scl = <&pio19 6 ALT1 OUT>;
597 };
598 };
599
600 pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 {
601 st,pins {
602 mtsr = <&pio19 7 ALT1 BIDIR_PU>;
603 scl = <&pio19 6 ALT1 OUT>;
604 };
605 };
606 };
607
608 spi1 {
609 pinctrl_spi1_default: spi1-4w-alt2-0 {
610 st,pins {
611 mtsr = <&pio11 1 ALT2 OUT>;
612 mrst = <&pio11 2 ALT2 IN>;
613 scl = <&pio11 0 ALT2 OUT>;
614 };
615 };
616
617 pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 {
618 st,pins {
619 mtsr = <&pio11 1 ALT2 BIDIR_PU>;
620 scl = <&pio11 0 ALT2 OUT>;
621 };
622 };
623
624 pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 {
625 st,pins {
626 mtsr = <&pio14 3 ALT1 OUT>;
627 mrst = <&pio14 4 ALT1 IN>;
628 scl = <&pio14 2 ALT1 OUT>;
629 };
630 };
631
632 pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 {
633 st,pins {
634 mtsr = <&pio14 3 ALT1 BIDIR_PU>;
635 scl = <&pio14 2 ALT1 OUT>;
636 };
637 };
638 };
639
640 spi2 {
641 pinctrl_spi2_default: spi2-4w-alt2-0 {
642 st,pins {
643 mtsr = <&pio12 6 ALT2 OUT>;
644 mrst = <&pio12 7 ALT2 IN>;
645 scl = <&pio12 5 ALT2 OUT>;
646 };
647 };
648
649 pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 {
650 st,pins {
651 mtsr = <&pio12 6 ALT2 BIDIR_PU>;
652 scl = <&pio12 5 ALT2 OUT>;
653 };
654 };
655
656 pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 {
657 st,pins {
658 mtsr = <&pio14 6 ALT1 OUT>;
659 mrst = <&pio14 7 ALT1 IN>;
660 scl = <&pio14 5 ALT1 OUT>;
661 };
662 };
663
664 pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 {
665 st,pins {
666 mtsr = <&pio14 6 ALT1 BIDIR_PU>;
667 scl = <&pio14 5 ALT1 OUT>;
668 };
669 };
670
671 pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 {
672 st,pins {
673 mtsr = <&pio15 6 ALT2 OUT>;
674 mrst = <&pio15 7 ALT2 IN>;
675 scl = <&pio15 5 ALT2 OUT>;
676 };
677 };
678
679 pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 {
680 st,pins {
681 mtsr = <&pio15 6 ALT2 BIDIR_PU>;
682 scl = <&pio15 5 ALT2 OUT>;
683 };
684 };
685 };
686
687 spi3 {
688 pinctrl_spi3_default: spi3-4w-alt3-0 {
689 st,pins {
690 mtsr = <&pio13 6 ALT3 OUT>;
691 mrst = <&pio13 7 ALT3 IN>;
692 scl = <&pio13 5 ALT3 OUT>;
693 };
694 };
695
696 pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 {
697 st,pins {
698 mtsr = <&pio13 6 ALT3 BIDIR_PU>;
699 scl = <&pio13 5 ALT3 OUT>;
700 };
701 };
702
703 pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 {
704 st,pins {
705 mtsr = <&pio17 7 ALT1 OUT>;
706 mrst = <&pio17 5 ALT1 IN>;
707 scl = <&pio17 6 ALT1 OUT>;
708 };
709 };
710
711 pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 {
712 st,pins {
713 mtsr = <&pio17 7 ALT1 BIDIR_PU>;
714 scl = <&pio17 6 ALT1 OUT>;
715 };
716 };
717
718 pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 {
719 st,pins {
720 mtsr = <&pio18 6 ALT1 OUT>;
721 mrst = <&pio18 7 ALT1 IN>;
722 scl = <&pio18 5 ALT1 OUT>;
723 };
724 };
725
726 pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 {
727 st,pins {
728 mtsr = <&pio18 6 ALT1 BIDIR_PU>;
729 scl = <&pio18 5 ALT1 OUT>;
730 };
731 };
732 };
733
734 tsin0 {
735 pinctrl_tsin0_parallel: tsin0_parallel {
736 st,pins {
737 DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
738 DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
739 DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
740 DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
741 DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
742 DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
743 DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
744 DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
745 CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
746 VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
747 ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
748 PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
749 };
750 };
751 pinctrl_tsin0_serial: tsin0_serial {
752 st,pins {
753 DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
754 CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
755 VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
756 ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
757 PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
758 };
759 };
760 };
761
762 tsin1 {
763 pinctrl_tsin1_parallel: tsin1_parallel {
764 st,pins {
765 DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
766 DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
767 DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
768 DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
769 DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
770 DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
771 DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
772 DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
773 CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
774 VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
775 ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
776 PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
777 };
778 };
779 pinctrl_tsin1_serial: tsin1_serial {
780 st,pins {
781 DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
782 CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
783 VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
784 ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
785 PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
786 };
787 };
788 };
789
790 tsin2 {
791 pinctrl_tsin2_parallel: tsin2_parallel {
792 st,pins {
793 DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
794 DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>;
795 DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>;
796 DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>;
797 DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
798 DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>;
799 DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
800 DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
801 CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
802 VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
803 ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
804 PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
805 };
806 };
807 pinctrl_tsin2_serial: tsin2_serial {
808 st,pins {
809 DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
810 CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
811 VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
812 ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
813 PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
814 };
815 };
816 };
817
818 tsin3 {
819 pinctrl_tsin3_serial: tsin3_serial {
820 st,pins {
821 DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
822 CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>;
823 VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
824 ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
825 PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
826 };
827 };
828 };
829
830 tsin4 {
831 pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 {
832 st,pins {
833 DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
834 CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>;
835 VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>;
836 ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>;
837 PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
838 };
839 };
840 };
841
842 tsin5 {
843 pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 {
844 st,pins {
845 DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
846 CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
847 VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
848 ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
849 PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
850 };
851 };
852 pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 {
853 st,pins {
854 DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>;
855 CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>;
856 VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
857 ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
858 PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
859 };
860 };
861 };
862
863 tsout0 {
864 pinctrl_tsout0_parallel: tsout0_parallel {
865 st,pins {
866 DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
867 DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
868 DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
869 DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
870 DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
871 DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
872 DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
873 DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
874 CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
875 VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
876 ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
877 PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
878 };
879 };
880 pinctrl_tsout0_serial: tsout0_serial {
881 st,pins {
882 DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
883 CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
884 VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
885 ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
886 PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
887 };
888 };
889 };
890
891 tsout1 {
892 pinctrl_tsout1_serial: tsout1_serial {
893 st,pins {
894 DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
895 CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>;
896 VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
897 ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
898 PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
899 };
900 };
901 };
902
903 mtsin0 {
904 pinctrl_mtsin0_parallel: mtsin0_parallel {
905 st,pins {
906 DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
907 DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>;
908 DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
909 DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>;
910 DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
911 DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
912 DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
913 DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>;
914 CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>;
915 VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
916 ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
917 PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
918 };
919 };
920 };
921
922 systrace {
923 pinctrl_systrace_default: systrace-default {
924 st,pins {
925 trc_data0 = <&pio11 3 ALT5 OUT>;
926 trc_data1 = <&pio11 4 ALT5 OUT>;
927 trc_data2 = <&pio11 5 ALT5 OUT>;
928 trc_data3 = <&pio11 6 ALT5 OUT>;
929 trc_clk = <&pio11 7 ALT5 OUT>;
930 };
931 };
932 };
933 };
934
935 pin-controller-front1 {
936 #address-cells = <1>;
937 #size-cells = <1>;
938 compatible = "st,stih407-front-pinctrl";
939 st,syscfg = <&syscfg_front>;
940 reg = <0x0921f080 0x4>;
941 reg-names = "irqmux";
942 interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
943 interrupt-names = "irqmux";
944 ranges = <0 0x09210000 0x10000>;
945
946 pio20: pio@09210000 {
947 gpio-controller;
948 #gpio-cells = <2>;
949 interrupt-controller;
950 #interrupt-cells = <2>;
951 reg = <0x0 0x100>;
952 st,bank-name = "PIO20";
953 };
954
955 tsin4 {
956 pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 {
957 st,pins {
958 DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
959 CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
960 VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
961 ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
962 PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
963 };
964 };
965 };
966 };
967
968 pin-controller-rear {
969 #address-cells = <1>;
970 #size-cells = <1>;
971 compatible = "st,stih407-rear-pinctrl";
972 st,syscfg = <&syscfg_rear>;
973 reg = <0x0922f080 0x4>;
974 reg-names = "irqmux";
975 interrupts = <GIC_SPI 191 IRQ_TYPE_NONE>;
976 interrupt-names = "irqmux";
977 ranges = <0 0x09220000 0x6000>;
978
979 pio30: gpio@09220000 {
980 gpio-controller;
981 #gpio-cells = <2>;
982 interrupt-controller;
983 #interrupt-cells = <2>;
984 reg = <0x0 0x100>;
985 st,bank-name = "PIO30";
986 };
987 pio31: gpio@09221000 {
988 gpio-controller;
989 #gpio-cells = <2>;
990 interrupt-controller;
991 #interrupt-cells = <2>;
992 reg = <0x1000 0x100>;
993 st,bank-name = "PIO31";
994 };
995 pio32: gpio@09222000 {
996 gpio-controller;
997 #gpio-cells = <2>;
998 interrupt-controller;
999 #interrupt-cells = <2>;
1000 reg = <0x2000 0x100>;
1001 st,bank-name = "PIO32";
1002 };
1003 pio33: gpio@09223000 {
1004 gpio-controller;
1005 #gpio-cells = <2>;
1006 interrupt-controller;
1007 #interrupt-cells = <2>;
1008 reg = <0x3000 0x100>;
1009 st,bank-name = "PIO33";
1010 };
1011 pio34: gpio@09224000 {
1012 gpio-controller;
1013 #gpio-cells = <2>;
1014 interrupt-controller;
1015 #interrupt-cells = <2>;
1016 reg = <0x4000 0x100>;
1017 st,bank-name = "PIO34";
1018 };
1019 pio35: gpio@09225000 {
1020 gpio-controller;
1021 #gpio-cells = <2>;
1022 interrupt-controller;
1023 #interrupt-cells = <2>;
1024 reg = <0x5000 0x100>;
1025 st,bank-name = "PIO35";
1026 st,retime-pin-mask = <0x7f>;
1027 };
1028
1029 dvo {
1030 pinctrl_dvo: dvo {
1031 st,pins {
1032 hs = <&pio30 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1033 vs = <&pio30 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1034 de = <&pio30 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1035 ck = <&pio30 3 ALT2 (OE | CLKNOTDATA) 0>;
1036 d0 = <&pio30 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1037 d1 = <&pio30 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1038 d2 = <&pio30 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1039 d3 = <&pio30 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1040 d4 = <&pio31 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1041 d5 = <&pio31 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1042 d6 = <&pio31 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1043 d7 = <&pio31 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1044 d8 = <&pio31 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1045 d9 = <&pio31 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1046 d10 = <&pio31 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1047 d11 = <&pio31 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1048 d12 = <&pio32 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1049 d13 = <&pio32 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1050 d14 = <&pio32 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1051 d15 = <&pio32 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1052 d16 = <&pio32 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1053 d17 = <&pio32 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1054 d18 = <&pio32 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1055 d19 = <&pio32 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1056 d20 = <&pio33 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1057 d21 = <&pio33 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1058 d22 = <&pio33 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1059 d23 = <&pio33 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
1060 };
1061 };
1062 };
1063
1064 i2c4 {
1065 pinctrl_i2c4_default: i2c4-default {
1066 st,pins {
1067 sda = <&pio30 1 ALT1 BIDIR>;
1068 scl = <&pio30 0 ALT1 BIDIR>;
1069 };
1070 };
1071 };
1072
1073 i2c5 {
1074 pinctrl_i2c5_default: i2c5-default {
1075 st,pins {
1076 sda = <&pio34 4 ALT1 BIDIR>;
1077 scl = <&pio34 3 ALT1 BIDIR>;
1078 };
1079 };
1080 };
1081
1082 usb3 {
1083 pinctrl_usb3: usb3-2 {
1084 st,pins {
1085 usb-oc-detect = <&pio35 4 ALT1 IN>;
1086 usb-pwr-enable = <&pio35 5 ALT1 OUT>;
1087 usb-vbus-valid = <&pio35 6 ALT1 IN>;
1088 };
1089 };
1090 };
1091
1092 pwm0 {
1093 pinctrl_pwm0_chan0_default: pwm0-0-default {
1094 st,pins {
1095 pwm-capturein = <&pio31 0 ALT1 IN>;
1096 pwm-out = <&pio31 1 ALT1 OUT>;
1097 };
1098 };
1099 };
1100
1101 spi4 {
1102 pinctrl_spi4_default: spi4-4w-alt1-0 {
1103 st,pins {
1104 mtsr = <&pio30 1 ALT1 OUT>;
1105 mrst = <&pio30 2 ALT1 IN>;
1106 scl = <&pio30 0 ALT1 OUT>;
1107 };
1108 };
1109
1110 pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 {
1111 st,pins {
1112 mtsr = <&pio30 1 ALT1 BIDIR_PU>;
1113 scl = <&pio30 0 ALT1 OUT>;
1114 };
1115 };
1116
1117 pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 {
1118 st,pins {
1119 mtsr = <&pio34 1 ALT3 OUT>;
1120 mrst = <&pio34 2 ALT3 IN>;
1121 scl = <&pio34 0 ALT3 OUT>;
1122 };
1123 };
1124
1125 pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 {
1126 st,pins {
1127 mtsr = <&pio34 1 ALT3 BIDIR_PU>;
1128 scl = <&pio34 0 ALT3 OUT>;
1129 };
1130 };
1131 };
1132
1133 i2s_out {
1134 pinctrl_i2s_8ch_out: i2s_8ch_out{
1135 st,pins {
1136 mclk = <&pio33 5 ALT1 OUT>;
1137 lrclk = <&pio33 7 ALT1 OUT>;
1138 sclk = <&pio33 6 ALT1 OUT>;
1139 data0 = <&pio33 4 ALT1 OUT>;
1140 data1 = <&pio34 0 ALT1 OUT>;
1141 data2 = <&pio34 1 ALT1 OUT>;
1142 data3 = <&pio34 2 ALT1 OUT>;
1143 };
1144 };
1145
1146 pinctrl_i2s_2ch_out: i2s_2ch_out{
1147 st,pins {
1148 mclk = <&pio33 5 ALT1 OUT>;
1149 lrclk = <&pio33 7 ALT1 OUT>;
1150 sclk = <&pio33 6 ALT1 OUT>;
1151 data0 = <&pio33 4 ALT1 OUT>;
1152 };
1153 };
1154 };
1155
1156 i2s_in {
1157 pinctrl_i2s_8ch_in: i2s_8ch_in{
1158 st,pins {
1159 mclk = <&pio32 5 ALT1 IN>;
1160 lrclk = <&pio32 7 ALT1 IN>;
1161 sclk = <&pio32 6 ALT1 IN>;
1162 data0 = <&pio32 4 ALT1 IN>;
1163 data1 = <&pio33 0 ALT1 IN>;
1164 data2 = <&pio33 1 ALT1 IN>;
1165 data3 = <&pio33 2 ALT1 IN>;
1166 data4 = <&pio33 3 ALT1 IN>;
1167 };
1168 };
1169
1170 pinctrl_i2s_2ch_in: i2s_2ch_in{
1171 st,pins {
1172 mclk = <&pio32 5 ALT1 IN>;
1173 lrclk = <&pio32 7 ALT1 IN>;
1174 sclk = <&pio32 6 ALT1 IN>;
1175 data0 = <&pio32 4 ALT1 IN>;
1176 };
1177 };
1178 };
1179
1180 spdif_out {
1181 pinctrl_spdif_out: spdif_out{
1182 st,pins {
1183 spdif_out = <&pio34 7 ALT1 OUT>;
1184 };
1185 };
1186 };
1187
1188 serial3 {
1189 pinctrl_serial3: serial3-0 {
1190 st,pins {
1191 tx = <&pio31 3 ALT1 OUT>;
1192 rx = <&pio31 4 ALT1 IN>;
1193 };
1194 };
1195 };
1196 };
1197
1198 pin-controller-flash {
1199 #address-cells = <1>;
1200 #size-cells = <1>;
1201 compatible = "st,stih407-flash-pinctrl";
1202 st,syscfg = <&syscfg_flash>;
1203 reg = <0x0923f080 0x4>;
1204 reg-names = "irqmux";
1205 interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>;
1206 interrupts-names = "irqmux";
1207 ranges = <0 0x09230000 0x3000>;
1208
1209 pio40: gpio@09230000 {
1210 gpio-controller;
1211 #gpio-cells = <2>;
1212 interrupt-controller;
1213 #interrupt-cells = <2>;
1214 reg = <0 0x100>;
1215 st,bank-name = "PIO40";
1216 };
1217 pio41: gpio@09231000 {
1218 gpio-controller;
1219 #gpio-cells = <2>;
1220 interrupt-controller;
1221 #interrupt-cells = <2>;
1222 reg = <0x1000 0x100>;
1223 st,bank-name = "PIO41";
1224 };
1225 pio42: gpio@09232000 {
1226 gpio-controller;
1227 #gpio-cells = <2>;
1228 interrupt-controller;
1229 #interrupt-cells = <2>;
1230 reg = <0x2000 0x100>;
1231 st,bank-name = "PIO42";
1232 };
1233
1234 mmc0 {
1235 pinctrl_mmc0: mmc0-0 {
1236 st,pins {
1237 emmc_clk = <&pio40 6 ALT1 BIDIR>;
1238 emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>;
1239 emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>;
1240 emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>;
1241 emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>;
1242 emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>;
1243 emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>;
1244 emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>;
1245 emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>;
1246 emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>;
1247 };
1248 };
1249 pinctrl_sd0: sd0-0 {
1250 st,pins {
1251 sd_clk = <&pio40 6 ALT1 BIDIR>;
1252 sd_cmd = <&pio40 7 ALT1 BIDIR_PU>;
1253 sd_dat0 = <&pio41 0 ALT1 BIDIR_PU>;
1254 sd_dat1 = <&pio41 1 ALT1 BIDIR_PU>;
1255 sd_dat2 = <&pio41 2 ALT1 BIDIR_PU>;
1256 sd_dat3 = <&pio41 3 ALT1 BIDIR_PU>;
1257 sd_led = <&pio42 0 ALT2 OUT>;
1258 sd_pwren = <&pio42 2 ALT2 OUT>;
1259 sd_vsel = <&pio42 3 ALT2 OUT>;
1260 sd_cd = <&pio42 4 ALT2 IN>;
1261 sd_wp = <&pio42 5 ALT2 IN>;
1262 };
1263 };
1264 };
1265
1266 fsm {
1267 pinctrl_fsm: fsm {
1268 st,pins {
1269 spi-fsm-clk = <&pio40 1 ALT1 OUT>;
1270 spi-fsm-cs = <&pio40 0 ALT1 OUT>;
1271 spi-fsm-mosi = <&pio40 2 ALT1 OUT>;
1272 spi-fsm-miso = <&pio40 3 ALT1 IN>;
1273 spi-fsm-hol = <&pio40 5 ALT1 OUT>;
1274 spi-fsm-wp = <&pio40 4 ALT1 OUT>;
1275 };
1276 };
1277 };
1278
1279 nand {
1280 pinctrl_nand: nand {
1281 st,pins {
1282 nand_cs1 = <&pio40 6 ALT3 OUT>;
1283 nand_cs0 = <&pio40 7 ALT3 OUT>;
1284 nand_d0 = <&pio41 0 ALT3 BIDIR>;
1285 nand_d1 = <&pio41 1 ALT3 BIDIR>;
1286 nand_d2 = <&pio41 2 ALT3 BIDIR>;
1287 nand_d3 = <&pio41 3 ALT3 BIDIR>;
1288 nand_d4 = <&pio41 4 ALT3 BIDIR>;
1289 nand_d5 = <&pio41 5 ALT3 BIDIR>;
1290 nand_d6 = <&pio41 6 ALT3 BIDIR>;
1291 nand_d7 = <&pio41 7 ALT3 BIDIR>;
1292 nand_we = <&pio42 0 ALT3 OUT>;
1293 nand_dqs = <&pio42 1 ALT3 OUT>;
1294 nand_ale = <&pio42 2 ALT3 OUT>;
1295 nand_cle = <&pio42 3 ALT3 OUT>;
1296 nand_rnb = <&pio42 4 ALT3 IN>;
1297 nand_oe = <&pio42 5 ALT3 OUT>;
1298 };
1299 };
1300 };
1301 };
1302 };
1303};