| York Sun | 667ab1a | 2012-10-11 07:13:37 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Freescale Semiconductor, Inc. |
| 3 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| York Sun | 667ab1a | 2012-10-11 07:13:37 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __T4020QDS_QIXIS_H__ |
| 8 | #define __T4020QDS_QIXIS_H__ |
| 9 | |
| 10 | /* Definitions of QIXIS Registers for T4020QDS */ |
| 11 | |
| 12 | /* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ |
| 13 | #define BRDCFG4_EMISEL_MASK 0xE0 |
| 14 | #define BRDCFG4_EMISEL_SHIFT 5 |
| 15 | |
| 16 | /* SYSCLK */ |
| 17 | #define QIXIS_SYSCLK_66 0x0 |
| 18 | #define QIXIS_SYSCLK_83 0x1 |
| 19 | #define QIXIS_SYSCLK_100 0x2 |
| 20 | #define QIXIS_SYSCLK_125 0x3 |
| 21 | #define QIXIS_SYSCLK_133 0x4 |
| 22 | #define QIXIS_SYSCLK_150 0x5 |
| 23 | #define QIXIS_SYSCLK_160 0x6 |
| 24 | #define QIXIS_SYSCLK_166 0x7 |
| 25 | |
| 26 | /* DDRCLK */ |
| 27 | #define QIXIS_DDRCLK_66 0x0 |
| 28 | #define QIXIS_DDRCLK_100 0x1 |
| 29 | #define QIXIS_DDRCLK_125 0x2 |
| 30 | #define QIXIS_DDRCLK_133 0x3 |
| 31 | |
| Ed Swarthout | a55ec45 | 2013-03-25 07:39:37 +0000 | [diff] [blame] | 32 | #define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */ |
| York Sun | 667ab1a | 2012-10-11 07:13:37 +0000 | [diff] [blame] | 33 | |
| 34 | #define BRDCFG12_SD3EN_MASK 0x20 |
| 35 | #define BRDCFG12_SD3MX_MASK 0x08 |
| 36 | #define BRDCFG12_SD3MX_SLOT5 0x08 |
| 37 | #define BRDCFG12_SD3MX_SLOT6 0x00 |
| 38 | #define BRDCFG12_SD4EN_MASK 0x04 |
| 39 | #define BRDCFG12_SD4MX_MASK 0x03 |
| 40 | #define BRDCFG12_SD4MX_SLOT7 0x02 |
| 41 | #define BRDCFG12_SD4MX_SLOT8 0x01 |
| 42 | #define BRDCFG12_SD4MX_AURO_SATA 0x00 |
| 43 | #endif |