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git01.mediatek.com / filogic / uboot / e8e2224a2eb015c2a729d057513703d3444227d6 / . / include / mpc8220.h
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wdenk337f5652004-10-28 00:09:35 +0000[diff] [blame]1/*
2 * include/mpc8220.h
3 *
4 * Prototypes, etc. for the Motorola MPC8220
5 * embedded cpu chips
6 *
7 * 2004 (c) Freescale, Inc.
8 * Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28#ifndef __MPC8220_H__
29#define __MPC8220_H__
30
31/* Processor name */
32#if defined(CONFIG_MPC8220)
33#define CPU_ID_STR "MPC8220"
34#endif
35
36/* Exception offsets (PowerPC standard) */
37#define EXC_OFF_SYS_RESET 0x0100
38
39/* Internal memory map */
40/* MPC8220 Internal Register MMAP */
41#define MMAP_MBAR (CFG_MBAR + 0x00000000) /* chip selects */
42#define MMAP_MEMCTL (CFG_MBAR + 0x00000100) /* sdram controller */
43#define MMAP_XLBARB (CFG_MBAR + 0x00000200) /* xlb arbitration control */
44#define MMAP_CDM (CFG_MBAR + 0x00000300) /* clock distribution module */
45#define MMAP_VDOPLL (CFG_MBAR + 0x00000400) /* video PLL */
46#define MMAP_FB (CFG_MBAR + 0x00000500) /* flex bus controller */
47#define MMAP_PCFG (CFG_MBAR + 0x00000600) /* port config */
48#define MMAP_ICTL (CFG_MBAR + 0x00000700) /* interrupt controller */
49#define MMAP_GPTMR (CFG_MBAR + 0x00000800) /* general purpose timers */
50#define MMAP_SLTMR (CFG_MBAR + 0x00000900) /* slice timers */
51#define MMAP_GPIO (CFG_MBAR + 0x00000A00) /* gpio module */
52#define MMAP_XCPCI (CFG_MBAR + 0x00000B00) /* pci controller */
53#define MMAP_PCIARB (CFG_MBAR + 0x00000C00) /* pci arbiter */
54#define MMAP_EXTDMA1 (CFG_MBAR + 0x00000D00) /* external dma1 */
55#define MMAP_EXTDMA2 (CFG_MBAR + 0x00000E00) /* external dma1 */
56#define MMAP_USBH (CFG_MBAR + 0x00001000) /* usb host */
57#define MMAP_CMTMR (CFG_MBAR + 0x00007f00) /* comm timers */
58#define MMAP_DMA (CFG_MBAR + 0x00008000) /* dma */
59#define MMAP_USBD (CFG_MBAR + 0x00008200) /* usb device */
60#define MMAP_COMMPCI (CFG_MBAR + 0x00008400) /* pci comm Bus regs */
61#define MMAP_1284 (CFG_MBAR + 0x00008500) /* 1284 */
62#define MMAP_PEV (CFG_MBAR + 0x00008600) /* print engine video */
63#define MMAP_PSC1 (CFG_MBAR + 0x00008800) /* psc1 block */
64#define MMAP_I2C (CFG_MBAR + 0x00008f00) /* i2c controller */
65#define MMAP_FEC1 (CFG_MBAR + 0x00009000) /* fast ethernet 1 */
66#define MMAP_FEC2 (CFG_MBAR + 0x00009800) /* fast ethernet 2 */
67#define MMAP_JBIGRAM (CFG_MBAR + 0x0000a000) /* jbig RAM */
68#define MMAP_JBIG (CFG_MBAR + 0x0000c000) /* jbig */
69#define MMAP_PDLA (CFG_MBAR + 0x00010000) /* */
70#define MMAP_SRAMCFG (CFG_MBAR + 0x0001ff00) /* SRAM config */
71#define MMAP_SRAM (CFG_MBAR + 0x00020000) /* SRAM */
72
73#define SRAM_SIZE 0x8000 /* 32 KB */
74
75/* ------------------------------------------------------------------------ */
76/*
77 * Macro for Programmable Serial Channel
78 */
79/* equates for mode reg. 1 for channel A or B */
80#define PSC_MR1_RX_RTS 0x80000000 /* receiver RTS enabled */
81#define PSC_MR1_RX_INT 0x40000000 /* receiver intrupt enabled */
82#define PSC_MR1_ERR_MODE 0x20000000 /* block error mode */
83#define PSC_MR1_PAR_MODE_MULTI 0x18000000 /* multi_drop mode */
84#define PSC_MR1_NO_PARITY 0x10000000 /* no parity mode */
85#define PSC_MR1_ALWAYS_0 0x08000000 /* force parity mode */
86#define PSC_MR1_ALWAYS_1 0x0c000000 /* force parity mode */
87#define PSC_MR1_EVEN_PARITY 0x00000000 /* parity mode */
88#define PSC_MR1_ODD_PARITY 0x04000000 /* 0 = even, 1 = odd */
89#define PSC_MR1_BITS_CHAR_8 0x03000000 /* 8 bits */
90#define PSC_MR1_BITS_CHAR_7 0x02000000 /* 7 bits */
91#define PSC_MR1_BITS_CHAR_6 0x01000000 /* 6 bits */
92#define PSC_MR1_BITS_CHAR_5 0x00000000 /* 5 bits */
93
94/* equates for mode reg. 2 for channel A or B */
95#define PSC_MR2_NORMAL_MODE 0x00000000 /* normal channel mode */
96#define PSC_MR2_AUTO_MODE 0x40000000 /* automatic channel mode */
97#define PSC_MR2_LOOPBACK_LOCL 0x80000000 /* local loopback channel mode */
98#define PSC_MR2_LOOPBACK_REMT 0xc0000000 /* remote loopback channel mode */
99#define PSC_MR2_TX_RTS 0x20000000 /* transmitter RTS enabled */
100#define PSC_MR2_TX_CTS 0x10000000 /* transmitter CTS enabled */
101#define PSC_MR2_STOP_BITS_2 0x0f000000 /* 2 stop bits */
102#define PSC_MR2_STOP_BITS_1 0x07000000 /* 1 stop bit */
103
104/* equates for status reg. A or B */
105#define PSC_SR_BREAK 0x80000000 /* received break */
106#define PSC_SR_NEOF PSC_SR_BREAK /* Next byte is EOF - MIR/FIR */
107#define PSC_SR_FRAMING 0x40000000 /* framing error */
108#define PSC_SR_PHYERR PSC_SR_FRAMING/* Physical Layer error - MIR/FIR */
109#define PSC_SR_PARITY 0x20000000 /* parity error */
110#define PSC_SR_CRCERR PSC_SR_PARITY /* CRC error */
111#define PSC_SR_OVERRUN 0x10000000 /* overrun error */
112#define PSC_SR_TXEMT 0x08000000 /* transmitter empty */
113#define PSC_SR_TXRDY 0x04000000 /* transmitter ready*/
114#define PSC_SR_FFULL 0x02000000 /* fifo full */
115#define PSC_SR_RXRDY 0x01000000 /* receiver ready */
116#define PSC_SR_DEOF 0x00800000 /* Detect EOF or RX-FIFO contain EOF */
117#define PSC_SR_ERR 0x00400000 /* Error Status including FIFO */
118
119/* equates for clock select reg. */
120#define PSC_CSRX16EXT_CLK 0x1110 /* x 16 ext_clock */
121#define PSC_CSRX1EXT_CLK 0x1111 /* x 1 ext_clock */
122
123/* equates for command reg. A or B */
124#define PSC_CR_NO_COMMAND 0x00000000 /* no command */
125#define PSC_CR_RST_MR_PTR_CMD 0x10000000 /* reset mr pointer command */
126#define PSC_CR_RST_RX_CMD 0x20000000 /* reset receiver command */
127#define PSC_CR_RST_TX_CMD 0x30000000 /* reset transmitter command */
128#define PSC_CR_RST_ERR_STS_CMD 0x40000000 /* reset error status cmnd */
129#define PSC_CR_RST_BRK_INT_CMD 0x50000000 /* reset break int. command */
130#define PSC_CR_STR_BREAK_CMD 0x60000000 /* start break command */
131#define PSC_CR_STP_BREAK_CMD 0x70000000 /* stop break command */
132#define PSC_CR_RX_ENABLE 0x01000000 /* receiver enabled */
133#define PSC_CR_RX_DISABLE 0x02000000 /* receiver disabled */
134#define PSC_CR_TX_ENABLE 0x04000000 /* transmitter enabled */
135#define PSC_CR_TX_DISABLE 0x08000000 /* transmitter disabled */
136
137/* equates for input port change reg. */
138#define PSC_IPCR_SYNC 0x80000000 /* Sync Detect */
139#define PSC_IPCR_D_CTS 0x10000000 /* Delta CTS */
140#define PSC_IPCR_CTS 0x01000000 /* CTS - current state of PSC_CTS */
141
142/* equates for auxiliary control reg. (timer and counter clock selects) */
143#define PSC_ACR_BRG 0x80000000 /* for 68681 compatibility
144 baud rate gen select
145 0 = set 1; 1 = set 2
146 equates are set 2 ONLY */
147#define PSC_ACR_TMR_EXT_CLK_16 0x70000000 /* xtnl clock divided by 16 */
148#define PSC_ACR_TMR_EXT_CLK 0x60000000 /* external clock */
149#define PSC_ACR_TMR_IP2_16 0x50000000 /* ip2 divided by 16 */
150#define PSC_ACR_TMR_IP2 0x40000000 /* ip2 */
151#define PSC_ACR_CTR_EXT_CLK_16 0x30000000 /* xtnl clock divided by 16 */
152#define PSC_ACR_CTR_TXCB 0x20000000 /* channel B xmitr clock */
153#define PSC_ACR_CTR_TXCA 0x10000000 /* channel A xmitr clock */
154#define PSC_ACR_CTR_IP2 0x00000000 /* ip2 */
155#define PSC_ACR_IEC0 0x01000000 /* interrupt enable ctrl for D_CTS */
156
157/* equates for int. status reg. */
158#define PSC_ISR_IPC 0x80000000 /* input port change*/
159#define PSC_ISR_BREAK 0x04000000 /* delta break */
160#define PSC_ISR_RX_RDY 0x02000000 /* receiver rdy /fifo full */
161#define PSC_ISR_TX_RDY 0x01000000 /* transmitter ready */
162#define PSC_ISR_DEOF 0x00800000 /* Detect EOF / RX-FIFO contains EOF */
163#define PSC_ISR_ERR 0x00400000 /* Error Status including FIFO */
164
165/* equates for int. mask reg. */
166#define PSC_IMR_CLEAR 0xff000000 /* Clear the imr */
167#define PSC_IMR_IPC 0x80000000 /* input port change*/
168#define PSC_IMR_BREAK 0x04000000 /* delta break */
169#define PSC_IMR_RX_RDY 0x02000000 /* rcvr ready / fifo full */
170#define PSC_IMR_TX_RDY 0x01000000 /* transmitter ready */
171#define PSC_IMR_DEOF 0x00800000 /* Detect EOF / RX-FIFO contains EOF */
172#define PSC_IMR_ERR 0x00400000 /* Error Status including FIFO */
173
174/* equates for input port reg. */
175#define PSC_IP_LPWRB 0x80000000 /* Low power mode in Ac97 */
176#define PSC_IP_TGL 0x40000000 /* test usage */
177#define PSC_IP_CTS 0x01000000 /* CTS */
178
179/* equates for output port bit set reg. */
180#define PSC_OPSET_RTS 0x01000000 /* Assert PSC_RTS output */
181
182/* equates for output port bit reset reg. */
183#define PSC_OPRESET_RTS 0x01000000 /* Assert PSC_RTS output */
184
185/* equates for rx FIFO number of data reg. */
186#define PSC_RFNUM(x) ((x&0xff)<<24)/* receive count */
187
188/* equates for tx FIFO number of data reg. */
189#define PSC_TFNUM(x) ((x&0xff)<<24)/* receive count */
190
191/* equates for rx FIFO status reg */
192#define PSC_RFSTAT_TAG(x) ((x&3)<<28) /* tag */
193#define PSC_RFSTAT_FRAME0 0x08 /* Frame Indicator 0 */
194#define PSC_RFSTAT_FRAME1 0x04 /* Frame Indicator 1 */
195#define PSC_RFSTAT_FRAME2 0x02 /* Frame Indicator 2 */
196#define PSC_RFSTAT_FRAME3 0x01 /* Frame Indicator 3 */
197#define PSC_RFSTAT_FRAME(x) ((x&0x0f)<<24)/* Frame indicator */
198#define PSC_RFSTAT_ERR 0x00400000 /* Fifo err */
199#define PSC_RFSTAT_UF 0x00200000 /* Underflow */
200#define PSC_RFSTAT_OF 0x00100000 /* overflow */
201#define PSC_RFSTAT_FR 0x00080000 /* frame ready */
202#define PSC_RFSTAT_FULL 0x00040000 /* full */
203#define PSC_RFSTAT_ALARM 0x00020000 /* alarm */
204#define PSC_RFSTAT_EMPTY 0x00010000 /* empty */
205
206/* equates for tx FIFO status reg */
207#define PSC_TFSTAT_TAG(x) ((x&3)<<28) /* tag */
208#define PSC_TFSTAT_FRAME0 0x08 /* Frame Indicator 0 */
209#define PSC_TFSTAT_FRAME1 0x04 /* Frame Indicator 1 */
210#define PSC_TFSTAT_FRAME2 0x02 /* Frame Indicator 2 */
211#define PSC_TFSTAT_FRAME3 0x01 /* Frame Indicator 3 */
212#define PSC_TFSTAT_FRAME(x) ((x&0x0f)<<24)/* Frame indicator */
213#define PSC_TFSTAT_ERR 0x00400000 /* Fifo err */
214#define PSC_TFSTAT_UF 0x00200000 /* Underflow */
215#define PSC_TFSTAT_OF 0x00100000 /* overflow */
216#define PSC_TFSTAT_FR 0x00080000 /* frame ready */
217#define PSC_TFSTAT_FULL 0x00040000 /* full */
218#define PSC_TFSTAT_ALARM 0x00020000 /* alarm */
219#define PSC_TFSTAT_EMPTY 0x00010000 /* empty */
220
221/* equates for rx FIFO control reg. */
222#define PSC_RFCNTL_WTAG(x) ((x&3)<<29) /* Write tag */
223#define PSC_RFCNTL_FRAME 0x08000000 /* Frame mode enable */
224#define PSC_RFCNTL_GR(x) ((x&7)<<24) /* Granularity */
225
226/* equates for tx FIFO control reg. */
227#define PSC_TFCNTL_WTAG(x) ((x&3)<<29) /* Write tag */
228#define PSC_TFCNTL_FRAME 0x08000000 /* Frame mode enable */
229#define PSC_TFCNTL_GR(x) ((x&7)<<24) /* Granularity */
230
231/* equates for rx FIFO alarm reg */
232#define PSC_RFALARM(x) (x&0x1ff) /* Alarm */
233
234/* equates for tx FIFO alarm reg */
235#define PSC_TFALARM(x) (x&0x1ff) /* Alarm */
236
237/* equates for rx FIFO read pointer */
238#define PSC_RFRPTR(x) (x&0x1ff) /* read pointer */
239
240/* equates for tx FIFO read pointer */
241#define PSC_TFRPTR(x) (x&0x1ff) /* read pointer */
242
243/* equates for rx FIFO write pointer */
244#define PSC_RFWPTR(x) (x&0x1ff) /* write pointer */
245
246/* equates for rx FIFO write pointer */
247#define PSC_TFWPTR(x) (x&0x1ff) /* write pointer */
248
249/* equates for rx FIFO last read frame pointer reg */
250#define PSC_RFLRFPTR(x) (x&0x1ff) /* last read frame pointer */
251
252/* equates for tx FIFO last read frame pointer reg */
253#define PSC_TFLRFPTR(x) (x&0x1ff) /* last read frame pointer */
254
255/* equates for rx FIFO last write frame pointer reg */
256#define PSC_RFLWFPTR(x) (x&0x1ff) /* last write frame pointer */
257
258/* equates for tx FIFO last write frame pointer reg */
259#define PSC_TFLWFPTR(x) (x&0x1ff) /* last write frame pointer */
260
261
262/* ------------------------------------------------------------------------ */
263/*
264 * Macro for General Purpose Timer
265 */
266/* Enable and Mode Select */
267#define GPT_OCT(x) (x & 0x3)<<4/* Output Compare Type */
268#define GPT_ICT(x) (x & 0x3) /* Input Capture Type */
269#define GPT_CTRL_WDEN 0x80 /* Watchdog Enable */
270#define GPT_CTRL_CE 0x10 /* Counter Enable */
271#define GPT_CTRL_STPCNT 0x04 /* Stop continous */
272#define GPT_CTRL_ODRAIN 0x02 /* Open Drain */
273#define GPT_CTRL_INTEN 0x01 /* Interrupt Enable */
274#define GPT_MODE_GPIO(x) (x & 0x3)<<4/* Gpio Mode Type */
275#define GPT_TMS_ICT 0x01 /* Input Capture Enable */
276#define GPT_TMS_OCT 0x02 /* Output Capture Enable */
277#define GPT_TMS_PWM 0x03 /* PWM Capture Enable */
278#define GPT_TMS_SGPIO 0x04 /* PWM Capture Enable */
279
280#define GPT_PWM_WIDTH(x) (x & 0xffff)
281
282/* Status */
283#define GPT_STA_CAPTURE(x) (x & 0xffff)/* Read of internal counter */
284
285#define GPT_OVFPIN_OVF(x) (x & 0x70) /* Internal counter roll over */
286#define GPT_OVFPIN_PIN 0x01 /* Input pin - Timer 0 and 1 */
287
288#define GPT_INT_TEXP 0x08 /* Timer Expired in Internal Timer mode */
289#define GPT_INT_PWMP 0x04 /* PWM end of period occurred */
290#define GPT_INT_COMP 0x02 /* OC reference event occurred */
291#define GPT_INT_CAPT 0x01 /* IC reference event occurred */
292
293/* ------------------------------------------------------------------------ */
294/*
295 * Port configuration
296 */
297#define CFG_FEC1_PORT0_CONFIG 0x00000000
298#define CFG_FEC1_PORT1_CONFIG 0x00000000
299#define CFG_1284_PORT0_CONFIG 0x55555557
300#define CFG_1284_PORT1_CONFIG 0x80000000
301#define CFG_FEC2_PORT2_CONFIG 0x00000000
302#define CFG_PEV_PORT2_CONFIG 0x55555540
303#define CFG_GP0_PORT0_CONFIG 0xaaaaaaa0
304#define CFG_GP1_PORT2_CONFIG 0xaaaaa000
305#define CFG_PSC_PORT3_CONFIG 0x00000000
306#define CFG_CS2_PORT3_CONFIG 0x10000000
307#define CFG_CS3_PORT3_CONFIG 0x40000000
308#define CFG_CS4_PORT3_CONFIG 0x00000400
309#define CFG_CS5_PORT3_CONFIG 0x00000100
310#define CFG_I2C_PORT3_CONFIG 0x003c0000
311
312/* ------------------------------------------------------------------------ */
313/*
314 * DRAM configuration
315 */
316
317/* Field definitions for the control register */
318#define CTL_MODE_ENABLE_SHIFT 31
319#define CTL_CKE_SHIFT 30
320#define CTL_DDR_SHIFT 29
321#define CTL_REFRESH_SHIFT 28
322#define CTL_ADDRMUX_SHIFT 24
323#define CTL_PRECHARGE_SHIFT 23
324#define CTL_DRIVE_RULE_SHIFT 22
325#define CTL_REFRESH_INTERVAL_SHIFT 16
326#define CTL_DQSOEN_SHIFT 8
327#define CTL_BUFFERED_SHIFT 4
328#define CTL_REFRESH_CMD_SHIFT 2
329#define CTL_PRECHARGE_CMD_SHIFT 1
330
331#define CTL_MODE_ENABLE (1<<CTL_MODE_ENABLE_SHIFT)
332#define CTL_CKE_HIGH (1<<CTL_CKE_SHIFT)
333#define CTL_DDR_MODE (1<<CTL_DDR_SHIFT)
334#define CTL_REFRESH_ENABLE (1<<CTL_REFRESH_SHIFT)
335#define CTL_ADDRMUX(value) ((value)<<CTL_ADDRMUX_SHIFT)
336#define CTL_A8PRECHARGE (1<<CTL_PRECHARGE_SHIFT)
337#define CTL_REFRESH_INTERVAL(value) ((value)<<CTL_REFRESH_INTERVAL_SHIFT)
338#define CTL_DQSOEN(value) ((value)<<CTL_DQSOEN_SHIFT)
339#define CTL_BUFFERED (1<<CTL_BUFFERED_SHIFT)
340#define CTL_REFRESH_CMD (1<<CTL_REFRESH_CMD_SHIFT)
341#define CTL_PRECHARGE_CMD (1<<CTL_PRECHARGE_CMD_SHIFT)
342
343/* Field definitions for config register 1 */
344
345#define CFG1_SRD2RWP_SHIFT 28
346#define CFG1_SWT2RWP_SHIFT 24
347#define CFG1_RLATENCY_SHIFT 20
348#define CFG1_ACT2WR_SHIFT 16
349#define CFG1_PRE2ACT_SHIFT 12
350#define CFG1_REF2ACT_SHIFT 8
351#define CFG1_WLATENCY_SHIFT 4
352
353#define CFG1_SRD2RWP(value) ((value)<<CFG1_SRD2RWP_SHIFT)
354#define CFG1_SWT2RWP(value) ((value)<<CFG1_SWT2RWP_SHIFT)
355#define CFG1_RLATENCY(value) ((value)<<CFG1_RLATENCY_SHIFT)
356#define CFG1_ACT2WR(value) ((value)<<CFG1_ACT2WR_SHIFT)
357#define CFG1_PRE2ACT(value) ((value)<<CFG1_PRE2ACT_SHIFT)
358#define CFG1_REF2ACT(value) ((value)<<CFG1_REF2ACT_SHIFT)
359#define CFG1_WLATENCY(value) ((value)<<CFG1_WLATENCY_SHIFT)
360
361/* Field definitions for config register 2 */
362#define CFG2_BRD2RP_SHIFT 28
363#define CFG2_BWT2RWP_SHIFT 24
364#define CFG2_BRD2WT_SHIFT 20
365#define CFG2_BURSTLEN_SHIFT 16
366
367#define CFG2_BRD2RP(value) ((value)<<CFG2_BRD2RP_SHIFT)
368#define CFG2_BWT2RWP(value) ((value)<<CFG2_BWT2RWP_SHIFT)
369#define CFG2_BRD2WT(value) ((value)<<CFG2_BRD2WT_SHIFT)
370#define CFG2_BURSTLEN(value) ((value)<<CFG2_BURSTLEN_SHIFT)
371
372/* Field definitions for the mode/extended mode register - mode
373 * register access
374 */
375#define MODE_REG_SHIFT 30
376#define MODE_OPMODE_SHIFT 25
377#define MODE_CL_SHIFT 22
378#define MODE_BT_SHIFT 21
379#define MODE_BURSTLEN_SHIFT 18
380#define MODE_CMD_SHIFT 16
381
382#define MODE_MODE 0
383#define MODE_OPMODE(value) ((value)<<MODE_OPMODE_SHIFT)
384#define MODE_CL(value) ((value)<<MODE_CL_SHIFT)
385#define MODE_BT_INTERLEAVED (1<<MODE_BT_SHIFT)
386#define MODE_BT_SEQUENTIAL (0<<MODE_BT_SHIFT)
387#define MODE_BURSTLEN(value) ((value)<<MODE_BURSTLEN_SHIFT)
388#define MODE_CMD (1<<MODE_CMD_SHIFT)
389
390#define MODE_BURSTLEN_8 3
391#define MODE_BURSTLEN_4 2
392#define MODE_BURSTLEN_2 1
393
394#define MODE_CL_2 2
395#define MODE_CL_2p5 6
396#define MODE_OPMODE_NORMAL 0
397#define MODE_OPMODE_RESETDLL 2
398
399
400/* Field definitions for the mode/extended mode register - extended
401 * mode register access
402 */
403#define MODE_X_DLL_SHIFT 18 /* DLL enable/disable */
404#define MODE_X_DS_SHIFT 19 /* Drive strength normal/reduced */
405#define MODE_X_QFC_SHIFT 20 /* QFC function (whatever that is) */
406#define MODE_X_OPMODE_SHIFT 21
407
408#define MODE_EXTENDED (1<<MODE_REG_SHIFT)
409#define MODE_X_DLL_ENABLE 0
410#define MODE_X_DLL_DISABLE (1<<MODE_X_DLL_SHIFT)
411#define MODE_X_DS_NORMAL 0
412#define MODE_X_DS_REDUCED (1<<MODE_X_DS_SHIFT)
413#define MODE_X_QFC_DISABLED 0
414#define MODE_X_OPMODE(value) ((value)<<MODE_X_OPMODE_SHIFT)
415
416#ifndef __ASSEMBLY__
417/*
418 * DMA control/status registers.
419 */
420struct mpc8220_dma {
421 u32 taskBar; /* DMA + 0x00 */
422 u32 currentPointer; /* DMA + 0x04 */
423 u32 endPointer; /* DMA + 0x08 */
424 u32 variablePointer;/* DMA + 0x0c */
425
426 u8 IntVect1; /* DMA + 0x10 */
427 u8 IntVect2; /* DMA + 0x11 */
428 u16 PtdCntrl; /* DMA + 0x12 */
429
430 u32 IntPend; /* DMA + 0x14 */
431 u32 IntMask; /* DMA + 0x18 */
432
433 u16 tcr_0; /* DMA + 0x1c */
434 u16 tcr_1; /* DMA + 0x1e */
435 u16 tcr_2; /* DMA + 0x20 */
436 u16 tcr_3; /* DMA + 0x22 */
437 u16 tcr_4; /* DMA + 0x24 */
438 u16 tcr_5; /* DMA + 0x26 */
439 u16 tcr_6; /* DMA + 0x28 */
440 u16 tcr_7; /* DMA + 0x2a */
441 u16 tcr_8; /* DMA + 0x2c */
442 u16 tcr_9; /* DMA + 0x2e */
443 u16 tcr_a; /* DMA + 0x30 */
444 u16 tcr_b; /* DMA + 0x32 */
445 u16 tcr_c; /* DMA + 0x34 */
446 u16 tcr_d; /* DMA + 0x36 */
447 u16 tcr_e; /* DMA + 0x38 */
448 u16 tcr_f; /* DMA + 0x3a */
449
450 u8 IPR0; /* DMA + 0x3c */
451 u8 IPR1; /* DMA + 0x3d */
452 u8 IPR2; /* DMA + 0x3e */
453 u8 IPR3; /* DMA + 0x3f */
454 u8 IPR4; /* DMA + 0x40 */
455 u8 IPR5; /* DMA + 0x41 */
456 u8 IPR6; /* DMA + 0x42 */
457 u8 IPR7; /* DMA + 0x43 */
458 u8 IPR8; /* DMA + 0x44 */
459 u8 IPR9; /* DMA + 0x45 */
460 u8 IPR10; /* DMA + 0x46 */
461 u8 IPR11; /* DMA + 0x47 */
462 u8 IPR12; /* DMA + 0x48 */
463 u8 IPR13; /* DMA + 0x49 */
464 u8 IPR14; /* DMA + 0x4a */
465 u8 IPR15; /* DMA + 0x4b */
466 u8 IPR16; /* DMA + 0x4c */
467 u8 IPR17; /* DMA + 0x4d */
468 u8 IPR18; /* DMA + 0x4e */
469 u8 IPR19; /* DMA + 0x4f */
470 u8 IPR20; /* DMA + 0x50 */
471 u8 IPR21; /* DMA + 0x51 */
472 u8 IPR22; /* DMA + 0x52 */
473 u8 IPR23; /* DMA + 0x53 */
474 u8 IPR24; /* DMA + 0x54 */
475 u8 IPR25; /* DMA + 0x55 */
476 u8 IPR26; /* DMA + 0x56 */
477 u8 IPR27; /* DMA + 0x57 */
478 u8 IPR28; /* DMA + 0x58 */
479 u8 IPR29; /* DMA + 0x59 */
480 u8 IPR30; /* DMA + 0x5a */
481 u8 IPR31; /* DMA + 0x5b */
482
483 u32 res1; /* DMA + 0x5c */
484 u32 res2; /* DMA + 0x60 */
485 u32 res3; /* DMA + 0x64 */
486 u32 MDEDebug; /* DMA + 0x68 */
487 u32 ADSDebug; /* DMA + 0x6c */
488 u32 Value1; /* DMA + 0x70 */
489 u32 Value2; /* DMA + 0x74 */
490 u32 Control; /* DMA + 0x78 */
491 u32 Status; /* DMA + 0x7c */
492 u32 EU00; /* DMA + 0x80 */
493 u32 EU01; /* DMA + 0x84 */
494 u32 EU02; /* DMA + 0x88 */
495 u32 EU03; /* DMA + 0x8c */
496 u32 EU04; /* DMA + 0x90 */
497 u32 EU05; /* DMA + 0x94 */
498 u32 EU06; /* DMA + 0x98 */
499 u32 EU07; /* DMA + 0x9c */
500 u32 EU10; /* DMA + 0xa0 */
501 u32 EU11; /* DMA + 0xa4 */
502 u32 EU12; /* DMA + 0xa8 */
503 u32 EU13; /* DMA + 0xac */
504 u32 EU14; /* DMA + 0xb0 */
505 u32 EU15; /* DMA + 0xb4 */
506 u32 EU16; /* DMA + 0xb8 */
507 u32 EU17; /* DMA + 0xbc */
508 u32 EU20; /* DMA + 0xc0 */
509 u32 EU21; /* DMA + 0xc4 */
510 u32 EU22; /* DMA + 0xc8 */
511 u32 EU23; /* DMA + 0xcc */
512 u32 EU24; /* DMA + 0xd0 */
513 u32 EU25; /* DMA + 0xd4 */
514 u32 EU26; /* DMA + 0xd8 */
515 u32 EU27; /* DMA + 0xdc */
516 u32 EU30; /* DMA + 0xe0 */
517 u32 EU31; /* DMA + 0xe4 */
518 u32 EU32; /* DMA + 0xe8 */
519 u32 EU33; /* DMA + 0xec */
520 u32 EU34; /* DMA + 0xf0 */
521 u32 EU35; /* DMA + 0xf4 */
522 u32 EU36; /* DMA + 0xf8 */
523 u32 EU37; /* DMA + 0xfc */
524};
525
526
527/* function prototypes */
528void loadtask(int basetask, int tasks);
529u32 dramSetup(void);
530
531#if defined(CONFIG_PSC_CONSOLE)
532int psc_serial_init (void);
533void psc_serial_putc(const char c);
534void psc_serial_puts (const char *s);
535int psc_serial_getc(void);
536int psc_serial_tstc(void);
537void psc_serial_setbrg(void);
538#endif
539
540#if defined (CONFIG_EXTUART_CONSOLE)
541int ext_serial_init (void);
542void ext_serial_putc(const char c);
543void ext_serial_puts (const char *s);
544int ext_serial_getc(void);
545int ext_serial_tstc(void);
546void ext_serial_setbrg(void);
547#endif
548
549#endif /* __ASSEMBLY__ */
550
551#endif /* __MPC8220_H__ */