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git01.mediatek.com / filogic / uboot / e8c47f4bd9ccc3b0db50b10380e3180d6ec9ec2c / . / include / configs / xm250.h
blob: 825bfd14e93bb5e9646880872a002381fe58e1f3 [file] [log] [blame]
wdenkc12081a2004-03-23 20:18:25 +0000[diff] [blame]1/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
wdenkc12081a2004-03-23 20:18:25 +0000[diff] [blame]32 * High Level Configuration Options
33 * (easy to change)
34 */
35#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
36#define CONFIG_XM250 1 /* on a MicroSys XM250 Board */
37#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
38
39/*
40 * Size of malloc() pool; this lives below the uppermost 128 KiB which are
41 * used for the RAM copy of the uboot code
42 *
43 */
44#define CFG_MALLOC_LEN (256*1024)
45#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
46
47/*
48 * Hardware drivers
49 */
50#define CONFIG_DRIVER_SMC91111
51#define CONFIG_SMC91111_BASE 0x04000300
52#undef CONFIG_SMC91111_EXT_PHY
53#define CONFIG_SMC_USE_32_BIT
54#undef CONFIG_SHOW_ACTIVITY
55#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
56
57/*
58 * I2C bus
59 */
60#define CONFIG_HARD_I2C 1
61#define CFG_I2C_SPEED 50000
62#define CFG_I2C_SLAVE 0xfe
63
64#define CONFIG_RTC_PCF8563 1
65#define CFG_I2C_RTC_ADDR 0x51
66
67#define CFG_I2C_EEPROM_ADDR 0x58 /* A0 = 0 (hardwired) */
68#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 4 bits = 16 octets */
69#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */
70#define CFG_I2C_EEPROM_ADDR_LEN 1 /* length of address */
71#define CFG_EEPROM_SIZE 2048 /* size in bytes */
72#undef CFG_I2C_INIT_BOARD /* board has no own init */
73
74/*
75 * select serial console configuration
76 */
77#define CONFIG_FFUART 1 /* we use FFUART */
78
79/* allow to overwrite serial and ethaddr */
80#define CONFIG_ENV_OVERWRITE
81
82#define CONFIG_BAUDRATE 115200
83
84#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
85 CFG_CMD_ELF | \
86 CFG_CMD_EEPROM | \
87 CFG_CMD_DATE | \
88 CFG_CMD_I2C )
89
90/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
91#include <cmd_confdefs.h>
92
93#define CONFIG_BOOTDELAY 3
94
95/*
96 * Miscellaneous configurable options
97 */
98#define CFG_LONGHELP /* undef to save memory */
99#define CFG_PROMPT "=> " /* Monitor Command Prompt */
100#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
101#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
102#define CFG_MAXARGS 16 /* max number of command args */
103#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
104
105#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
106#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
107
108#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
109
110#define CFG_LOAD_ADDR 0xa3000000 /* default load address */
111
112#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
113#define CFG_CPUSPEED 0x161 /* set core clock to 400/400/100 MHz */
114
115 /* valid baudrates */
116
117#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
118
119/*
120 * Definitions related to passing arguments to kernel.
121 */
Wolfgang Denk815c72e2006-07-21 11:36:48 +0200[diff] [blame]122#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
123#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
124#define CONFIG_INITRD_TAG 1 /* do not send initrd params */
wdenkc12081a2004-03-23 20:18:25 +0000[diff] [blame]125#undef CONFIG_VFD /* do not send framebuffer setup */
126
127/*
128 * Stack sizes
129 *
130 * The stack sizes are set up in start.S using the settings below
131 */
132#define CONFIG_STACKSIZE (128*1024) /* regular stack */
133#ifdef CONFIG_USE_IRQ
134#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
135#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
136#endif
137
138/*
139 * Physical Memory Map
140 */
141#define CONFIG_NR_DRAM_BANKS 4
142#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
143#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
144#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
145#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
146#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
147#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
148#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
149#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
150
151#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
152#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
153#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
154#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
155#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
156
157#define CFG_DRAM_BASE 0xa0000000
158#define CFG_DRAM_SIZE 0x04000000
159
160#define CFG_FLASH_BASE PHYS_FLASH_1
161
162/*
163 * FLASH and environment organization
164 */
165#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
166#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
167
168/* timeout values are in ticks */
169#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
170#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
171#define CFG_FLASH_LOCK_TOUT (2*CFG_HZ) /* Timeout for Flash Set Lock Bit */
172#define CFG_FLASH_UNLOCK_TOUT (2*CFG_HZ) /* Timeout for Flash Clear Lock Bits */
173#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
174
175#define CFG_ENV_IS_IN_FLASH 1
176#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector */
177#define CFG_ENV_SIZE 0x4000
178#define CFG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
179#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
180
181/******************************************************************************
182 *
183 * CPU specific defines
184 *
185 ******************************************************************************/
186
187/*
188 * GPIO settings
189 *
190 * GPIO pin assignments
191 * GPIO Name Dir Out AF
192 * 0 NC
193 * 1 NC
194 * 2 SIRQ1 I
195 * 3 SIRQ2 I
196 * 4 SIRQ3 I
197 * 5 DMAACK1 O 0
198 * 6 DMAACK2 O 0
199 * 7 DMAACK3 O 0
200 * 8 TC1 O 0
201 * 9 TC2 O 0
202 * 10 TC3 O 0
203 * 11 nDMAEN O 1
204 * 12 AENCTRL O 0
205 * 13 PLDTC O 0
206 * 14 ETHIRQ I
207 * 15 NC
208 * 16 NC
209 * 17 NC
210 * 18 RDY I
211 * 19 DMASIO I
212 * 20 ETHIRQ NC
213 * 21 NC
214 * 22 PGMEN O 1 FIXME for debug only enable flash
215 * 23 NC
216 * 24 NC
217 * 25 NC
218 * 26 NC
219 * 27 NC
220 * 28 NC
221 * 29 NC
222 * 30 NC
223 * 31 NC
224 * 32 NC
225 * 33 NC
226 * 34 FFRXD I 01
227 * 35 FFCTS I 01
228 * 36 FFDCD I 01
229 * 37 FFDSR I 01
230 * 38 FFRI I 01
231 * 39 FFTXD O 1 10
232 * 40 FFDTR O 0 10
233 * 41 FFRTS O 0 10
234 * 42 RS232FOFF O 0 00
235 * 43 NC
236 * 44 NC
237 * 45 IRSL0 O 0
238 * 46 IRRX0 I 01
239 * 47 IRTX0 O 0 10
240 * 48 NC
241 * 49 nIOWE O 0
242 * 50 NC
243 * 51 NC
244 * 52 NC
245 * 53 NC
246 * 54 NC
247 * 55 NC
248 * 56 NC
249 * 57 NC
250 * 58 DKDIRQ I
251 * 59 NC
252 * 60 NC
253 * 61 NC
254 * 62 NC
255 * 63 NC
256 * 64 COMLED O 0
257 * 65 COMLED O 0
258 * 66 COMLED O 0
259 * 67 COMLED O 0
260 * 68 COMLED O 0
261 * 69 COMLED O 0
262 * 70 COMLED O 0
263 * 71 COMLED O 0
264 * 72 NC
265 * 73 NC
266 * 74 NC
267 * 75 NC
268 * 76 NC
269 * 77 NC
270 * 78 CSIO O 1
271 * 79 NC
272 * 80 CSETH O 1
273 *
274 * NOTE: All NC's are defined to be outputs
275 *
276 */
277/* Pin direction control */
278#define CFG_GPDR0_VAL 0xd3808000
279#define CFG_GPDR1_VAL 0xfcffab83
280#define CFG_GPDR2_VAL 0x0001ffff
281/* Set and Clear registers */
282#define CFG_GPSR0_VAL 0x00008000
283#define CFG_GPSR1_VAL 0x00ff0002
284#define CFG_GPSR2_VAL 0x0001c000
285#define CFG_GPCR0_VAL 0x00000000
286#define CFG_GPCR1_VAL 0x00000000
287#define CFG_GPCR2_VAL 0x00000000
288/* Edge detect registers (these are set by the kernel) */
289#define CFG_GRER0_VAL 0x00002180
290#define CFG_GRER1_VAL 0x00000000
291#define CFG_GRER2_VAL 0x00000000
292#define CFG_GFER0_VAL 0x000043e0
293#define CFG_GFER1_VAL 0x00000000
294#define CFG_GFER2_VAL 0x00000000
295/* Alternate function registers */
296#define CFG_GAFR0_L_VAL 0x80000004
297#define CFG_GAFR0_U_VAL 0x595a8010
298#define CFG_GAFR1_L_VAL 0x699a9559
299#define CFG_GAFR1_U_VAL 0xaaa5aaaa
300#define CFG_GAFR2_L_VAL 0xaaaaaaaa
301#define CFG_GAFR2_U_VAL 0x00000002
302
303/*
304 * Clocks, power control and interrupts
305 */
306#define CFG_PSSR_VAL 0x00000030
307#define CFG_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */
308#define CFG_CKEN_VAL 0x000141ec /* FFUART and STUART enabled */
309#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */
310
311/* FIXME
312 *
313 * RTC settings
314 * Watchdog
315 *
316 */
317
318/*
319 * Memory settings
320 *
321 */
322#define CFG_MSC0_VAL 0x122423f0 /* FLASH / LAN (cs0)/(cS1) */
323#define CFG_MSC1_VAL 0x35f4aa4c /* USB / ST3+ST5 (cs2)/(cS3) */
324#define CFG_MSC2_VAL 0x35f435fc /* IDE / BCR + WatchDog (cs4)/(cS5) */
325#define CFG_MDCNFG_VAL 0x000009c9
326#define CFG_MDMRS_VAL 0x00220022
wdenk336b2bc2005-04-02 23:52:25 +0000[diff] [blame]327#define CFG_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in lowlevel_init.S */
wdenkc12081a2004-03-23 20:18:25 +0000[diff] [blame]328
329/*
330 * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
331 */
332#define CFG_MECR_VAL 0x00000000
333#define CFG_MCMEM0_VAL 0x00010504
334#define CFG_MCMEM1_VAL 0x00010504
335#define CFG_MCATT0_VAL 0x00010504
336#define CFG_MCATT1_VAL 0x00010504
337#define CFG_MCIO0_VAL 0x00004715
338#define CFG_MCIO1_VAL 0x00004715
339
340/* Board specific defines */
341
342#ifndef __ASSEMBLY__
343
344/* global prototypes */
345void led_code(int code, int color);
346
347#endif
348
349#endif /* __CONFIG_H */