| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* |
| 3 | * MPC8544 DS Device Tree Source |
| 4 | * |
| 5 | * Copyright 2007, 2008 Freescale Semiconductor Inc. |
| 6 | */ |
| 7 | |
| 8 | /include/ "mpc8544si-pre.dtsi" |
| 9 | |
| 10 | / { |
| 11 | model = "MPC8544DS"; |
| 12 | compatible = "MPC8544DS", "MPC85xxDS"; |
| 13 | |
| 14 | memory { |
| 15 | device_type = "memory"; |
| 16 | reg = <0 0 0 0>; // Filled by U-Boot |
| 17 | }; |
| 18 | |
| 19 | board_lbc: lbc: localbus@e0005000 { |
| 20 | reg = <0 0xe0005000 0 0x1000>; |
| 21 | |
| 22 | ranges = <0x0 0x0 0x0 0xff800000 0x800000>; |
| 23 | }; |
| 24 | |
| 25 | board_soc: soc: soc8544@e0000000 { |
| 26 | ranges = <0x0 0x0 0xe0000000 0x100000>; |
| 27 | }; |
| 28 | |
| 29 | pci0: pci@e0008000 { |
| 30 | reg = <0 0xe0008000 0 0x1000>; |
| 31 | ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 |
| 32 | 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>; |
| 33 | clock-frequency = <66666666>; |
| 34 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
| 35 | interrupt-map = < |
| 36 | |
| 37 | /* IDSEL 0x11 J17 Slot 1 */ |
| 38 | 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 |
| 39 | 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 |
| 40 | 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0 |
| 41 | 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 |
| 42 | |
| 43 | /* IDSEL 0x12 J16 Slot 2 */ |
| 44 | |
| 45 | 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0 |
| 46 | 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0 |
| 47 | 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 |
| 48 | 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0>; |
| 49 | }; |
| 50 | |
| 51 | pci1: pcie@e0009000 { |
| 52 | reg = <0x0 0xe0009000 0x0 0x1000>; |
| 53 | ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 |
| 54 | 0x1000000 0x0 0x00000000 0 0xe1010000 0x0 0x10000>; |
| 55 | pcie@0 { |
| 56 | ranges = <0x2000000 0x0 0x80000000 |
| 57 | 0x2000000 0x0 0x80000000 |
| 58 | 0x0 0x20000000 |
| 59 | |
| 60 | 0x1000000 0x0 0x0 |
| 61 | 0x1000000 0x0 0x0 |
| 62 | 0x0 0x10000>; |
| 63 | }; |
| 64 | }; |
| 65 | |
| 66 | pci2: pcie@e000a000 { |
| 67 | reg = <0x0 0xe000a000 0x0 0x1000>; |
| 68 | ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000 |
| 69 | 0x1000000 0x0 0x00000000 0 0xe1020000 0x0 0x10000>; |
| 70 | pcie@0 { |
| 71 | ranges = <0x2000000 0x0 0xa0000000 |
| 72 | 0x2000000 0x0 0xa0000000 |
| 73 | 0x0 0x10000000 |
| 74 | |
| 75 | 0x1000000 0x0 0x0 |
| 76 | 0x1000000 0x0 0x0 |
| 77 | 0x0 0x10000>; |
| 78 | }; |
| 79 | }; |
| 80 | |
| 81 | board_pci3: pci3: pcie@e000b000 { |
| 82 | reg = <0x0 0xe000b000 0x0 0x1000>; |
| 83 | ranges = <0x2000000 0x0 0xb0000000 0 0xb0000000 0x0 0x100000 |
| 84 | 0x1000000 0x0 0x00000000 0 0xb0100000 0x0 0x100000>; |
| 85 | pcie@0 { |
| 86 | ranges = <0x2000000 0x0 0xb0000000 |
| 87 | 0x2000000 0x0 0xb0000000 |
| 88 | 0x0 0x100000 |
| 89 | |
| 90 | 0x1000000 0x0 0x0 |
| 91 | 0x1000000 0x0 0x0 |
| 92 | 0x0 0x100000>; |
| 93 | }; |
| 94 | }; |
| 95 | }; |
| 96 | |
| 97 | /* |
| 98 | * mpc8544ds.dtsi must be last to ensure board_pci3 overrides pci3 settings |
| 99 | * for interrupt-map & interrupt-map-mask |
| 100 | */ |
| 101 | |
| 102 | /include/ "mpc8544si-post.dtsi" |
| 103 | /include/ "mpc8544ds.dtsi" |