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git01.mediatek.com / filogic / uboot / e8c089bccddbe51c9380d1a3018b432d57f8d6df / . / arch / sh / include / asm / cpu_sh7752.h
blob: f084ed8e34f22786e198a5215ca39d32ae19c3e2 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Yoshihiro Shimoda07fecef2012-11-04 15:53:22 +0000[diff] [blame]2/*
3 * Copyright (C) 2012 Renesas Solutions Corp.
Yoshihiro Shimoda07fecef2012-11-04 15:53:22 +0000[diff] [blame]4 */
5
6#ifndef _ASM_CPU_SH7752_H_
7#define _ASM_CPU_SH7752_H_
8
9#define CCR 0xFF00001C
10#define WTCNT 0xFFCC0000
11#define CCR_CACHE_INIT 0x0000090b
12#define CACHE_OC_NUM_WAYS 1
13
14#ifndef __ASSEMBLY__ /* put C only stuff in this section */
15/* MMU */
16struct mmu_regs {
17 unsigned int reserved[4];
18 unsigned int mmucr;
19};
20#define MMU_BASE ((struct mmu_regs *)0xff000000)
21
22/* Watchdog */
23#define WTCSR0 0xffcc0002
24#define WRSTCSR_R 0xffcc0003
25#define WRSTCSR_W 0xffcc0002
26#define WTCSR_PREFIX 0xa500
27#define WRSTCSR_PREFIX 0x6900
28#define WRSTCSR_WOVF_PREFIX 0x9600
29
30/* SCIF */
31#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */
32#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */
33#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */
34
35/* TMU0 */
36#define TMU_BASE 0xFE430000
37
38/* ETHER, GETHER MAC address */
39struct ether_mac_regs {
40 unsigned int reserved[114];
41 unsigned int mahr;
42 unsigned int reserved2;
43 unsigned int malr;
44};
45#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400)
46#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00)
47#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000)
48#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800)
49
50/* GETHER */
51struct gether_control_regs {
52 unsigned int gbecont;
53};
54#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100)
55#define GBECONT_RMII1 0x00020000
56#define GBECONT_RMII0 0x00010000
57
58/* SerMux */
59struct sermux_regs {
60 unsigned char smr0;
61 unsigned char smr1;
62 unsigned char smr2;
63 unsigned char smr3;
64 unsigned char smr4;
65 unsigned char smr5;
66};
67#define SERMUX_BASE ((struct sermux_regs *)0xfe470000)
68
Yoshihiro Shimoda07fecef2012-11-04 15:53:22 +0000[diff] [blame]69/* USB0/1 */
70struct usb_common_regs {
71 unsigned short reserved[129];
72 unsigned short suspmode;
73};
74#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000)
75#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000)
76
77struct usb0_phy_regs {
78 unsigned short reset;
79 unsigned short reserved[4];
80 unsigned short portsel;
81};
82#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000)
83
84struct usb1_port_regs {
85 unsigned int port1sel;
86 unsigned int reserved;
87 unsigned int usb1intsts;
88};
89#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000)
90
91struct usb1_alignment_regs {
92 unsigned int ehcidatac; /* 0xfe4fe018 */
93 unsigned int reserved[63];
94 unsigned int ohcidatac;
95};
96#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018)
97
98/* GPIO */
99struct gpio_regs {
100 unsigned short pacr;
101 unsigned short pbcr;
102 unsigned short pccr;
103 unsigned short pdcr;
104 unsigned short pecr;
105 unsigned short pfcr;
106 unsigned short pgcr;
107 unsigned short phcr;
108 unsigned short picr;
109 unsigned short pjcr;
110 unsigned short pkcr;
111 unsigned short plcr;
112 unsigned short pmcr;
113 unsigned short pncr;
114 unsigned short pocr;
115 unsigned short reserved;
116 unsigned short pqcr;
117 unsigned short prcr;
118 unsigned short pscr;
119 unsigned short ptcr;
120 unsigned short pucr;
121 unsigned short pvcr;
122 unsigned short pwcr;
123 unsigned short pxcr;
124 unsigned short pycr;
125 unsigned short pzcr;
126 unsigned char padr;
127 unsigned char reserved_a;
128 unsigned char pbdr;
129 unsigned char reserved_b;
130 unsigned char pcdr;
131 unsigned char reserved_c;
132 unsigned char pddr;
133 unsigned char reserved_d;
134 unsigned char pedr;
135 unsigned char reserved_e;
136 unsigned char pfdr;
137 unsigned char reserved_f;
138 unsigned char pgdr;
139 unsigned char reserved_g;
140 unsigned char phdr;
141 unsigned char reserved_h;
142 unsigned char pidr;
143 unsigned char reserved_i;
144 unsigned char pjdr;
145 unsigned char reserved_j;
146 unsigned char pkdr;
147 unsigned char reserved_k;
148 unsigned char pldr;
149 unsigned char reserved_l;
150 unsigned char pmdr;
151 unsigned char reserved_m;
152 unsigned char pndr;
153 unsigned char reserved_n;
154 unsigned char podr;
155 unsigned char reserved_o;
156 unsigned char ppdr;
157 unsigned char reserved_p;
158 unsigned char pqdr;
159 unsigned char reserved_q;
160 unsigned char prdr;
161 unsigned char reserved_r;
162 unsigned char psdr;
163 unsigned char reserved_s;
164 unsigned char ptdr;
165 unsigned char reserved_t;
166 unsigned char pudr;
167 unsigned char reserved_u;
168 unsigned char pvdr;
169 unsigned char reserved_v;
170 unsigned char pwdr;
171 unsigned char reserved_w;
172 unsigned char pxdr;
173 unsigned char reserved_x;
174 unsigned char pydr;
175 unsigned char reserved_y;
176 unsigned char pzdr;
177 unsigned char reserved_z;
178 unsigned short ncer;
179 unsigned short ncmcr;
180 unsigned short nccsr;
181 unsigned char reserved2[2];
182 unsigned short psel0; /* +0x70 */
183 unsigned short psel1;
184 unsigned short psel2;
185 unsigned short psel3;
186 unsigned short psel4;
187 unsigned short psel5;
188 unsigned short psel6;
189 unsigned short reserved3[2];
190 unsigned short psel7;
191};
192#define GPIO_BASE ((struct gpio_regs *)0xffec0000)
193
194#endif /* ifndef __ASSEMBLY__ */
195#endif /* _ASM_CPU_SH7752_H_ */