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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: BSD-3-Clause */
Pavel Machekc7213802014-09-08 14:08:45 +02002/*
Tien Fong Chee31e50f42017-07-26 13:05:38 +08003 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
Pavel Machekc7213802014-09-08 14:08:45 +02004 * All rights reserved.
Pavel Machekc7213802014-09-08 14:08:45 +02005 */
6
7#ifndef _FPGA_MANAGER_H_
8#define _FPGA_MANAGER_H_
9
10#include <altera.h>
11
Tien Fong Chee31e50f42017-07-26 13:05:38 +080012#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
13#include <asm/arch/fpga_manager_gen5.h>
Tien Fong Chee1d675f32017-07-26 13:05:43 +080014#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
15#include <asm/arch/fpga_manager_arria10.h>
Tien Fong Chee31e50f42017-07-26 13:05:38 +080016#endif
Pavel Machekc7213802014-09-08 14:08:45 +020017
18/* FPGA CD Ratio Value */
19#define CDRATIO_x1 0x0
20#define CDRATIO_x2 0x1
21#define CDRATIO_x4 0x2
22#define CDRATIO_x8 0x3
23
Tien Fong Chee31e50f42017-07-26 13:05:38 +080024#ifndef __ASSEMBLY__
25
26/* Common prototypes */
Pavel Machekc7213802014-09-08 14:08:45 +020027int fpgamgr_get_mode(void);
Tien Fong Chee31e50f42017-07-26 13:05:38 +080028int fpgamgr_poll_fpga_ready(void);
29void fpgamgr_program_write(const void *rbf_data, size_t rbf_size);
30int fpgamgr_test_fpga_ready(void);
31int fpgamgr_dclkcnt_set(unsigned long cnt);
Pavel Machekc7213802014-09-08 14:08:45 +020032
Tien Fong Chee31e50f42017-07-26 13:05:38 +080033#endif /* __ASSEMBLY__ */
Pavel Machekc7213802014-09-08 14:08:45 +020034#endif /* _FPGA_MANAGER_H_ */