blob: b173c9c502736676bf84f4e6ed3daa6aee66f0ad [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -05002/*
3 * pci.c -- WindRiver SBC8349 PCI board support.
4 * Copyright (c) 2006 Wind River Systems, Inc.
Kim Phillips57a2af32009-07-18 18:42:13 -05005 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -05006 *
7 * Based on MPC8349 PCI support but w/o PIB related code.
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -05008 */
9
10#include <asm/mmu.h>
Kim Phillips57a2af32009-07-18 18:42:13 -050011#include <asm/io.h>
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050012#include <common.h>
Kim Phillips57a2af32009-07-18 18:42:13 -050013#include <mpc83xx.h>
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050014#include <pci.h>
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050015#include <i2c.h>
Kim Phillips57a2af32009-07-18 18:42:13 -050016#include <asm/fsl_i2c.h>
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050017
Kim Phillips57a2af32009-07-18 18:42:13 -050018static struct pci_region pci1_regions[] = {
19 {
20 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
21 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
22 size: CONFIG_SYS_PCI1_MEM_SIZE,
23 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050024 },
Kim Phillips57a2af32009-07-18 18:42:13 -050025 {
26 bus_start: CONFIG_SYS_PCI1_IO_BASE,
27 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
28 size: CONFIG_SYS_PCI1_IO_SIZE,
29 flags: PCI_REGION_IO
30 },
31 {
32 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
33 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
34 size: CONFIG_SYS_PCI1_MMIO_SIZE,
35 flags: PCI_REGION_MEM
36 },
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050037};
38
Kim Phillips57a2af32009-07-18 18:42:13 -050039/*
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050040 * pci_init_board()
41 *
42 * NOTICE: PCI2 is not supported. There is only one
43 * physical PCI slot on the board.
44 *
45 */
46void
47pci_init_board(void)
48{
Kim Phillips57a2af32009-07-18 18:42:13 -050049 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
50 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
51 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
52 struct pci_region *reg[] = { pci1_regions };
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050053
Kim Phillips57a2af32009-07-18 18:42:13 -050054 /* Enable all 8 PCI_CLK_OUTPUTS */
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050055 clk->occr = 0xff000000;
56 udelay(2000);
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050057
Kim Phillips57a2af32009-07-18 18:42:13 -050058 /* Configure PCI Local Access Windows */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020059 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050060 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
61
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020062 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050063 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
64
Kim Phillips57a2af32009-07-18 18:42:13 -050065 udelay(2000);
Kim Phillipsfd47a742007-12-20 14:09:22 -060066
Peter Tysere2283322010-09-14 19:13:50 -050067 mpc83xx_pci_init(1, reg);
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -050068}