Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Tom Warren | 22425c9 | 2015-02-12 15:01:49 -0700 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2013-2015 |
| 4 | * NVIDIA Corporation <www.nvidia.com> |
Tom Warren | 22425c9 | 2015-02-12 15:01:49 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _TEGRA210_COMMON_H_ |
| 8 | #define _TEGRA210_COMMON_H_ |
| 9 | |
| 10 | #include "tegra-common.h" |
| 11 | |
Tom Warren | 22425c9 | 2015-02-12 15:01:49 -0700 | [diff] [blame] | 12 | /* |
| 13 | * NS16550 Configuration |
| 14 | */ |
| 15 | #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ |
| 16 | |
Tom Warren | 22425c9 | 2015-02-12 15:01:49 -0700 | [diff] [blame] | 17 | /* |
| 18 | * Memory layout for where various images get loaded by boot scripts: |
| 19 | * |
| 20 | * scriptaddr can be pretty much anywhere that doesn't conflict with something |
| 21 | * else. Put it above BOOTMAPSZ to eliminate conflicts. |
| 22 | * |
| 23 | * pxefile_addr_r can be pretty much anywhere that doesn't conflict with |
| 24 | * something else. Put it above BOOTMAPSZ to eliminate conflicts. |
| 25 | * |
| 26 | * kernel_addr_r must be within the first 128M of RAM in order for the |
| 27 | * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will |
| 28 | * decompress itself to 0x8000 after the start of RAM, kernel_addr_r |
| 29 | * should not overlap that area, or the kernel will have to copy itself |
| 30 | * somewhere else before decompression. Similarly, the address of any other |
| 31 | * data passed to the kernel shouldn't overlap the start of RAM. Pushing |
| 32 | * this up to 16M allows for a sizable kernel to be decompressed below the |
| 33 | * compressed load address. |
| 34 | * |
| 35 | * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for |
| 36 | * the compressed kernel to be up to 16M too. |
| 37 | * |
| 38 | * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows |
| 39 | * for the FDT/DTB to be up to 1M, which is hopefully plenty. |
| 40 | */ |
Tom Warren | 22425c9 | 2015-02-12 15:01:49 -0700 | [diff] [blame] | 41 | #define MEM_LAYOUT_ENV_SETTINGS \ |
| 42 | "scriptaddr=0x90000000\0" \ |
| 43 | "pxefile_addr_r=0x90100000\0" \ |
Tom Rini | 9004ee0 | 2021-08-23 10:25:30 -0400 | [diff] [blame] | 44 | "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ |
Peter Robinson | 637ac01 | 2020-04-02 00:28:54 +0100 | [diff] [blame] | 45 | "fdtfile=" FDTFILE "\0" \ |
Tom Warren | fbb4771 | 2020-03-16 17:01:43 -0700 | [diff] [blame] | 46 | "fdt_addr_r=0x83000000\0" \ |
| 47 | "ramdisk_addr_r=0x83200000\0" |
Tom Warren | 22425c9 | 2015-02-12 15:01:49 -0700 | [diff] [blame] | 48 | |
Tom Warren | 22425c9 | 2015-02-12 15:01:49 -0700 | [diff] [blame] | 49 | /* For USB EHCI controller */ |
| 50 | #define CONFIG_EHCI_IS_TDI |
| 51 | #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 |
Tom Warren | 22425c9 | 2015-02-12 15:01:49 -0700 | [diff] [blame] | 52 | |
Alexandre Courbot | 7f936d4 | 2015-07-09 16:33:00 +0900 | [diff] [blame] | 53 | /* GPU needs setup */ |
| 54 | #define CONFIG_TEGRA_GPU |
| 55 | |
Tom Warren | 22425c9 | 2015-02-12 15:01:49 -0700 | [diff] [blame] | 56 | #endif /* _TEGRA210_COMMON_H_ */ |