blob: e67dee0f00b9c6be5570d9b3df6262810b3050db [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
York Sun03017032015-03-20 19:28:23 -07002/*
Yangbo Lubb32e682021-06-03 10:51:19 +08003 * Copyright 2017, 2019-2021 NXP
York Sun03017032015-03-20 19:28:23 -07004 * Copyright 2015 Freescale Semiconductor
York Sun03017032015-03-20 19:28:23 -07005 */
6
7#ifndef __LS2_QDS_H
8#define __LS2_QDS_H
9
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053010#include "ls2080a_common.h"
York Sun03017032015-03-20 19:28:23 -070011
York Sun03017032015-03-20 19:28:23 -070012#ifndef __ASSEMBLY__
13unsigned long get_board_sys_clk(void);
York Sun03017032015-03-20 19:28:23 -070014#endif
15
Yuan Yao5a89cce2016-06-08 18:24:54 +080016#ifdef CONFIG_FSL_QSPI
Yuan Yao5a89cce2016-06-08 18:24:54 +080017#define CONFIG_QIXIS_I2C_ACCESS
Yuan Yao5a89cce2016-06-08 18:24:54 +080018#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
19#endif
20
21#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
York Sun03017032015-03-20 19:28:23 -070022#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
York Sun03017032015-03-20 19:28:23 -070023#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
24
York Sun03017032015-03-20 19:28:23 -070025#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
26#define SPD_EEPROM_ADDRESS1 0x51
27#define SPD_EEPROM_ADDRESS2 0x52
28#define SPD_EEPROM_ADDRESS3 0x53
29#define SPD_EEPROM_ADDRESS4 0x54
30#define SPD_EEPROM_ADDRESS5 0x55
31#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
32#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
33#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
34#define CONFIG_DIMM_SLOTS_PER_CTLR 2
35#define CONFIG_CHIP_SELECTS_PER_CTRL 4
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053036#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Sun03017032015-03-20 19:28:23 -070037#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053038#endif
York Sun03017032015-03-20 19:28:23 -070039
Tang Yuantian57894be2015-12-09 15:32:18 +080040/* SATA */
Tang Yuantian57894be2015-12-09 15:32:18 +080041#define CONFIG_SCSI_AHCI_PLAT
Tang Yuantian57894be2015-12-09 15:32:18 +080042
43#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
44#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
45
46#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
47#define CONFIG_SYS_SCSI_MAX_LUN 1
48#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
49 CONFIG_SYS_SCSI_MAX_LUN)
50
York Sun03017032015-03-20 19:28:23 -070051#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
52#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
53#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
54
55#define CONFIG_SYS_NOR0_CSPR \
56 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
57 CSPR_PORT_SIZE_16 | \
58 CSPR_MSEL_NOR | \
59 CSPR_V)
60#define CONFIG_SYS_NOR0_CSPR_EARLY \
61 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
62 CSPR_PORT_SIZE_16 | \
63 CSPR_MSEL_NOR | \
64 CSPR_V)
65#define CONFIG_SYS_NOR1_CSPR \
66 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
67 CSPR_PORT_SIZE_16 | \
68 CSPR_MSEL_NOR | \
69 CSPR_V)
70#define CONFIG_SYS_NOR1_CSPR_EARLY \
71 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
72 CSPR_PORT_SIZE_16 | \
73 CSPR_MSEL_NOR | \
74 CSPR_V)
75#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
76#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
77 FTIM0_NOR_TEADC(0x5) | \
78 FTIM0_NOR_TEAHC(0x5))
79#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
80 FTIM1_NOR_TRAD_NOR(0x1a) |\
81 FTIM1_NOR_TSEQRAD_NOR(0x13))
82#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
83 FTIM2_NOR_TCH(0x4) | \
84 FTIM2_NOR_TWPH(0x0E) | \
85 FTIM2_NOR_TWP(0x1c))
86#define CONFIG_SYS_NOR_FTIM3 0x04000000
87#define CONFIG_SYS_IFC_CCR 0x01000000
88
Masahiro Yamada8cea9b52017-02-11 22:43:54 +090089#ifdef CONFIG_MTD_NOR_FLASH
York Sun03017032015-03-20 19:28:23 -070090#define CONFIG_SYS_FLASH_QUIET_TEST
91#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
92
93#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
94#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
95#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
96#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
97
98#define CONFIG_SYS_FLASH_EMPTY_INFO
99#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
100 CONFIG_SYS_FLASH_BASE + 0x40000000}
101#endif
102
York Sun03017032015-03-20 19:28:23 -0700103#define CONFIG_SYS_NAND_MAX_ECCPOS 256
104#define CONFIG_SYS_NAND_MAX_OOBFREE 2
105
York Sun03017032015-03-20 19:28:23 -0700106#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
107#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
108 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
109 | CSPR_MSEL_NAND /* MSEL = NAND */ \
110 | CSPR_V)
111#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
112
113#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
114 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
115 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
116 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
117 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
118 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
119 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
120
York Sun03017032015-03-20 19:28:23 -0700121/* ONFI NAND Flash mode0 Timing Params */
122#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
123 FTIM0_NAND_TWP(0x18) | \
124 FTIM0_NAND_TWCHT(0x07) | \
125 FTIM0_NAND_TWH(0x0a))
126#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
127 FTIM1_NAND_TWBE(0x39) | \
128 FTIM1_NAND_TRR(0x0e) | \
129 FTIM1_NAND_TRP(0x18))
130#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
131 FTIM2_NAND_TREH(0x0a) | \
132 FTIM2_NAND_TWHRE(0x1e))
133#define CONFIG_SYS_NAND_FTIM3 0x0
134
135#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
136#define CONFIG_SYS_MAX_NAND_DEVICE 1
137#define CONFIG_MTD_NAND_VERIFY_WRITE
York Sun03017032015-03-20 19:28:23 -0700138
York Sun03017032015-03-20 19:28:23 -0700139#define CONFIG_FSL_QIXIS /* use common QIXIS code */
140#define QIXIS_LBMAP_SWITCH 0x06
141#define QIXIS_LBMAP_MASK 0x0f
142#define QIXIS_LBMAP_SHIFT 0
143#define QIXIS_LBMAP_DFLTBANK 0x00
144#define QIXIS_LBMAP_ALTBANK 0x04
Scott Wood8e728cd2015-03-24 13:25:02 -0700145#define QIXIS_LBMAP_NAND 0x09
Santan Kumar1afa9002017-05-05 15:42:29 +0530146#define QIXIS_LBMAP_SD 0x00
Yuan Yao331c87c2016-06-08 18:25:00 +0800147#define QIXIS_LBMAP_QSPI 0x0f
York Sun03017032015-03-20 19:28:23 -0700148#define QIXIS_RST_CTL_RESET 0x31
149#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
150#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
151#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
Scott Wood8e728cd2015-03-24 13:25:02 -0700152#define QIXIS_RCW_SRC_NAND 0x107
Santan Kumar1afa9002017-05-05 15:42:29 +0530153#define QIXIS_RCW_SRC_SD 0x40
Yuan Yao331c87c2016-06-08 18:25:00 +0800154#define QIXIS_RCW_SRC_QSPI 0x62
York Sun03017032015-03-20 19:28:23 -0700155#define QIXIS_RST_FORCE_MEM 0x01
156
157#define CONFIG_SYS_CSPR3_EXT (0x0)
158#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
159 | CSPR_PORT_SIZE_8 \
160 | CSPR_MSEL_GPCM \
161 | CSPR_V)
162#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
163 | CSPR_PORT_SIZE_8 \
164 | CSPR_MSEL_GPCM \
165 | CSPR_V)
166
167#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
168#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
169/* QIXIS Timing parameters for IFC CS3 */
170#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
171 FTIM0_GPCM_TEADC(0x0e) | \
172 FTIM0_GPCM_TEAHC(0x0e))
173#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
174 FTIM1_GPCM_TRAD(0x3f))
175#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
176 FTIM2_GPCM_TCH(0xf) | \
177 FTIM2_GPCM_TWP(0x3E))
178#define CONFIG_SYS_CS3_FTIM3 0x0
179
Santan Kumar99136482017-05-05 15:42:28 +0530180#if defined(CONFIG_SPL)
181#if defined(CONFIG_NAND_BOOT)
Scott Wood8e728cd2015-03-24 13:25:02 -0700182#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
183#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
184#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
185#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
186#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
187#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
188#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
189#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
190#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
191#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
192#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
193#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
194#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
195#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
196#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
197#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
198#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
199#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
200#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
201#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
202#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
203#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
204#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
205#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
206#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
207#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
208#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
209
Scott Wood8e728cd2015-03-24 13:25:02 -0700210#define CONFIG_SPL_PAD_TO 0x20000
Yuan Yao5d555b92016-06-08 18:24:58 +0800211#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
Santan Kumar99136482017-05-05 15:42:28 +0530212#endif
Scott Wood8e728cd2015-03-24 13:25:02 -0700213#else
York Sun03017032015-03-20 19:28:23 -0700214#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
215#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
216#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
217#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
218#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
219#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
220#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
221#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
222#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
223#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
224#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
225#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
226#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
227#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
228#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
229#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
230#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
231#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
232#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
233#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
234#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
235#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
236#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
237#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
238#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
239#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
240#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
Yuan Yao331c87c2016-06-08 18:25:00 +0800241#endif
Scott Wood8e728cd2015-03-24 13:25:02 -0700242
York Sun03017032015-03-20 19:28:23 -0700243/* Debug Server firmware */
244#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
245#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
246
York Sun03017032015-03-20 19:28:23 -0700247#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
248
249/*
250 * I2C
251 */
252#define I2C_MUX_PCA_ADDR 0x77
253#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
254
255/* I2C bus multiplexer */
256#define I2C_MUX_CH_DEFAULT 0x8
257
Haikun Wang9547c5d2015-07-03 16:51:34 +0800258/* SPI */
Yuan Yao6fc42b02016-06-08 18:24:55 +0800259#ifdef CONFIG_FSL_DSPI
260#define CONFIG_SPI_FLASH_STMICRO
261#define CONFIG_SPI_FLASH_SST
262#define CONFIG_SPI_FLASH_EON
263#endif
264
265#ifdef CONFIG_FSL_QSPI
266#define CONFIG_SPI_FLASH_SPANSION
Yuan Yao6fc42b02016-06-08 18:24:55 +0800267#endif
Yuan Yao86f42d72016-06-08 18:24:57 +0800268/*
269 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
270 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
271 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
272 */
273#define FSL_QIXIS_BRDCFG9_QSPI 0x1
Yuan Yao6fc42b02016-06-08 18:24:55 +0800274
York Sun03017032015-03-20 19:28:23 -0700275/*
Yangbo Lud0e295d2015-03-20 19:28:31 -0700276 * MMC
277 */
278#ifdef CONFIG_MMC
279#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
280 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
281#endif
282
283/*
York Sun03017032015-03-20 19:28:23 -0700284 * RTC configuration
285 */
286#define RTC
287#define CONFIG_RTC_DS3231 1
Chuanhua Han1ab68c72019-07-26 19:24:01 +0800288#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
York Sun03017032015-03-20 19:28:23 -0700289#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Chuanhua Han4f97aac2019-07-26 19:24:00 +0800290#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
York Sun03017032015-03-20 19:28:23 -0700291
292/* EEPROM */
York Sun03017032015-03-20 19:28:23 -0700293#define CONFIG_SYS_I2C_EEPROM_NXID
294#define CONFIG_SYS_EEPROM_BUS_NUM 0
York Sun03017032015-03-20 19:28:23 -0700295
York Sun03017032015-03-20 19:28:23 -0700296#define CONFIG_FSL_MEMAC
York Sun03017032015-03-20 19:28:23 -0700297
298#ifdef CONFIG_PCI
York Sun03017032015-03-20 19:28:23 -0700299#define CONFIG_PCI_SCAN_SHOW
York Sun03017032015-03-20 19:28:23 -0700300#endif
301
York Sun03017032015-03-20 19:28:23 -0700302/* Initial environment variables */
303#undef CONFIG_EXTRA_ENV_SETTINGS
Udit Agarwal22ec2382019-11-07 16:11:32 +0000304#ifdef CONFIG_NXP_ESBC
York Sun03017032015-03-20 19:28:23 -0700305#define CONFIG_EXTRA_ENV_SETTINGS \
306 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
307 "loadaddr=0x80100000\0" \
308 "kernel_addr=0x100000\0" \
309 "ramdisk_addr=0x800000\0" \
310 "ramdisk_size=0x2000000\0" \
311 "fdt_high=0xa0000000\0" \
312 "initrd_high=0xffffffffffffffff\0" \
Udit Agarwald11fed72017-05-02 17:43:57 +0530313 "kernel_start=0x581000000\0" \
York Sun03017032015-03-20 19:28:23 -0700314 "kernel_load=0xa0000000\0" \
Prabhakar Kushwahaae193f92016-02-03 17:03:51 +0530315 "kernel_size=0x2800000\0" \
Santan Kumar0a946f42017-02-06 14:18:12 +0530316 "mcmemsize=0x40000000\0" \
Priyanka Singh7cef8b62020-01-22 10:32:38 +0000317 "mcinitcmd=esbc_validate 0x580640000;" \
318 "esbc_validate 0x580680000;" \
Udit Agarwald11fed72017-05-02 17:43:57 +0530319 "fsl_mc start mc 0x580a00000" \
320 " 0x580e00000 \0"
Rajesh Bhagatfb0c2f32018-12-27 04:38:01 +0000321#else
322#ifdef CONFIG_TFABOOT
323#define SD_MC_INIT_CMD \
Priyanka Jainb20a9c72021-07-19 14:54:25 +0530324 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
Wasim Khan2260b3e2019-06-10 10:17:27 +0000325 "mmc read 0x80e00000 0x7000 0x800;" \
326 "fsl_mc start mc 0x80a00000 0x80e00000\0"
Rajesh Bhagatfb0c2f32018-12-27 04:38:01 +0000327#define IFC_MC_INIT_CMD \
328 "fsl_mc start mc 0x580a00000" \
329 " 0x580e00000 \0"
330#define CONFIG_EXTRA_ENV_SETTINGS \
331 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
332 "loadaddr=0x80100000\0" \
333 "loadaddr_sd=0x90100000\0" \
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000334 "kernel_addr=0x581000000\0" \
335 "kernel_addr_sd=0x8000\0" \
Rajesh Bhagatfb0c2f32018-12-27 04:38:01 +0000336 "ramdisk_addr=0x800000\0" \
337 "ramdisk_size=0x2000000\0" \
338 "fdt_high=0xa0000000\0" \
339 "initrd_high=0xffffffffffffffff\0" \
340 "kernel_start=0x581000000\0" \
341 "kernel_start_sd=0x8000\0" \
342 "kernel_load=0xa0000000\0" \
343 "kernel_size=0x2800000\0" \
344 "kernel_size_sd=0x14000\0" \
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000345 "load_addr=0xa0000000\0" \
Priyanka Singh7cef8b62020-01-22 10:32:38 +0000346 "kernelheader_addr=0x580600000\0" \
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000347 "kernelheader_addr_r=0x80200000\0" \
348 "kernelheader_size=0x40000\0" \
349 "BOARD=ls2088aqds\0" \
350 "mcmemsize=0x70000000 \0" \
Biwen Li35c82d62020-03-19 20:01:07 +0800351 "scriptaddr=0x80000000\0" \
352 "scripthdraddr=0x80080000\0" \
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000353 IFC_MC_INIT_CMD \
Biwen Li35c82d62020-03-19 20:01:07 +0800354 BOOTENV \
355 "boot_scripts=ls2088aqds_boot.scr\0" \
356 "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \
357 "scan_dev_for_boot_part=" \
358 "part list ${devtype} ${devnum} devplist; " \
359 "env exists devplist || setenv devplist 1; " \
360 "for distro_bootpart in ${devplist}; do " \
361 "if fstype ${devtype} " \
362 "${devnum}:${distro_bootpart} " \
363 "bootfstype; then " \
364 "run scan_dev_for_boot; " \
365 "fi; " \
366 "done\0" \
367 "boot_a_script=" \
368 "load ${devtype} ${devnum}:${distro_bootpart} " \
369 "${scriptaddr} ${prefix}${script}; " \
370 "env exists secureboot && load ${devtype} " \
371 "${devnum}:${distro_bootpart} " \
372 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
373 "&& esbc_validate ${scripthdraddr};" \
374 "source ${scriptaddr}\0" \
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000375 "nor_bootcmd=echo Trying load from nor..;" \
376 "cp.b $kernel_addr $load_addr " \
377 "$kernel_size ; env exists secureboot && " \
378 "cp.b $kernelheader_addr $kernelheader_addr_r " \
379 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
380 "bootm $load_addr#$BOARD\0" \
381 "sd_bootcmd=echo Trying load from SD ..;" \
382 "mmcinfo; mmc read $load_addr " \
383 "$kernel_addr_sd $kernel_size_sd && " \
384 "bootm $load_addr#$BOARD\0"
Santan Kumar1afa9002017-05-05 15:42:29 +0530385#elif defined(CONFIG_SD_BOOT)
386#define CONFIG_EXTRA_ENV_SETTINGS \
387 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
388 "loadaddr=0x90100000\0" \
389 "kernel_addr=0x800\0" \
390 "ramdisk_addr=0x800000\0" \
391 "ramdisk_size=0x2000000\0" \
392 "fdt_high=0xa0000000\0" \
393 "initrd_high=0xffffffffffffffff\0" \
394 "kernel_start=0x8000\0" \
395 "kernel_load=0xa0000000\0" \
396 "kernel_size=0x14000\0" \
Priyanka Jainb20a9c72021-07-19 14:54:25 +0530397 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
398 "mmc read 0x80e00000 0x7000 0x800;" \
399 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
Santan Kumar1afa9002017-05-05 15:42:29 +0530400 "mcmemsize=0x70000000 \0"
Udit Agarwal18583432017-01-06 15:58:57 +0530401#else
402#define CONFIG_EXTRA_ENV_SETTINGS \
403 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
404 "loadaddr=0x80100000\0" \
405 "kernel_addr=0x100000\0" \
406 "ramdisk_addr=0x800000\0" \
407 "ramdisk_size=0x2000000\0" \
408 "fdt_high=0xa0000000\0" \
409 "initrd_high=0xffffffffffffffff\0" \
Santan Kumar0f0173d2017-04-28 12:47:24 +0530410 "kernel_start=0x581000000\0" \
Udit Agarwal18583432017-01-06 15:58:57 +0530411 "kernel_load=0xa0000000\0" \
412 "kernel_size=0x2800000\0" \
Santan Kumar0a946f42017-02-06 14:18:12 +0530413 "mcmemsize=0x40000000\0" \
Santan Kumar0f0173d2017-04-28 12:47:24 +0530414 "mcinitcmd=fsl_mc start mc 0x580a00000" \
415 " 0x580e00000 \0"
Rajesh Bhagatfb0c2f32018-12-27 04:38:01 +0000416#endif /* CONFIG_TFABOOT */
Udit Agarwal22ec2382019-11-07 16:11:32 +0000417#endif /* CONFIG_NXP_ESBC */
Udit Agarwal18583432017-01-06 15:58:57 +0530418
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000419#ifdef CONFIG_TFABOOT
Biwen Li35c82d62020-03-19 20:01:07 +0800420#define BOOT_TARGET_DEVICES(func) \
421 func(USB, usb, 0) \
422 func(MMC, mmc, 0) \
423 func(SCSI, scsi, 0) \
424 func(DHCP, dhcp, na)
425#include <config_distro_bootcmd.h>
426
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000427#define SD_BOOTCOMMAND \
428 "env exists mcinitcmd && env exists secureboot "\
Priyanka Singh7cef8b62020-01-22 10:32:38 +0000429 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000430 "&& esbc_validate $load_addr; " \
431 "env exists mcinitcmd && run mcinitcmd " \
Wasim Khan2260b3e2019-06-10 10:17:27 +0000432 "&& mmc read 0x80d00000 0x6800 0x800 " \
433 "&& fsl_mc lazyapply dpl 0x80d00000; " \
Biwen Li35c82d62020-03-19 20:01:07 +0800434 "run distro_bootcmd;run sd_bootcmd; " \
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000435 "env exists secureboot && esbc_halt;"
436
437#define IFC_NOR_BOOTCOMMAND \
438 "env exists mcinitcmd && env exists secureboot "\
Priyanka Singh7cef8b62020-01-22 10:32:38 +0000439 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000440 "&& fsl_mc lazyapply dpl 0x580d00000;" \
Biwen Li35c82d62020-03-19 20:01:07 +0800441 "run distro_bootcmd;run nor_bootcmd; " \
Wasim Khanfcfe0af2019-06-10 10:17:25 +0000442 "env exists secureboot && esbc_halt;"
443#endif
444
Santan Kumar1afa9002017-05-05 15:42:29 +0530445#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
Prabhakar Kushwahac158fad2015-03-20 19:28:26 -0700446#define CONFIG_FSL_MEMAC
Prabhakar Kushwahac158fad2015-03-20 19:28:26 -0700447#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
448#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
449#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
450#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
451
Prabhakar Kushwaha35f93f62015-08-07 18:01:51 +0530452#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
453#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
454#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
455#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
456#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
457#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
458#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
459#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
460#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
461#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
462#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
463#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
464#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
465#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
466#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
467#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
468
Prabhakar Kushwaha0a95f8f2016-04-19 08:53:42 +0530469#define CONFIG_ETHPRIME "DPMAC1@xgmii"
Prabhakar Kushwahac158fad2015-03-20 19:28:26 -0700470
471#endif
472
Saksham Jainc0c38d22016-03-23 16:24:35 +0530473#include <asm/fsl_secure_boot.h>
474
York Sun03017032015-03-20 19:28:23 -0700475#endif /* __LS2_QDS_H */