Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the Freescale MCF5208EVBe. |
| 4 | * |
| 5 | * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
| 6 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef _M5208EVBE_H |
| 10 | #define _M5208EVBE_H |
| 11 | |
| 12 | /* |
| 13 | * High Level Configuration Options |
| 14 | * (easy to change) |
| 15 | */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 16 | #define CONFIG_MCFUART |
| 17 | #define CONFIG_SYS_UART_PORT (0) |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 18 | |
| 19 | #undef CONFIG_WATCHDOG |
| 20 | #define CONFIG_WATCHDOG_TIMEOUT 5000 |
| 21 | |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 22 | #ifdef CONFIG_MCFFEC |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 23 | # define CONFIG_MII_INIT 1 |
| 24 | # define CONFIG_SYS_DISCOVER_PHY |
| 25 | # define CONFIG_SYS_RX_ETH_BUFFER 8 |
| 26 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
| 27 | # define CONFIG_HAS_ETH1 |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 28 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
| 29 | # ifndef CONFIG_SYS_DISCOVER_PHY |
| 30 | # define FECDUPLEX FULL |
| 31 | # define FECSPEED _100BASET |
| 32 | # else |
| 33 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
| 34 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
| 35 | # endif |
| 36 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
| 37 | #endif |
| 38 | |
| 39 | /* Timer */ |
| 40 | #define CONFIG_MCFTMR |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 41 | |
| 42 | /* I2C */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 43 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
| 44 | |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 45 | #define CONFIG_UDP_CHECKSUM |
| 46 | |
| 47 | #ifdef CONFIG_MCFFEC |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 48 | # define CONFIG_IPADDR 192.162.1.2 |
| 49 | # define CONFIG_NETMASK 255.255.255.0 |
| 50 | # define CONFIG_SERVERIP 192.162.1.1 |
| 51 | # define CONFIG_GATEWAYIP 192.162.1.1 |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 52 | #endif /* CONFIG_MCFFEC */ |
| 53 | |
Mario Six | 790d844 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 54 | #define CONFIG_HOSTNAME "M5208EVBe" |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 55 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 56 | "netdev=eth0\0" \ |
| 57 | "loadaddr=40010000\0" \ |
| 58 | "u-boot=u-boot.bin\0" \ |
| 59 | "load=tftp ${loadaddr) ${u-boot}\0" \ |
| 60 | "upd=run load; run prog\0" \ |
| 61 | "prog=prot off 0 3ffff;" \ |
| 62 | "era 0 3ffff;" \ |
| 63 | "cp.b ${loadaddr} 0 ${filesize};" \ |
| 64 | "save\0" \ |
| 65 | "" |
| 66 | |
| 67 | #define CONFIG_PRAM 512 /* 512 KB */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 68 | |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 69 | #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ |
| 70 | #define CONFIG_SYS_PLL_ODR 0x36 |
| 71 | #define CONFIG_SYS_PLL_FDR 0x7D |
| 72 | |
| 73 | #define CONFIG_SYS_MBAR 0xFC000000 |
| 74 | |
| 75 | /* |
| 76 | * Low Level Configuration Settings |
| 77 | * (address mappings, register initial values, etc.) |
| 78 | * You should know what you are doing if you make changes here. |
| 79 | */ |
| 80 | /* Definitions for initial stack pointer and data area (in DPRAM) */ |
| 81 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 82 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 83 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 84 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 85 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 86 | |
| 87 | /* |
| 88 | * Start addresses for the final memory configuration |
| 89 | * (Set up by the startup code) |
| 90 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| 91 | */ |
| 92 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
TsiChung Liew | f6f4ec9 | 2010-03-10 18:50:22 -0600 | [diff] [blame] | 93 | #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 94 | #define CONFIG_SYS_SDRAM_CFG1 0x43711630 |
| 95 | #define CONFIG_SYS_SDRAM_CFG2 0x56670000 |
| 96 | #define CONFIG_SYS_SDRAM_CTRL 0xE1002000 |
| 97 | #define CONFIG_SYS_SDRAM_EMOD 0x80010000 |
| 98 | #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 |
| 99 | |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 100 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
| 101 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
| 102 | |
| 103 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 104 | |
| 105 | /* |
| 106 | * For booting Linux, the board info and command line data |
| 107 | * have to be in the first 8 MB of memory, since this is |
| 108 | * the maximum mapped by the Linux kernel during initialization ?? |
| 109 | */ |
| 110 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
| 111 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
| 112 | |
| 113 | /* FLASH organization */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 114 | #ifdef CONFIG_SYS_FLASH_CFI |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 115 | # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ |
| 116 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
| 117 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 118 | # define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 119 | #endif |
| 120 | |
| 121 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
| 122 | |
| 123 | /* |
| 124 | * Configuration for environment |
| 125 | * Environment is embedded in u-boot in the second sector of the flash |
| 126 | */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 127 | |
angelo@sysam.it | 6312a95 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 128 | #define LDS_BOARD_TEXT \ |
Simon Glass | 547cb40 | 2017-08-03 12:21:49 -0600 | [diff] [blame] | 129 | . = DEFINED(env_offset) ? env_offset : .; \ |
| 130 | env/embedded.o(.text*); |
angelo@sysam.it | 6312a95 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 131 | |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 132 | /* Cache Configuration */ |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 133 | |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 134 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 135 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 136 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 137 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 138 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) |
| 139 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ |
| 140 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ |
| 141 | CF_ACR_EN | CF_ACR_SM_ALL) |
| 142 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ |
| 143 | CF_CACR_DISD | CF_CACR_INVI | \ |
| 144 | CF_CACR_CEIB | CF_CACR_DCM | \ |
| 145 | CF_CACR_EUSP) |
| 146 | |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 147 | /* Chipselect bank definitions */ |
| 148 | /* |
| 149 | * CS0 - NOR Flash |
| 150 | * CS1 - Available |
| 151 | * CS2 - Available |
| 152 | * CS3 - Available |
| 153 | * CS4 - Available |
| 154 | * CS5 - Available |
| 155 | */ |
| 156 | #define CONFIG_SYS_CS0_BASE 0 |
| 157 | #define CONFIG_SYS_CS0_MASK 0x007F0001 |
| 158 | #define CONFIG_SYS_CS0_CTRL 0x00001FA0 |
| 159 | |
| 160 | #endif /* _M5208EVBE_H */ |