Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / e86e9e2ff7e89f6d377157e758c8edbc57d4d161 / . / drivers / clk / sunxi / clk_h616.c
blob: 553d7c6e550a07cb307f441677fab134cb4b3639 [file] [log] [blame]
Jernej Skrabece52dc3e2021-01-11 21:11:52 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2021 Jernej Skrabec <jernej.skrabec@siol.net>
4 */
5
6#include <common.h>
7#include <clk-uclass.h>
8#include <dm.h>
9#include <errno.h>
10#include <asm/arch/ccu.h>
11#include <dt-bindings/clock/sun50i-h616-ccu.h>
12#include <dt-bindings/reset/sun50i-h616-ccu.h>
13#include <linux/bitops.h>
14
15static struct ccu_clk_gate h616_gates[] = {
16 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
17 [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
18 [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
19
20 [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
21 [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
22 [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
23 [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
24 [CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
25 [CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
26
27 [CLK_SPI0] = GATE(0x940, BIT(31)),
28 [CLK_SPI1] = GATE(0x944, BIT(31)),
29
30 [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
31 [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
32
33 [CLK_BUS_EMAC0] = GATE(0x97c, BIT(0)),
34 [CLK_BUS_EMAC1] = GATE(0x97c, BIT(1)),
35
36 [CLK_USB_PHY0] = GATE(0xa70, BIT(29)),
37 [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
38
39 [CLK_USB_PHY1] = GATE(0xa74, BIT(29)),
40 [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
41
42 [CLK_USB_PHY2] = GATE(0xa78, BIT(29)),
43 [CLK_USB_OHCI2] = GATE(0xa78, BIT(31)),
44
45 [CLK_USB_PHY3] = GATE(0xa7c, BIT(29)),
46 [CLK_USB_OHCI3] = GATE(0xa7c, BIT(31)),
47
48 [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
49 [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
50 [CLK_BUS_OHCI2] = GATE(0xa8c, BIT(2)),
51 [CLK_BUS_OHCI3] = GATE(0xa8c, BIT(3)),
52 [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
53 [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)),
54 [CLK_BUS_EHCI2] = GATE(0xa8c, BIT(6)),
55 [CLK_BUS_EHCI3] = GATE(0xa8c, BIT(7)),
56 [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
57};
58
59static struct ccu_reset h616_resets[] = {
60 [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
61 [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
62 [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
63
64 [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
65 [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
66 [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
67 [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
68 [RST_BUS_UART4] = RESET(0x90c, BIT(20)),
69 [RST_BUS_UART5] = RESET(0x90c, BIT(21)),
70
71 [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
72 [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
73
74 [RST_BUS_EMAC0] = RESET(0x97c, BIT(16)),
75 [RST_BUS_EMAC1] = RESET(0x97c, BIT(17)),
76
77 [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
78
79 [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
80
81 [RST_USB_PHY2] = RESET(0xa78, BIT(30)),
82
83 [RST_USB_PHY3] = RESET(0xa7c, BIT(30)),
84
85 [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
86 [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)),
87 [RST_BUS_OHCI2] = RESET(0xa8c, BIT(18)),
88 [RST_BUS_OHCI3] = RESET(0xa8c, BIT(19)),
89 [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
90 [RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)),
91 [RST_BUS_EHCI2] = RESET(0xa8c, BIT(22)),
92 [RST_BUS_EHCI3] = RESET(0xa8c, BIT(23)),
93 [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
94};
95
96static const struct ccu_desc h616_ccu_desc = {
97 .gates = h616_gates,
98 .resets = h616_resets,
99};
100
101static int h616_clk_bind(struct udevice *dev)
102{
103 return sunxi_reset_bind(dev, ARRAY_SIZE(h616_resets));
104}
105
106static const struct udevice_id h616_ccu_ids[] = {
107 { .compatible = "allwinner,sun50i-h616-ccu",
108 .data = (ulong)&h616_ccu_desc },
109 { }
110};
111
112U_BOOT_DRIVER(clk_sun50i_h616) = {
113 .name = "sun50i_h616_ccu",
114 .id = UCLASS_CLK,
115 .of_match = h616_ccu_ids,
116 .priv_auto = sizeof(struct ccu_priv),
117 .ops = &sunxi_clk_ops,
118 .probe = sunxi_clk_probe,
119 .bind = h616_clk_bind,
120};