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git01.mediatek.com / filogic / uboot / e86e9e2ff7e89f6d377157e758c8edbc57d4d161 / . / board / Synology / ds109 / ds109.c
blob: 3914faaf37bb48e79cce8911cea85354e5d2e73b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Walter Schweizerd2ac3262016-10-06 23:29:56 +0200[diff] [blame]2/*
3 * Copyright (C) 2009-2012
4 * Wojciech Dubowik <wojciech.dubowik@neratec.com>
5 * Luka Perkov <luka@openwrt.org>
Walter Schweizerd2ac3262016-10-06 23:29:56 +0200[diff] [blame]6 */
7
8#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -0600[diff] [blame]9#include <init.h>
Walter Schweizerd2ac3262016-10-06 23:29:56 +0200[diff] [blame]10#include <miiphy.h>
Simon Glass0c364412019-12-28 10:44:48 -0700[diff] [blame]11#include <net.h>
Simon Glass3ba929a2020-10-30 21:38:53 -0600[diff] [blame]12#include <asm/global_data.h>
Simon Glassd9a766f2017-05-17 08:23:00 -0600[diff] [blame]13#include <asm/setup.h>
Walter Schweizerd2ac3262016-10-06 23:29:56 +0200[diff] [blame]14#include <asm/arch/cpu.h>
15#include <asm/arch/soc.h>
16#include <asm/arch/mpp.h>
Simon Glassdbd79542020-05-10 11:40:11 -0600[diff] [blame]17#include <linux/delay.h>
Walter Schweizerd2ac3262016-10-06 23:29:56 +0200[diff] [blame]18#include "ds109.h"
19
20DECLARE_GLOBAL_DATA_PTR;
21
22int board_early_init_f(void)
23{
24 /*
25 * default gpio configuration
26 * There are maximum 64 gpios controlled through 2 sets of registers
27 * the below configuration configures mainly initial LED status
28 */
29 mvebu_config_gpio(DS109_OE_VAL_LOW,
30 DS109_OE_VAL_HIGH,
31 DS109_OE_LOW, DS109_OE_HIGH);
32
33 /* Multi-Purpose Pins Functionality configuration */
34 static const u32 kwmpp_config[] = {
35 MPP0_SPI_SCn, /* SPI Flash */
36 MPP1_SPI_MOSI,
37 MPP2_SPI_SCK,
38 MPP3_SPI_MISO,
39 MPP4_GPIO,
40 MPP5_GPO,
41 MPP6_SYSRST_OUTn, /* Reset signal */
42 MPP7_GPO,
43 MPP8_TW_SDA, /* I2C */
44 MPP9_TW_SCK, /* I2C */
45 MPP10_UART0_TXD,
46 MPP11_UART0_RXD,
47 MPP12_GPO,
48 MPP13_UART1_TXD,
49 MPP14_UART1_RXD,
50 MPP15_GPIO,
51 MPP16_GPIO,
52 MPP17_GPIO,
53 MPP18_GPO,
54 MPP19_GPO,
55 MPP20_SATA1_ACTn,
56 MPP21_SATA0_ACTn,
57 MPP22_GPIO, /* HDD2 FAIL LED */
58 MPP23_GPIO, /* HDD1 FAIL LED */
59 MPP24_GPIO,
60 MPP25_GPIO,
61 MPP26_GPIO,
62 MPP27_GPIO,
63 MPP28_GPIO,
64 MPP29_GPIO,
65 MPP30_GPIO,
66 MPP31_GPIO, /* HDD2 */
67 MPP32_GPIO, /* FAN A */
68 MPP33_GPIO, /* FAN B */
69 MPP34_GPIO, /* FAN C */
70 MPP35_GPIO, /* FAN SENSE */
71 MPP36_GPIO,
72 MPP37_GPIO,
73 MPP38_GPIO,
74 MPP39_GPIO,
75 MPP40_GPIO,
76 MPP41_GPIO,
77 MPP42_GPIO,
78 MPP43_GPIO,
79 MPP44_GPIO,
80 MPP45_GPIO,
81 MPP46_GPIO,
82 MPP47_GPIO,
83 MPP48_GPIO,
84 MPP49_GPIO,
85 0
86 };
87 kirkwood_mpp_conf(kwmpp_config, NULL);
88 return 0;
89}
90
91int board_init(void)
92{
93 /* address of boot parameters */
94 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
95
96 return 0;
97}
98
99/* Synology reset uses UART */
100#include <ns16550.h>
101#define SOFTWARE_SHUTDOWN 0x31
102#define SOFTWARE_REBOOT 0x43
103#define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE
104void reset_misc(void)
105{
106 int b_d;
107 printf("Synology reset...");
108 udelay(50000);
109
Simon Glass119e7ef2020-12-22 19:30:18 -0700[diff] [blame]110 b_d = ns16550_calc_divisor((struct ns16550 *)CONFIG_SYS_NS16550_COM2,
111 CONFIG_SYS_NS16550_CLK, 9600);
Simon Glass2b923982020-12-22 19:30:19 -0700[diff] [blame]112 ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM2, b_d);
113 ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM2,
114 SOFTWARE_REBOOT);
Walter Schweizerd2ac3262016-10-06 23:29:56 +0200[diff] [blame]115}
116
Walter Schweizerd2ac3262016-10-06 23:29:56 +0200[diff] [blame]117#ifdef CONFIG_RESET_PHY_R
118/* Configure and enable MV88E1116 PHY */
119void reset_phy(void)
120{
121 u16 reg;
122 u16 devadr;
123 char *name = "egiga0";
124
125 if (miiphy_set_current_dev(name))
126 return;
127
128 /* command to read PHY dev address */
129 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
130 printf("Error: 88E1116 could not read PHY dev address\n");
131 return;
132 }
133
134 /*
135 * Enable RGMII delay on Tx and Rx for CPU port
136 * Ref: sec 4.7.2 of chip datasheet
137 */
138 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
139 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
140 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
141 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
142 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
143
144 /* reset the phy */
145 miiphy_reset(name, devadr);
146
147 printf("88E1116 Initialized on %s\n", name);
148}
149#endif /* CONFIG_RESET_PHY_R */