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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andy Shevchenkod31315d2017-07-06 14:41:53 +03002/*
3 * Copyright (c) 2017 Intel Corporation
Andy Shevchenkod31315d2017-07-06 14:41:53 +03004 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/x86-gpio.h>
9#include <dt-bindings/interrupt-router/intel-irq.h>
10
11/include/ "skeleton.dtsi"
12/include/ "rtc.dtsi"
Andy Shevchenkod31315d2017-07-06 14:41:53 +030013
Bin Meng8967f632021-07-28 12:00:23 +080014#include "tsc_timer.dtsi"
Simon Glassbee77f62020-11-05 06:32:17 -070015#include "smbios.dtsi"
16
Andy Shevchenkod31315d2017-07-06 14:41:53 +030017/ {
18 model = "Intel Edison";
Andy Shevchenkoae3c6252020-12-02 12:35:32 +020019 compatible = "intel,edison", "intel,tangier";
Andy Shevchenkod31315d2017-07-06 14:41:53 +030020
21 aliases {
Andy Shevchenko9b9ca5b2019-02-28 10:10:07 +020022 serial0 = &serial0;
23 serial1 = &serial1;
Andy Shevchenko8e9ce292019-02-28 10:10:06 +020024 serial2 = &serial2;
Andy Shevchenkod31315d2017-07-06 14:41:53 +030025 };
26
Simon Glassb6764922020-09-06 10:35:34 -060027 binman: binman {
28 multiple-images;
29 };
30
Andy Shevchenkod31315d2017-07-06 14:41:53 +030031 chosen {
Andy Shevchenko8e9ce292019-02-28 10:10:06 +020032 stdout-path = &serial2;
Andy Shevchenkod31315d2017-07-06 14:41:53 +030033 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 cpu@0 {
40 device_type = "cpu";
41 compatible = "cpu-x86";
42 reg = <0>;
43 intel,apic-id = <0>;
44 };
45
46 cpu@1 {
47 device_type = "cpu";
48 compatible = "cpu-x86";
49 reg = <1>;
50 intel,apic-id = <2>;
51 };
52 };
53
54 pci {
55 compatible = "pci-x86";
56 #address-cells = <3>;
57 #size-cells = <2>;
58 u-boot,dm-pre-reloc;
59 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
60 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
61 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
62 };
63
Andy Shevchenko9b9ca5b2019-02-28 10:10:07 +020064 serial0: serial@ff010080 {
65 compatible = "intel,mid-uart";
66 reg = <0xff010080 0x100>;
67 reg-shift = <0>;
68 clock-frequency = <29491200>;
69 current-speed = <115200>;
70 };
71
72 serial1: serial@ff010100 {
73 compatible = "intel,mid-uart";
74 reg = <0xff010100 0x100>;
75 reg-shift = <0>;
76 clock-frequency = <29491200>;
77 current-speed = <115200>;
78 };
79
Andy Shevchenko8e9ce292019-02-28 10:10:06 +020080 serial2: serial@ff010180 {
Andy Shevchenkod31315d2017-07-06 14:41:53 +030081 compatible = "intel,mid-uart";
82 reg = <0xff010180 0x100>;
83 reg-shift = <0>;
84 clock-frequency = <29491200>;
85 current-speed = <115200>;
86 };
87
88 emmc: mmc@ff3fc000 {
89 compatible = "intel,sdhci-tangier";
90 reg = <0xff3fc000 0x1000>;
Andy Shevchenkod64c09f2021-09-10 10:59:27 +030091 non-removable;
Andy Shevchenkod31315d2017-07-06 14:41:53 +030092 };
93
Andy Shevchenkod31315d2017-07-06 14:41:53 +030094 sdcard: mmc@ff3fa000 {
95 compatible = "intel,sdhci-tangier";
96 reg = <0xff3fa000 0x1000>;
97 };
Andy Shevchenkod31315d2017-07-06 14:41:53 +030098
99 pmu: power@ff00b000 {
100 compatible = "intel,pmu-mid";
101 reg = <0xff00b000 0x1000>;
102 };
103
104 scu: ipc@ff009000 {
105 compatible = "intel,scu-ipc";
106 reg = <0xff009000 0x1000>;
107 };
Bin Mengaf5b8d22018-07-19 03:07:33 -0700108
Andy Shevchenko221d7fa2020-12-03 19:45:01 +0200109 usb: usb@f9100000 {
110 compatible = "intel,tangier-dwc3";
Andy Shevchenko51b2f302020-12-03 19:45:02 +0200111 #address-cells = <1>;
112 #size-cells = <1>;
113
114 dwc3: dwc3 {
115 reg = <0xf9100000 0x100000>;
116 maximum-speed = "high-speed";
117 dr_mode = "peripheral";
118 };
Andy Shevchenko221d7fa2020-12-03 19:45:01 +0200119 };
120
Andy Shevchenkod13a8a32019-06-21 13:28:08 +0300121 watchdog: wdt@0 {
122 compatible = "intel,tangier-wdt";
123 };
124
Bin Mengaf5b8d22018-07-19 03:07:33 -0700125 reset {
126 compatible = "intel,reset-tangier";
127 u-boot,dm-pre-reloc;
128 };
Georgii Staroselskiid9c72772018-09-11 13:31:08 +0300129
130 pinctrl {
131 compatible = "intel,pinctrl-tangier";
132 reg = <0xff0c0000 0x8000>;
133
134 /*
135 * Initial configuration came from the firmware.
136 * Which quite likely has been used in the phones, where I2C #8,
137 * that is not part of Atom peripheral, is in use.
138 * Thus we need to override the leftover.
139 */
140 i2c6_scl@0 {
141 pad-offset = <111>;
142 mode-func = <1>;
143 protected;
144 };
145 i2c6_sda@0 {
146 pad-offset = <112>;
147 mode-func = <1>;
148 protected;
149 };
150 };
Andy Shevchenkod31315d2017-07-06 14:41:53 +0300151};
Simon Glassb6764922020-09-06 10:35:34 -0600152
153&binman {
154 u-boot-edison {
155 filename = "u-boot-edison.img";
156
157 /* This is the OSIP */
158 blob {
159 filename = "edison-osip.dat";
160 };
161
162 u-boot {
163 offset = <0x200>;
164 };
165
166 u-boot-env {
167 offset = <0x200200>;
168 filename = "edison-environment.txt";
169 size = <0x10000>;
170 fill-byte = [ff];
171 };
172
173 u-boot-env2 {
174 type = "u-boot-env";
175 offset = <0x500200>;
176 filename = "edison-environment.txt";
177 size = <0x10000>;
178 fill-byte = [ff];
179 };
180 };
181};