blob: ff861d10bb42730d96968e172368aef474ca4e77 [file] [log] [blame]
wdenk12490652004-04-18 21:13:41 +00001/*
2 * include/asm-microblaze/ptrace.h -- Access to CPU registers
3 *
4 * Copyright (C) 2003 John Williams <jwilliams@itee.uq.edu.au>
5 * Copyright (C) 2001,2002 NEC Corporation
6 * Copyright (C) 2001,2002 Miles Bader <miles@gnu.org>
7 *
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file COPYING in the main directory of this
10 * archive for more details.
11 *
12 * Written by Miles Bader <miles@gnu.org>
13 * Microblaze port by John Williams
14 */
15
16#ifndef __MICROBLAZE_PTRACE_H__
17#define __MICROBLAZE_PTRACE_H__
18
wdenk12490652004-04-18 21:13:41 +000019/* Microblaze general purpose registers with special meanings. */
20#define GPR_ZERO 0 /* constant zero */
21#define GPR_ASM 18 /* reserved for assembler */
22#define GPR_SP 1 /* stack pointer */
23#define GPR_GP 2 /* global data pointer */
24#define GPR_EP 30 /* `element pointer' */
25#define GPR_LP 15 /* link pointer (current return address) */
26
27/* These aren't official names, but they make some code more descriptive. */
28#define GPR_ARG0 5
29#define GPR_ARG1 6
30#define GPR_ARG2 7
31#define GPR_ARG3 8
32#define GPR_ARG4 9
33#define GPR_ARG5 10
34#define GPR_RVAL0 3
35#define GPR_RVAL1 4
36#define GPR_RVAL GPR_RVAL0
37
38#define NUM_GPRS 32
39
40/* `system' registers. */
41/* Note these are old v850 values, microblaze has many fewer */
42#define SR_EIPC 0
43#define SR_EIPSW 1
44#define SR_FEPC 2
45#define SR_FEPSW 3
46#define SR_ECR 4
47#define SR_PSW 5
48#define SR_CTPC 16
49#define SR_CTPSW 17
50#define SR_DBPC 18
51#define SR_DBPSW 19
52#define SR_CTBP 20
53#define SR_DIR 21
54#define SR_ASID 23
55
wdenk12490652004-04-18 21:13:41 +000056#ifndef __ASSEMBLY__
57
58typedef unsigned long microblaze_reg_t;
59
60/* How processor state is stored on the stack during a syscall/signal.
61 If you change this structure, change the associated assembly-language
62 macros below too (PT_*)! */
63struct pt_regs
64{
65 /* General purpose registers. */
66 microblaze_reg_t gpr[NUM_GPRS];
67
68 microblaze_reg_t pc; /* program counter */
69 microblaze_reg_t psw; /* program status word */
70
71 microblaze_reg_t kernel_mode; /* 1 if in `kernel mode', 0 if user mode */
72 microblaze_reg_t single_step; /* 1 if in single step mode */
73};
74
wdenk12490652004-04-18 21:13:41 +000075#define instruction_pointer(regs) ((regs)->pc)
76#define user_mode(regs) (!(regs)->kernel_mode)
77
78/* When a struct pt_regs is used to save user state for a system call in
79 the kernel, the system call is stored in the space for R0 (since it's
80 never used otherwise, R0 being a constant 0). Non-system-calls
81 simply store 0 there. */
82#define PT_REGS_SYSCALL(regs) (regs)->gpr[0]
83#define PT_REGS_SET_SYSCALL(regs, val) ((regs)->gpr[0] = (val))
84
85#endif /* !__ASSEMBLY__ */
86
wdenk12490652004-04-18 21:13:41 +000087/* The number of bytes used to store each register. */
88#define _PT_REG_SIZE 4
89
90/* Offset of a general purpose register in a stuct pt_regs. */
91#define PT_GPR(num) ((num) * _PT_REG_SIZE)
92
93/* Offsets of various special registers & fields in a struct pt_regs. */
94#define NUM_SPECIAL 4
95#define PT_PC ((NUM_GPRS + 0) * _PT_REG_SIZE)
96#define PT_PSW ((NUM_GPRS + 1) * _PT_REG_SIZE)
97#define PT_KERNEL_MODE ((NUM_GPRS + 2) * _PT_REG_SIZE)
98#define PT_SINGLESTEP ((NUM_GPRS + 3) * _PT_REG_SIZE)
99
100#define PT_SYSCALL PT_GPR(0)
101
102/* Size of struct pt_regs, including alignment. */
103#define PT_SIZE ((NUM_GPRS + NUM_SPECIAL) * _PT_REG_SIZE)
104
105/* These are `magic' values for PTRACE_PEEKUSR that return info about where
106 a process is located in memory. */
107#define PT_TEXT_ADDR (PT_SIZE + 1)
108#define PT_TEXT_LEN (PT_SIZE + 2)
109#define PT_DATA_ADDR (PT_SIZE + 3)
110#define PT_DATA_LEN (PT_SIZE + 4)
111
112#endif /* __MICROBLAZE_PTRACE_H__ */