wdenk | e85390d | 2002-04-01 14:29:03 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #ifndef _CPC710_PCI_H_ |
| 25 | #define _CPC710_PCI_H_ |
| 26 | |
| 27 | #define PCI_MEMORY_PHYS 0x00000000 |
| 28 | #define PCI_MEMORY_BUS 0x80000000 |
| 29 | #define PCI_MEMORY_MAXSIZE 0x20000000 |
| 30 | |
| 31 | #define BRIDGE_CPCI_PHYS 0xff500000 |
| 32 | #define BRIDGE_CPCI_MEM_SIZE 0x08000000 |
| 33 | #define BRIDGE_CPCI_MEM_PHYS 0xf0000000 |
| 34 | #define BRIDGE_CPCI_MEM_BUS 0x00000000 |
| 35 | #define BRIDGE_CPCI_IO_SIZE 0x02000000 |
| 36 | #define BRIDGE_CPCI_IO_PHYS 0xfc000000 |
| 37 | #define BRIDGE_CPCI_IO_BUS 0x00000000 |
| 38 | |
| 39 | #define BRIDGE_LOCAL_PHYS 0xff400000 |
| 40 | #define BRIDGE_LOCAL_MEM_SIZE 0x04000000 |
| 41 | #define BRIDGE_LOCAL_MEM_PHYS 0xf8000000 |
| 42 | #define BRIDGE_LOCAL_MEM_BUS 0x40000000 |
| 43 | #define BRIDGE_LOCAL_IO_SIZE 0x01000000 |
| 44 | #define BRIDGE_LOCAL_IO_PHYS 0xfe000000 |
| 45 | #define BRIDGE_LOCAL_IO_BUS 0x04000000 |
| 46 | |
| 47 | #define BRIDGE(r, x) (BRIDGE_##r##_PHYS + HW_BRIDGE_##x) |
| 48 | |
| 49 | #define PCI_LATENCY_TIMER_VAL 0xff |
| 50 | |
| 51 | #endif |