| Jagannadha Sutradharudu Teki | e84b4f6 | 2014-01-12 21:40:11 +0530 | [diff] [blame^] | 1 | SPI/QSPI Dual flash connection modes: |
| 2 | ===================================== |
| 3 | |
| 4 | This describes how SPI/QSPI flash memories are connected to a given |
| 5 | controller in a single chip select line. |
| 6 | |
| 7 | Current spi_flash framework supports, single flash memory connected |
| 8 | to a given controller with single chip select line, but there are some |
| 9 | hw logics(ex: xilinx zynq qspi) that describes two/dual memories are |
| 10 | connected with a single chip select line from a controller. |
| 11 | |
| 12 | "dual_flash" from include/spi.h describes these types of connection mode |
| 13 | |
| 14 | Possible connections: |
| 15 | -------------------- |
| 16 | SF_SINGLE_FLASH: |
| 17 | - single spi flash memory connected with single chip select line. |
| 18 | |
| 19 | +------------+ CS +---------------+ |
| 20 | | |----------------------->| | |
| 21 | | Controller | I0[3:0] | Flash memory | |
| 22 | | SPI/QSPI |<======================>| (SPI/QSPI) | |
| 23 | | | CLK | | |
| 24 | | |----------------------->| | |
| 25 | +------------+ +---------------+ |
| 26 | |
| 27 | SF_DUAL_STACKED_FLASH: |
| 28 | - dual spi/qspi flash memories are connected with a single chipselect |
| 29 | line and these two memories are operating stacked fasion with shared buses. |
| 30 | - xilinx zynq qspi controller has implemented this feature [1] |
| 31 | |
| 32 | +------------+ CS +---------------+ |
| 33 | | |---------------------->| | |
| 34 | | | I0[3:0] | Upper Flash | |
| 35 | | | +=========>| memory | |
| 36 | | | | CLK | (SPI/QSPI) | |
| 37 | | | | +---->| | |
| 38 | | Controller | CS | | +---------------+ |
| 39 | | SPI/QSPI |------------|----|---->| | |
| 40 | | | I0[3:0] | | | Lower Flash | |
| 41 | | |<===========+====|====>| memory | |
| 42 | | | CLK | | (SPI/QSPI) | |
| 43 | | |-----------------+---->| | |
| 44 | +------------+ +---------------+ |
| 45 | |
| 46 | - two memory flash devices should has same hw part attributes (like size, |
| 47 | vendor..etc) |
| 48 | - Configurations: |
| 49 | on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG |
| 50 | Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory |
| 51 | Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory |
| 52 | - Operation: |
| 53 | accessing memories serially like one after another. |
| 54 | by default, if U_PAGE is unset lower memory should accessible, |
| 55 | once user wants to access upper memory need to set U_PAGE. |
| 56 | |
| 57 | Note: Technically there is only one CS line from the controller, but |
| 58 | zynq qspi controller has an internal hw logic to enable additional CS |
| 59 | when controller is configured for dual memories. |
| 60 | |
| 61 | [1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf |
| 62 | |
| 63 | -- |
| 64 | Jagannadha Sutradharudu Teki <jaganna@xilinx.com> |
| 65 | 05-01-2014. |